74AC11646_09 [TI]
OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS;
| 型号： | 74AC11646_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总9页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
DW PACKAGE
(TOP VIEW)
• Independent Registers for A and B Buses
• Multiplexed Real-Time and Stored Data
• Flow-Through Architecture Optimizes
OE
A1
A2
A3
A4
GND
GND
GND
GND
CLKAB
SAB
B1
B2
B3
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
PCB Layout
• Center-Pin V
and GND Configurations
Minimize High-Speed Switching Noise
CC
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
B4
V
CC
• 500-mA Typical Latch-Up Immunity
at 125°C
V
CC
B5
A5 10
19 B6
description
A6
A7
B7
B8
11
12
18
17
The 74AC11646 consists of bus transceiver
circuits, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of
the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-
managementfunctionsthatcanbeperformedwith
the 74AC11646.
A8 13
16 CLKBA
15 SBA
DIR 14
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
The 74AC11646 is characterized for operation from –40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
1
OE
L
14
28
16
27
15
SBA
1
OE
L
14
DIR
28
16
27
15
SBA
DIR CLKAB CLKBA SAB
CLKAB CLKBA SAB
L
X
X
X
L
H
X
X
L
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
1
14
28
16
27
15
1
OE
L
14
DIR
L
28
16
27
15
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
X
L
L
X
H
X
H
X
X
L
H
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
FUNCTION TABLE
DATA I/O
INPUTS
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1 THRU A8
B1 THRU B8
↑
X
↑
†
†
Input
Unspecified
Input
Store A, B unspecified
†
†
Unspecified
Store B, A unspecified
X
X
↑
X
X
X
↑
X
X
Input
Input
Store A and B data
Input disabled
Input disabled
Isolation, hold storage
X
L
X
X
X
L
L
X
L
X
X
X
X
L
X
L
Output
Output
Input
Input
Real-time B data to A bus
Stored B data to A bus
L
L
X
H
L
H
H
L
X
Input
Input
Output
Output
Real-time A data to B bus
Stored A data to B bus
L
H
X
†
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
‡
logic symbol
1
G3
OE
14
DIR
3 EN1 [BA]
3 EN2 [AB]
16
CLKBA
C4
G5
15
28
27
SBA
CLKAB
SAB
C6
G7
20
25
4D
B1
B2
5
5
≥1
1
2
3
A1
A2
1
6D
7
7
≥1
2
1
4
5
24
23
A3
A4
B3
B4
10
11
12
20
19
18
A5
A6
A7
B5
B6
B7
13
17
A8
B8
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
logic diagram (positive logic)
1
OE
14
DIR
16
CLKBA
15
SBA
28
CLKAB
27
SAB
One of Eight
Channels
1D
C1
2
A1
26
B1
1D
C1
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
4.5 V
5.5 V
3 V
2.9
4.4
I
I
= – 50 µA
4.4
OH
5.4
5.4
V
OH
= – 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= – 24 mA
= –75 mA
OH
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
I
Control pins
A or B ports
V = V
or GND
±0.1
±0.5
8
µA
µA
µA
pF
pF
I
I
CC
‡
V
= V or GND
CC
±5
OZ
CC
O
V = V
or GND,
or GND
I = 0
O
80
I
CC
CC
C
C
OE or DIR
V = V
4.5
12
i
I
A or B ports
V
= V or GND
CC
5 V
io
O
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 3.3 V ± 0.3 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
65
0
7.7
6.5
1
65
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
7.7
6.5
1
w
ns
su
h
ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 2)
= 5 V ± 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MIN
0
MAX
f
t
t
t
Clock frequency
100
0
5
100
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, A or B before CLKAB↑ or CLKBA↑
Hold time, A or B after CLKAB↑ or CLKBA↑
5
w
4.5
1
4.5
1
ns
su
h
ns
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
65
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
65
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
max
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
9.1
10.7
13
12.1
13.4
16.4
20.4
9.6
13.8
14.5
18.7
21.8
10.3
9.6
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
ns
OE
OE
16.1
7.9
7.2
8.9
11.8
13.7
9.8
15
17
CLKBA or CLKAB
16.8
12.9
14.5
13.8
15
18.3
14.4
15.8
15.4
16.4
19.4
23.6
10.5
9.9
†
SBA or SAB
(A or B high)
12
†
10.7
12.4
13.7
16.8
7.9
SBA or SAB
(A or B low)
17.1
21
DIR
DIR
9.7
7.3
9.1
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
100
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
TYP
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
100
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
max
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
5.5
6.3
7.8
8.5
5.9
5.9
7
7.9
8.9
8.8
9.8
A or B
B or A
A or B
A or B
A or B
A or B
A or B
A or B
A or B
10.7
11.9
8.4
12
ns
ns
ns
ns
ns
ns
ns
OE
OE
13.1
8.9
7.7
8.3
9.7
11
CLKBA or CLKAB
8.2
5.9
7.2
6.3
7.3
8.4
9.1
6.3
5.7
11
12.2
9.4
†
8.4
SBA or SAB
(A or B high)
9.8
10.7
9.9
†
8.9
SBA or SAB
(A or B low)
9.9
11
11.2
12.3
8.2
12.6
13.7
8.7
DIR
DIR
7.5
8.1
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
Outputs enabled
Outputs disabled
59
15
C
Power dissipation capacitance per transceiver
C
pF
pd
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11646
OCTAL BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCAS079A – JULY 1987 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
t
t
/t
Open
PLH PHL
/t
C
= 50 pF
t
2 × V
CC
GND
L
500 Ω
PLZ PZL
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
V
CC
Timing Input
(see Note B)
50%
0 V
t
w
t
h
t
V
CC
su
V
CC
Input
50%
50%
50%
50%
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
V
V
CC
CC
Input
(see Note B)
50%
50%
50%
50%
0 V
0 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note C)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note C)
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
74AC11648D
Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO28,
YAGEO
74AC11648D-T
Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO28,
YAGEO
74AC11648DNT
AC SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP28, 0.300 INCH, PLASTIC, DIP-28
TI
74AC11648N
Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP28
YAGEO
74AC11651D
Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO28
YAGEO
74AC11651D-T
Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO28
YAGEO
74AC11651N
Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDIP28,
YAGEO
©2020 ICPDF网 联系我们和版权申明