74AC11174J [TI]
IC,FLIP-FLOP,HEX,D TYPE,AC-CMOS,DIP,20PIN,CERAMIC;型号: | 74AC11174J |
厂家: | TEXAS INSTRUMENTS |
描述: | IC,FLIP-FLOP,HEX,D TYPE,AC-CMOS,DIP,20PIN,CERAMIC 触发器 |
文件: | 总7页 (文件大小:88K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74AC11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 – MARCH 1990 – REVISED APRIL 1993
DW OR N PACKAGE
(TOP VIEW)
• Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
1Q
2Q
CLR
1D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
• Flow-Through Architecture Optimizes
PCB Layout
3Q
2D
• Center-Pin V
and GND Pin Configurations
Minimize High-Speed Switching Noise
CC
GND
GND
GND
GND
4Q
3D
V
CC
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
V
CC
4D
13 5D
12 6D
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
5Q
11
6Q
CLK
description
This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at
the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect
at the output.
The 74AC11174 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLR
L
CLK
D
X
H
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
O
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 – MARCH 1990 – REVISED APRIL 1993
†
logic symbol
logic diagram (positive logic)
20
20
R
CLR
CLK
CLR
11
C1
19
18
17
14
13
12
1
2
11
1D
2D
3D
4D
5D
6D
1D
1Q
2Q
3Q
4Q
5Q
6Q
CLK
19
3
1D
2D
3D
4D
1D
C1
1
2
3
8
9
8
1Q
2Q
3Q
4Q
9
R
10
18
17
14
1D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
C1
R
1D
C1
R
1D
C1
R
13
12
1D
5D
6D
C1
5Q
6Q
R
1D
10
C1
R
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 – MARCH 1990 – REVISED APRIL 1993
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage
3
2.1
5
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
V
High-level input voltage
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
V
V
0.9
1.35
1.65
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
V
V
Input voltage
0
0
V
V
V
I
CC
Output voltage
V
CC
–4
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
High-level output current
Low-level output current
= 4.5 V
= 5.5 V
= 3 V
–24
–24
12
mA
mA
OH
OL
I
= 4.5 V
= 5.5 V
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
CC
MIN
2.9
TYP
MAX
3 V
4.5 V
5.5 V
3 V
2.9
4.4
I
I
= – 50 µA
4.4
OH
5.4
5.4
V
OH
= – 4 mA
2.58
3.94
4.94
2.48
3.8
V
OH
4.5 V
5.5 V
5.5 V
3 V
I
I
= – 24 mA
= –75 mA
OL
4.8
†
3.85
OH
0.1
0.1
0.1
0.1
I
= 50 µA
4.5 V
5.5 V
3 V
OL
0.1
0.1
V
OL
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.36
0.44
0.44
0.44
1.65
±1
V
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5 V
†
= 75 mA
I
I
V = V
or GND
or GND,
or GND
±0.1
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
8
80
CC
I
C
V = V
4
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 – MARCH 1990 – REVISED APRIL 1993
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MHz
ns
MIN
0
MAX
f
t
Clock frequency
Pulse duration
80
0
4.5
6
80
clock
CLR low
4.5
6
w
CLK high or low
Data
7
7
t
t
Setup time before CLK↑
Hold time after CLK↑
ns
ns
su
CLR inactive
1.5
0
1.5
0
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
A
MIN
MAX
UNIT
MHz
ns
MIN
0
MAX
f
t
Clock frequency
Pulse duration
100
0
4
100
clock
CLR low
4
w
CLK high or low
Data
5
5
4.5
1.5
0
4.5
1.5
0
t
t
Setup time before CLK↑
Hold time after CLK↑
ns
ns
su
CLR inactive
h
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
80
MAX
f
t
105
80
3.9
2.4
3.4
MHz
ns
max
Any Q
Any Q
3.9
2.4
3.4
10
7.5
9.6
13.5
9.2
14.8
10.8
14
CLR
CLK
PHL
PLH
PHL
t
t
ns
12.7
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
MIN
100
2.9
MAX
f
t
125
100
2.9
2.1
2.7
MHz
ns
max
Any Q
Any Q
6.5
4.9
6.2
9.8
6.8
9.2
10.7
7.6
CLR
CLK
PHL
PLH
PHL
t
t
2.1
ns
2.7
10.1
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
C
29
pF
pd
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
74AC11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS146 – MARCH 1990 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
t
w
V
CC
C
= 50 pF
L
500 Ω
(see Note A)
Input
50%
50%
0 V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
V
CC
Input
(see Note B)
50%
50%
0 V
V
CC
Timing Input
(see Note B)
t
t
PHL
PLH
50%
V
OH
0 V
In-Phase
Output
50% V
CC
t
50% V
50% V
h
CC
t
V
OL
su
V
CC
t
PLH
t
50%
50%
PHL
Data Input
0 V
V
OH
Out-of-Phase
Output
50% V
CC
CC
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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