74ABTE16245DGGRG4 [TI]
ABTE/ETL SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48;
| 型号： | 74ABTE16245DGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABTE/ETL SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, GREEN, PLASTIC, TSSOP-48 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总9页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
SN54ABTE16245 . . . WD PACKAGE
SN74ABTE16245 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Support the VME64 ETL Specification
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Reduced, TTL-Compatible, Input Threshold
Range
1DIR
1B1
2B1
GND
1B2
2B2
V
1A1
2A1
GND
1A2
2A2
BIAS
CC
2
3
High-Drive Outputs (I
= –60 mA,
OH
4
I
= 90 mA) Support 25-Ω Incident-Wave
OL
5
Switching
6
V
BIAS Pin Minimizes Signal Distortion
CC
7
V
V
CC
CC
During Live Insertion
8
1B3
2B3
GND
1B4
2B4
1B5
2B5
GND
1B6
2B6
1A3
2A3
GND
1A4
2A4
1A5
2A5
GND
1A6
2A6
Internal Pullup Resistor on OE Keeps
Outputs in High-Impedance State During
Power Up or Power Down
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Equivalent 25-Ω Series Damping Resistor
on B Port
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
V
CC
CC
1B7
2B7
GND
1B8
2B8
1A7
2A7
GND
1A8
2A8
OE
description
The ’ABTE16245 devices are 16-bit (dual-octal)
noninverting 3-state transceivers designed for
synchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements. These
devices can be used as two 8-bit transceivers or
2DIR
one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to
disable the device so that the buses are effectively isolated. When OE is low, the device is active.
The B port has an equivalent 25-Ω series output resistor to reduce ringing. Active bus-hold inputs also are on
the B port to hold unused or floating inputs at a valid logic level.
The A port provides for the precharging of the outputs via V BIAS, which establishes a voltage between 1.3 V
CC
and 1.7 V when V
is not connected.
CC
Activebus-holdcircuitryholdsunusedorundriveninputsatavalidlogicstate. Useofpulluporpulldownresistors
with the bus-hold circuitry is not recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74ABTE16245DL
SN74ABTE16245DLR
SN74ABTE16245DGGR
Tube
SSOP – DL
ABTE16245
–40°C to 85°C
Tape and reel
TSSOP – DGG Tape and reel
–55°C to 125°C CFP – WD Tube
ABTE16245
SNJ54ABTE16245WD
SNJ54ABTE16245WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
DIR
L
OE
L
A data to B bus
B data to A bus
Isolation
L
H
H
X
logic diagram (positive logic)
1
24
1DIR
2DIR
25
OE
2
3
1B1
2B1
46
47
2A1
1A1
To Seven Other Channels
To Seven Other Channels
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and V BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
recommended operating conditions (see Note 3)
SN54ABTE16245
MIN NOM MAX
SN74ABTE16245
MIN NOM MAX
UNIT
V
V
CC
V
CC
,
Supply voltage
4.5
5
5.5
4.5
5
5.5
BIAS
OE
2
2
V
High-level input voltage
V
IH
Except OE
OE
1.6
1.6
0.8
1.4
0.8
1.4
V
V
Low-level input voltage
Input voltage
V
V
IL
Except OE
0
V
0
V
CC
I
CC
B bus
–12
–24
12
–12
–60
12
I
High-level output current
mA
OH
A bus
B bus
I
Low-level output current
mA
OL
A bus
64
90
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
Outputs enabled
10
10
ns/V
T
A
–55
125
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTE16245
SN74ABTE16245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
= 5.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –1 mA
= –12 mA
= –1 mA
= –32 mA
= –64 mA
= 1 mA
V
CC
–0.2
V –0.2
CC
CC
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
B port
A port
2.4
2
2.4
2
V
CC
V
CC
V
CC
= 4.5 V
= 5.5 V,
= 4.5 V
V
OH
V
V
4.5
4.5
2.4
2.4
2
0.4
0.4
0.8
B port
A port
V
= 4.5 V
= 4.5 V
CC
CC
= 12 mA
= 64 mA
= 90 mA
V
OL
0.55
0.55
0.9
V
V = 0.8 V
100
100
I
V
V
V
= 4.5 V
= 5.5 V,
= 5.5 V,
CC
CC
CC
I
I
B port
V = 2 V
I
–100
–100
µA
µA
I(hold)
V = 0 to 5.5 V
I
±500
±1
±500
±1
Control inputs
A or B ports
A port
V = V
I CC
or GND
I
±20
10
±20
10
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V
V
= 2.7 V
= 0.5 V
µA
µA
OZH
CC
O
‡
A port
–10
–180
–90
±100
36
–10
–180
–90
±100
36
OZL
CC
O
A port
–50
–25
–120
–52
–50
–25
I
O
V
= 5.5 V,
V
O
= 2.5 V
mA
CC
CC
B port
I
off
V
= 0, V or V ≤ 4.5 V, V BIAS = 0
µA
I
O
CC
Outputs high
28
38
28
38
V
= 5.5 V, I = 0,
O
or GND
CC
CC
I
A or B ports
A or B ports
Outputs low
Outputs disabled
OE high
48
48
mA
CC
V = V
I
20
32
20
32
0.02
0.33
0.02
0.33
2.5
V
C
= 5 V,
= 50 pF
mA/
MHz
CC
I
CCD
OE low
L
C
C
Control inputs V = 2.5 V or 0.5 V
10
13
4
8
pF
pF
i
I
I/O ports
V
O
= 2.5 V or 0.5 V
4.5
io
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
OZL
CC
and I
The parameters I
include the input leakage current.
OZH
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
live-insertion specifications over recommended operating free-air temperature range
SN54ABTE16245
SN74ABTE16245
PARAMETER
TEST CONDITIONS
UNIT
µA
†
†
MIN TYP
MAX
MIN TYP
MAX
V
= 0 to 4.5 V, V BIAS = 4.5 V to 5.5 V,
CC
CC
250
700
250
700
I
= 0
O(DC)
I
(V BIAS)
CC CC
‡
V
= 4.5 V to 5.5 V , V BIAS = 4.5 V to 5.5 V,
CC
CC
20
20
I
= 0
O(DC)
V
V
BIAS = 4.5 V to 5.5 V
1.1
1.3
–20
20
1.5
1.5
1.9
1.7
1.1
1.3
–20
20
1.5
1.5
1.9
1.7
CC
V
A port
A port
V
= 0
V
O
CC
CC
BIAS = 4.75 V to 5.25 V
CC
V
= 0
–100
100
–100
100
µA
µA
O
O
I
O
V
= 0,
CC
V
CC
BIAS = 4.5 V
V
= 3 V
†
‡
All typical values are at V
– 0.5 V < V BIAS
= 5 V, T = 25°C.
A
V
CC
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABTE16245 SN74ABTE16245
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.5
1.5
1.5
2
TYP
3.3
3.8
3
MAX
4.2
4.6
3.8
4
MIN
1.5
1.5
1.5
1.5
2
MAX
5.4
5.4
4.7
4.7
6.4
7
MIN
1.5
1.5
1.5
1.5
2
MAX
5.2
5.2
4.5
4.5
6.2
6.8
7.1
7.3
6.7
5.1
7
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
B
3.1
3.9
4.4
4.5
5
5.3
5.9
6
OE
OE
OE
OE
2
2
2
2
2
7.3
7.5
7
2
2
6.4
5.9
4.6
6.2
5
2
2
2
4.9
3.7
5.2
4
2
2
2
2
5.4
7.2
5.8
2
2
2
2
2
2
2
5.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
extended switching characteristics over recommended ranges of supply voltage and operating
free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 2)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABTE16245 SN74ABTE16245
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
LOAD
UNIT
MIN
1.5
1.5
1.5
1.5
1.5
1.5
TYP
3.2
3.8
3.1
3.5
3
MAX
4
MIN
1.5
1.5
1.5
1.5
1.5
1.5
MAX
5
MIN
1.5
1.5
1.5
1.5
1.5
1.5
MAX
4.8
5.6
4.6
4.9
4.5
4.7
2
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
B
B
B
A
A
A
R
R
R
= 13 Ω
ns
ns
ns
X
X
X
4.7
4
5.8
4.8
5.2
4.7
5.1
2
= 26 Ω
= 56 Ω
4.4
3.8
4.2
0.6
0.8
0.8
0.7
1.1
1
3.3
0.1
0.4
0.3
0.3
0.7
0.5
0.8
5.5
B
A
B
B
A
B
B
A
A
B
A
A
B
A
A
B
R
R
= Open
= Open
= 26 Ω
= Open
= Open
= 26 Ω
= 26 Ω
= Open
X
X
2
2
ns
ns
t
sk(p)
sk(o)
R
2
2
X
X
X
R
R
1.3
1.3
1.3
1.5
8.1
1.3
1.3
1.3
1.5
7.9
t
R
X
X
X
†
t
t
R
0.5
3.5
1.5
7.3
0.5
3.5
0.5
3.5
ns
ns
t
‡
R
t
†
‡
t is measured between 1 V and 2 V of the output waveform.
t is measured between 10% and 90% of the output waveform.
t
t
extended output characteristics over recommended ranges of supply voltage and operating
free-air temperature, C = 50 pF (see Figures 1 and 2)
L
SN54ABTE16245 SN74ABTE16245
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
LOAD
UNIT
MIN
MAX
3
MIN
MAX
2.5
4
A
B
B
A
V
= constant,
CC
∆T = 20°C
t
t
ns
ns
sk(temp)
R
= 56 Ω
4.5
A
X
V
= constant,
R = 13, 26,
X
or 56 Ω
CC
B
B
4.5
4
sk(load)
Temperature = constant
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
Device 1
A
B
Y1
A
Y2
Yn
Device
1 – Y1
t
sk(o)
sk(load)
t
t
PHL1
t
PLH1
In
B
t
Device n
sk(temp)
Device
1 – Yn
Y1
t
PLH2
Device
n – Yn
Y2
Yn
NOTES: A. Pulse skew, t
, is defined as the difference in propagation-delay times t
and t
on the same terminal at identical
PHL1
sk(p)
PLH1
operating conditions.
B. Output skew, t , is defined as the difference in propagation delay of any two outputs of the same device switching in the same
sk(o)
direction (e.g., |t
– t
|).
PLH1 PLH2
C. Temperature skew, t
, is the output skew of two devices, both having the same value of V
± 1% and with package
CC
sk(temp)
temperature differences of 20°C.
D. Load skew, t , is measured with R in Figure 2 at 13 for one unit and 56 for the other unit.
sk(load)
X
Figure 1. Voltage Waveforms for Extended Characteristics
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTE16245, SN74ABTE16245
16-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS226J – JULY 1993 – REVISED DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
SWITCHING TABLE
LOADS
(A and B port)
S1
S2
S2
Open
Up
Up
Up
Open
7 V
Open
t
/t
PLH PHL
t
/t
PLZ PZL
500 Ω
3.65 V
t
/t
PHZ PZH
94 Ω
EXTENDED
SWITCHING TABLE
LOADS
S1
†
R
X
S1
S2
From Output
Under Test
Down
Up
Down
Up
X
Open
X
t
t
/t
/t (A port)
C
= 50 pF
PLH PHL sk
L
2 nF
500 Ω
/t /t (B port)
(see Note A)
PLH PHL sk
t (A port) (see Note E)
t
Open
t (B port) (see Note F)
t
†
R
=13, 26, or56Ω
X
3 V
0 V
Output
Control
(low-level
enabling)
LOAD CIRCUIT FOR OUTPUTS
1.5 V
1.5 V
t
t
PZL
PLZ
Output
Waveform 1
S2 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
(see Note B)
t
t
t
t
PLH
PHL
PZH
PHZ
Output
Waveform 2
S2 at Open
(see Note B)
V
OH
V
OH
OL
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈0 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. t is measured between 1 V and 2 V of the output waveform.
t
F. t is measured between 10% and 90% of the output waveform.Figure 1
t
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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