74ABT162841DGGRG4 [TI]
ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56;
| 型号： | 74ABT162841DGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS665C − JUNE 1996 − REVISED JUNE 2004
SN54ABT162841 . . . WD PACKAGE
SN74ABT162841 . . . DGG OR DL PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
WidebusE Family
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
2
3
D
D
D
D
D
D
Typical V
<0.8 V at V
(Output Ground Bounce)
= 5 V, T = 25°C
A
OLP
CC
4
5
High-Impedance State During Power Up
and Power Down
6
7
V
V
CC
CC
I
and Power-Up 3-State Support Hot
off
8
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
Insertion
9
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
description/ordering information
These 20-bit transparent D-type latches feature
noninverting 3-state outputs designed specifically
for driving highly capacitive or relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
V
V
CC
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
2D7
2D8
GND
2D9
2D10
2LE
The ’ABT162841 devices can be used as two
10-bit latches or one 20-bit latch. While the
latch-enable (1LE or 2LE) input is high, the Q
outputs of the corresponding 10-bit latch follow
the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D
inputs.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube
SN74ABT162841DL
SN74ABT162841DLR
SN74ABT162841DGGR
SNJ54ABT162841WD
SSOP − DL
ABT162841
Tape and reel
Tape and reel
Tube
−40°C to 85°C
−55°C to 125°C
TSSOP − DGG
CFP − WD
ABT162841
SNJ54ABT162841WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢃꢇ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢃꢇ
ꢉꢍ ꢎꢅꢏ ꢆ ꢅ ꢐ ꢀꢎꢏ ꢁꢆ ꢑ ꢒꢓꢄꢔ ꢑ ꢕꢎꢆ ꢖꢗ ꢑ ꢘꢄꢆꢔ ꢙ ꢑꢀ
ꢚꢏ ꢆ ꢙ ꢛ ꢎꢀꢆꢄꢆ ꢑ ꢜꢐꢆ ꢗ ꢐꢆꢀ
SCBS665C − JUNE 1996 − REVISED JUNE 2004
description/ordering information (continued)
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE shall be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢚ ꢏꢆ ꢙ ꢛ ꢎꢀꢆꢄꢆ ꢑ ꢜ ꢐꢆ ꢗꢐ ꢆ
SCBS665C − JUNE 1996 − REVISED JUNE 2004
logic diagram (positive logic)
1
28
29
1OE
2OE
2LE
56
1LE
C1
C1
1D
2
15
1Q1
2Q1
55
42
1D
1D1
2D1
To Nine Other Channels
To Nine Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ABT162841 SN74ABT162841
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
−3
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
−12
12
mA
mA
ns/V
µs/V
°C
OH
8
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢃꢇ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢃꢇ
ꢉꢍ ꢎꢅꢏ ꢆ ꢅ ꢐ ꢀꢎꢏ ꢁꢆ ꢑ ꢒꢓꢄꢔ ꢑ ꢕꢎꢆ ꢖꢗ ꢑ ꢘꢄꢆꢔ ꢙ ꢑꢀ
ꢚꢏ ꢆ ꢙ ꢛ ꢎꢀꢆꢄꢆ ꢑ ꢜꢐꢆ ꢗ ꢐꢆꢀ
SCBS665C − JUNE 1996 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162841 SN74ABT162841
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = −18 mA
−1.2
−1.2
−1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= −1 mA
= −1 mA
= −3 mA
= −12 mA
= 8 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2.4
2*
2.4
2.4
2
V
= 4.5 V
= 4.5 V
CC
CC
0.4
0.8*
100
0.8
0.65
0.8
V
V
V
V
OL
= 12 mA
mV
µA
hys
V
= 0 to 5.5 V,
CC
I
I
I
I
I
1
50
1
50
1
50
I
V = V
I
or GND
CC
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
CC
O
µA
µA
µA
µA
OZPU
OZPD
OZH
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
50
50
50
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V
CC
O
10
10
10
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V
CC
O
−10
−10
−10
OZL
I
I
I
V
V
V
= 0,
V or V ≤ 4.5 V
100
50
100
50
µA
µA
off
CC
CC
CC
I
O
Outputs high
= 5.5 V,
= 5.5 V,
V
= 5.5 V
50
−100
0.5
CEX
O
O
‡
V
= 2.5 V
−25
−75 −100
−25
−25
−100
0.5
mA
O
Outputs high
Outputs low
0.5
89
V
= 5.5 V, I = 0,
O
CC
CC
89
89
I
mA
CC
V = V
or GND
I
Outputs disabled
0.5
0.5
0.5
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
§
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
9
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162841 SN74ABT162841
UNIT
MIN
4
MAX
MIN
4
MAX
MIN
4
MAX
t
w
t
su
t
h
Pulse duration, LE high or low
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
0.8
1.8
0.8
1.8
0.8
1.8
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ꢨ
ꢦ
ꢨ
ꢧ
ꢦ
ꢡ
ꢢ
ꢝ
ꢞ
ꢝ
ꢦ
ꢪ
ꢠ
ꢫ
ꢟ
ꢩ
ꢟ
ꢣ
ꢨ
ꢝ
ꢟ
ꢢ
ꢪ
ꢦ
ꢡ
ꢦ
ꢤ
ꢠ
ꢟ
ꢲ
ꢠ
ꢮ
ꢨ
ꢝ
ꢠ
ꢏ
ꢪ
ꢤ
ꢦ
ꢠ
ꢦ
ꢠ
ꢝ
ꢞ
ꢪ
ꢟ
ꢲ
ꢞ
ꢝ
ꢢ
ꢣ
ꢞ
ꢲ
ꢦ
ꢢ
ꢪ
ꢟ
ꢠ
ꢧ
ꢝꢟ
ꢧ
ꢦ
ꢝ
ꢞ
ꢦ
ꢪ
ꢢ
ꢠ
ꢰ
ꢢ
ꢤ
ꢝ
ꢟ
ꢦ
ꢮ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢃ
ꢇ
ꢋ
ꢀ
ꢁ
ꢌ
ꢃ
ꢉ ꢍ ꢎꢅꢏ ꢆ ꢅꢐꢀ ꢎꢏꢁꢆ ꢑꢒꢓꢄꢔꢑ ꢕꢎꢆ ꢖꢗ ꢑ ꢘꢄꢆꢔ ꢙ ꢑ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢊ
ꢃ
ꢇ
ꢀ
ꢀ
ꢚ ꢏꢆ ꢙ ꢛ ꢎꢀꢆꢄꢆ ꢑ ꢜ ꢐꢆ ꢗꢐ ꢆ
SCBS665C − JUNE 1996 − REVISED JUNE 2004
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162841 SN74ABT162841
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2.1
3
TYP
3.5
4.3
3.5
4.1
3.6
4.6
4.3
3.6
MAX
4.5
5.3
4.5
5.1
4.7
5.7
5.7
5.8
MIN
2.1
3
MAX
5.7
6.2
5.6
6.1
5.8
6.7
6.6
8.4
MIN
2.1
3
MAX
5.2
6
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
2.1
2.8
2
2.1
2.8
2
2.1
2.8
2
5.4
5.8
5.7
6.5
6.5
7.1
LE
OE
OE
3
3
3
2.6
2.2
2.6
2.2
2.6
2.2
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢃꢇ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢃꢇ
ꢉꢍ ꢎꢅꢏ ꢆ ꢅ ꢐ ꢀꢎꢏ ꢁꢆ ꢑ ꢒꢓꢄꢔ ꢑ ꢕꢎꢆ ꢖꢗ ꢑ ꢘꢄꢆꢔ ꢙ ꢑꢀ
ꢚꢏ ꢆ ꢙ ꢛ ꢎꢀꢆꢄꢆ ꢑ ꢜꢐꢆ ꢗ ꢐꢆꢀ
SCBS665C − JUNE 1996 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
S1
Open
S1
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
7 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
74ABT162841DGGRE4
74ABT162841DGGRG4
74ABT162841DLRG4
SN74ABT162841DGGR
SN74ABT162841DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
TSSOP
SSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ABT162841DLG4
SN74ABT162841DLR
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ABT162841DGGR TSSOP
SN74ABT162841DLR SSOP
DGG
DL
56
56
2000
1000
330.0
330.0
24.4
32.4
8.6
15.6
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35
18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ABT162841DGGR
SN74ABT162841DLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
346.0
346.0
346.0
346.0
41.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
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