74ABT16373 [FAIRCHILD]
16-Bit Transparent D-Type Latch with 3-STATE Outputs; 16位透明D类锁存器具有三态输出
| 型号： | 74ABT16373 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Transparent D-Type Latch with 3-STATE Outputs |
| 文件： | 总6页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1994
Revised May 2005
74ABT16373
16-Bit Transparent D-Type Latch with 3-STATE Outputs
General Description
Features
The ABT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
■ Separate control logic for each byte
■ 16-bit version of the ABT373
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
■ Guaranteed latch-up protection
Ordering Code:
Order Number
74ABT16373CSSC
74ABT16373CMTD
Package Number
MS48A
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD48
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Latch Enable Input
Data Inputs
LEn
D0–D15
O0–O15
Outputs
© 2005 Fairchild Semiconductor Corporation
DS011666
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Functional Description
Truth Tables
The ABT16373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
Inputs
OE1
Outputs
O0–O7
LE1
D0–D7
X
H
H
L
H
L
L
L
X
L
Z
L
H
the Dn enters the latches. In this condition the latches are
H
X
transparent, i.e., a latch output will change states each time
its D input changes. When LEn is LOW, the latches store
(Previous)
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LEn. The 3-
Inputs
OE2
Outputs
O8–O15
STATE standard outputs are controlled by the Output
Enable (OEn) input. When OEn is LOW, the standard out-
LE2
D8–D15
puts are in the 2-state mode. When OEn is HIGH, the stan-
X
H
H
L
H
L
L
L
X
L
Z
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
L
H
H
X
(Previous)
H
L
X
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
65 C to 150 C
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
55 C to 125 C
55 C to 150 C
0.5V to 7.0V
Free Air Ambient Temperature
Supply Voltage
40 C to 85 C
4.5V to 5.5V
Minimum Input Edge Rate ( V/ t)
Data Input
0.5V to 7.0V
50 mV/ns
20 mV/ns
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
30 mA to 5.0 mA
Enable Input
Power-Off State
0.5V to 5.5V
0.5V to VCC
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
350 mA
DC Latchup Source Current: OE Pin
(Across Comm Operating Range)
Other Pins
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
500 mA
10V
Over Voltage Latchup (I/O)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
V
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
Conditions
Recognized HIGH Signal
Recognized LOW Signal
CC
V
2.0
V
V
V
IH
V
V
V
Input LOW Voltage
0.8
1.2
IL
Input Clamp Diode Voltage
Output HIGH Voltage
Min
Min
Min
Max
Max
Max
0.0
I
I
I
I
18 mA
3 mA
CD
OH
IN
2.5
2.0
OH
OH
OL
32 mA
V
Output LOW Voltage
Input HIGH Current
0.55
V
A
A
A
V
64 mA
OL
I
1
1
7
1
1
V
V
V
V
V
2.7V (Note 3)
IH
IN
IN
IN
IN
IN
V
CC
I
I
Input HIGH Current Breakdown Test
Input LOW Current
7.0V
BVI
IL
0.5V (Note 3)
0.0V
V
Input Leakage Test
4.75
100
I
1.9
A
ID
ID
All Other Pins Grounded
I
Output Leakage Current
10
A
0
0
5.5V
5.5V
Max
V
2.7V; OE 2.0V
OZH
OUT
I
I
I
I
I
I
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
10
275
50
A
mA
A
V
V
V
V
0.5V; OE 2.0V
0.0V
OZL
OS
OUT
OUT
OUT
OUT
Max
0.0
V
CC
CEX
ZZ
100
2.0
62
A
5.5V; All Others GND
Power Supply Current
Power Supply Current
mA
mA
Max
Max
All Outputs HIGH
All Outputs LOW
CCH
CCL
I
Power Supply Current
2.0
mA
Max
OE
V
CC
CCZ
All Others at V or GND
CC
I
Additional I /Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
2.5
2.5
2.5
mA
mA
mA
V
V
2.1V
CCT
CC
I
CC
Max
Enable Input V
V
2.1V
2.1V
All Others at V or GND
I
CC
CC
CC
Data Input V
V
I
I
Dynamic I
(Note 3)
No Load
mA/
Outputs Open, LE
V
CC
CCD
CC
Max
0.15
MHz
OE GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, I 0.8 mA/MHz.
CCD
3
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AC Electrical Characteristics
(SOIC and SSOP Packages)
T
25 C
5.0V
T
40 C to 85 C
4.5V to 5.5V
A
A
V
V
CC
CC
Symbol
Parameter
Units
C
50 pF
C
50 pF
Max
L
L
Min
1.4
1.4
1.7
1.7
1.1
1.5
2.4
1.6
Typ
Max
5.6
5.6
6.0
5.5
6.1
5.6
7.1
6.5
Min
1.4
1.4
1.7
1.7
1.1
1.5
2.4
1.6
t
t
t
t
t
t
t
t
Propagation Delay
to O
5.6
5.6
6.0
5.5
6.1
5.6
7.1
6.5
PLH
ns
ns
ns
ns
D
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
n
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
AC Operating Requirements
(SOIC and SSOP Packages)
T
25 C
5.0V
T
40 C to 85 C
4.5V to 5.5V
A
A
V
V
CC
CC
Symbol
Parameter
Units
C
50 pF
C
50 pF
Max
L
L
Min
Typ
100
Max
Min
f
Maximum Toggle Frequency
Setup Time, HIGH
MHz
ns
TOGGLE
t (H)
1.5
1.5
1.0
1.0
1.5
1.5
1.0
1.0
S
t (L)
or LOW D to LE
n
S
t (H)
Hold Time, HIGH
H
ns
ns
t (L)
or LOW D to LE
n
H
t
(H)
Pulse Width,
LE HIGH
W
3.0
3.0
Capacitance
Conditions
(T 25 C)
Symbol
Parameter
Typ
Units
A
C
C
Input Capacitance
Output Capacitance
5
pF
pF
V
V
0V
5.0V
IN
CC
CC
(Note 5)
11
OUT
Note 5: C
is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
OUT
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4
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
相关型号：
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IC ABT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 6.10 MM, PLASTIC, SOT-362-1, TSSOP2-48, Bus Driver/Transceiver
NXP
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