5962-9762101Q2A [TI]
HIGH SPEED DIFFERENTIAL LINE DRIVERS; 高速差分线路驱动器
| 型号： | 5962-9762101Q2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH SPEED DIFFERENTIAL LINE DRIVERS |
| 文件： | 总33页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
SN55LVDS31 . . . J OR W
SN65LVDS31 . . . D OR PW
(Marked as LVDS31 or 65LVDS31)
D
D
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and
100-Ω Load
Typical Output Voltage Rise and Fall Times
of 500 ps (400 Mbps)
(TOP VIEW)
1A
1Y
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
4A
4Y
4Z
G
D
D
D
D
1Z
G
Typical Propagation Delay Times of 1.7 ns
Operate From a Single 3.3-V Supply
2Z
2Y
11 3Z
10 3Y
2A
Power Dissipation 25 mW Typical Per
Driver at 200 MHz
GND
9
3A
D
Driver at High Impedance When Disabled or
SN55LVDS31FK
(TOP VIEW)
With V
= 0
CC
D
Bus-Terminal ESD Protection Exceeds 8 kV
D
Low-Voltage TTL (LVTTL) Logic Input
Levels
3
2
1
20 19
D
Pin Compatible With AM26LS31, MC3487,
and µA9638
1Z
4Y
4Z
NC
G
4
5
6
7
8
18
G
NC
2Z
17
16
15
14
description
The
SN55LVDS31,
SN65LVDS31,
2Y
3Z
SN65LVDS3487, and SN65LVDS9638 are
differential line drivers that implement the
electrical characteristics of low-voltage differential
signaling (LVDS). This signaling technique lowers
the output voltage levels of 5-V differential
standard levels (such as TIA/EIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the
four current-mode drivers delivers a minimum
differential output voltage magnitude of 247 mV
into a 100-Ω load when enabled.
The intended application of these devices and
signaling technique is both point-to-point and
multidrop (one driver and multiple receivers) data
transmission over controlled impedance media of
approximately 100 Ω. The transmission media
may be printed-circuit board traces, backplanes,
or cables. The ultimate rate and distance of data
transfer is dependent upon the attenuation
characteristics of the media and the noise
coupling to the environment.
9
10 11 12 13
SN65LVDS3487D
(Marked as LVDS3487 or 65LVDS3487)
(TOP VIEW)
1A
1Y
V
CC
4A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
1Z
4Y
1,2EN
2Z
4Z
3,4EN
3Z
2Y
2A
10 3Y
3A
GND
9
SN65LVDS9638D (Marked as DK638 or LVDS38)
SN65LVDS9638DGN (Marked as L38)
SN65LVDS9638DGK (Marked as AXG)
(TOP VIEW)
V
1Y
1Z
2Y
2Z
1
2
3
4
8
7
6
5
CC
1A
The SN65LVDS31, SN65LVDS3487, and
SN65LVDS9638 are characterized for operation
from −40°C to 85°C. The SN55LVDS31 is
characterized for operation from −55°C to 125°C.
2A
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
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Copyright 1997 − 2004, Texas Instruments Incorporated
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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
(PW)
T
A
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
MSOP
(D)
SN65LVDS31D
SN65LVDS3487D
SN65LVDS9638D
—
SN65LVDS31PW
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
−40°C to
85°C
SN65LVDS9638DGN
SN65LVDS9638DGK
−55°C to
125°C
SNJ55LVDS31W
SN55LVDS31W
—
—
—
SNJ55LVDS31FK SNJ55LVDS31J
†
logic symbol
’LVDS31 logic diagram (positive logic)
SN55LVDS31, SN65LVDS31
4
G
≥ 1
4
12
G
G
EN
G
2
3
12
1
1Y
1Z
1A
2
3
6
5
1Y
1Z
1
7
2Y
2Z
1A
2A
3A
4A
6
5
10
11
2Y
2Z
3Y
3Z
4Y
4Z
7
9
3Y
3Z
2A
3A
4A
10
11
14
13
9
14
13
15
4Y
4Z
15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
logic symbol
SN65LVDS3487 logic diagram
(positive logic)
SN65LVDS3487
EN
4
2
3
1,2EN
1Y
1Z
1
1A
2
3
6
5
1
1Y
1Z
2Y
2Z
4
1A
1,2EN
6
5
2Y
2Z
7
7
2A
2A
10
11
12
9
3Y
3Z
3A
3,4EN
EN
10
11
14
13
12
9
3Y
3Z
4Y
4Z
3,4EN
3A
14
13
15
4Y
4Z
4A
15
4A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
†
logic symbol
SN65LVDS9638 logic diagram
(positive logic)
SN65LVDS9638
8
1Y
1Z
2
8
7
6
5
1A
7
2
1Y
1Z
2Y
2Z
1A
6
5
2Y
2Z
3
3
2A
2A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Function Tables
SN55LVDS31, SN65LVDS31
ENABLES
OUTPUTS
INPUT
A
G
H
H
X
X
L
Y
H
L
Z
L
G
X
X
L
H
L
H
L
H
H
L
L
L
H
Z
H
H
X
H
X
L
Z
L
Open
Open
H
X
L
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
SN65LVDS3487
OUTPUTS
INPUT
A
ENABLE
EN
Y
H
L
Z
L
H
L
H
H
L
H
Z
H
X
Z
L
Open
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
SN65LVDS9638
OUTPUTS
INPUT
A
Y
H
L
Z
L
H
L
H
H
Open
L
H = high level, L = low level
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A INPUT
EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
V
CC
50 Ω
50 Ω
Input
Input
7 V
10 kΩ
5 Ω
Y or Z
7 V
Output
300 kΩ
7 V
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
I
CC
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D (8)
D (16)
DGK
725 mW
5.8 mW/°C
7.6 mW/°C
3.4 mW/°C
17.1 mW/°C
11.0 mW/°C
11.0 mW/°C
6.2 mW/°C
8.0 mW/°C
464 mW
377 mW
—
—
950 mW
608 mW
494 mW
425 mW
272 mW
221 mW
—
§
DGN
2.14 W
1.37 W
1.11 W
—
FK
1375 mW
1375 mW
774 mW
880 mW
715 mW
275 mW
275 mW
—
J
PW (16)
W
880 mW
715 mW
496 mW
402 mW
1000 mW
640 mW
520 mW
200 mW
‡
§
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
The PowerPAD must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally Enhanced
Package (SLMA002)
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
3
2
3.3
3.6
V
V
V
High-level input voltage, V
IH
Low-level input voltage, V
IL
0.8
85
SN65 prefix
SN55 prefix
−40
−55
Operating free-air temperature, T
°C
A
125
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
SN55LVDS31 electrical characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
ꢀ
ꢂ
ꢃ
ꢄ
ꢄ
ꢅ
ꢆ
ꢅ
ꢇ
ꢈ
ꢃ
ꢉ
ꢊ
ꢋ
ꢌ
ꢈ
ꢍ
ꢌ
ꢈ
ꢎ
ꢋ
ꢊ
ꢈ
ꢉ
ꢏ
ꢅ
ꢐ
ꢉ
ꢏ
ꢇ
ꢃ
ꢈ
ꢌ
ꢑ
ꢅ
R
R
= 100 Ω,
See Figure 2
247
340
454
mV
ꢁ
ꢂ
L
L
Change in differential output voltage magnitude
between logic states
∆V
= 100 Ω,
See Figure 2
−50
50
mV
V
OD
V
Steady-state common-mode output voltage
See Figure 3
See Figure 3
See Figure 3
1.125
−50
1.2 1.375
50
OC(SS)
Change in steady-state common-mode output voltage
between logic states
∆V
mV
mV
OC(SS)
OC(PP)
V
I
Peak-to-peak common-mode output voltage
Supply current
50
9
150
20
V = 0.8 V or 2 V, Enabled,
I
No load
V = 0.8 or 2 V,
I
Enabled
R = 100 Ω,
L
mA
CC
25
35
V = 0 or V
CC
,
Disabled
0.25
4
1
20
10
−24
12
1
I
I
I
High-level input current
Low-level input current
V
V
V
V
V
V
= 2
µA
µA
IH
IH
= 0.8 V
0.1
−4
IL
IL
or V
= 0
O(Y)
O(Z)
I
Short-circuit output current
mA
OS
= 0
OD
I
I
High-impedance output current
Power-off output current
Input capacitance
= 0 or 2.4 V
µA
µA
pF
OZ
O
= 0,
V = 2.4 V
O
4
O(OFF)
CC
3
C
i
†
All typical values are at T = 25°C and with V
CC
= 3.3 V.
A
SN55LVDS31 switching characteristics over recommended operating conditions (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
4
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% to 80%)
Differential output signal fall time (80% to 20%)
0.5
1
1.4
1.7
0.5
0.5
0.3
0.3
5.4
2.5
8.1
7.3
PLH
PHL
r
4.5
1
ns
0.4
0.4
ns
R
= 100 Ω, C = 10 pF,
L
See Figure 2
L
1
ns
f
Pulse skew (|t
− t
|)
0.6
0.6
15
15
17
15
ns
sk(p)
sk(o)
PZH
PZL
PHZ
PLZ
PHL PLH
‡
Channel-to-channel output skew
ns
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
ns
ns
See Figure 4
ns
ns
†
‡
All typical values are at T = 25°C and with V
= 3.3 V.
is the maximum delay time difference between drivers on the same device.
A
CC
t
sk(o)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
ꢀ
Differential output voltage magnitude
R
R
= 100 Ω,
See Figure 2
See Figure 2
247
340
454
mV
mV
V
ꢁ
ꢂ
L
L
Change in differential output voltage magnitude
between logic states
∆V
= 100 Ω,
−50
50
OD
V
Steady-state common-mode output voltage
See Figure 3
See Figure 3
See Figure 3
1.125
−50
1.2 1.375
50
OC(SS)
Change in steady-state common-mode output voltage
between logic states
∆V
mV
mV
OC(SS)
OC(PP)
V
Peak-to-peak common-mode output voltage
50
9
150
20
V = 0.8 V or 2 V, Enabled,
I
No load
SN65LVDS31,
SN65LVDS3487
V = 0.8 or 2 V,
I
Enabled
R = 100 Ω,
L
25
35
I
Supply current
mA
CC
V = 0 or V
CC
,
Disabled
No load
0.25
4.7
9
1
8
I
SN65LVDS9638
V = 0.8 V or 2 V
I
R
= 100 Ω
13
20
10
−24
12
1
L
I
I
High-level input current
Low-level input current
V
V
V
V
V
V
= 2
4
µA
µA
IH
IH
= 0.8 V
0.1
−4
IL
IL
or V
O(Z)
= 0
O(Y)
I
Short-circuit output current
mA
OS
= 0
OD
I
I
High-impedance output current
Power-off output current
Input capacitance
= 0 or 2.4 V
µA
µA
pF
OZ
O
= 0,
V
O
= 2.4 V
1
O(OFF)
CC
3
C
i
†
All typical values are at T = 25°C and with V
CC
= 3.3 V.
A
6
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ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
SN65LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
2
t
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% to 80%)
Differential output signal fall time (80% to 20%)
0.5
1
1.4
1.7
0.5
0.5
0.3
0
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
PLH
PHL
r
2.5
0.6
0.6
0.6
0.3
800
15
0.4
0.4
R
= 100 Ω, C = 10 pF,
L
L
See Figure 2
f
Pulse skew (|t
− t
|)
sk(p)
sk(o)
sk(pp)
PZH
PZL
PHZ
PLZ
PHL PLH
‡
Channel-to-channel output skew
§
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
5.4
2.5
8.1
7.3
15
See Figure 4
15
15
†
‡
All typical values are at T = 25°C and with V
= 3.3 V.
is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same
A
CC
t
sk(o)
direction while driving identical specified loads.
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
§
t
sk(pp)
with the same supply voltages, same temperature, and have identical packages and test circuits.
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ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
I
OY
Y
Z
I
I
A
V
V
OD
I
OZ
V
OY
V
(V
OY
+ V )/2
OZ
OC
V
I
OZ
Figure 1. Voltage and Current Definitions
2 V
Input
1.4 V
0.8 V
t
t
PHL
PLH
Y
Z
Input
(see Note A)
100 Ω
1%
100%
80%
V
OD
V
OD
C
= 10 pF
L
0
(2 Places)
(see Note B)
20%
0%
t
t
r
f
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate
r
f
(PRR) = 50 Mpps, pulse width = 10 0.2 ns.
B.
C
L
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
49.9 Ω 1% (2 Places)
3 V
Y
A
Input
(see Note A)
A
0
V
OC(PP)
(see Note C)
Z
V
OC(SS)
V
OC
C
= 10 pF
L
V
OC
(2 Places)
(see Note B)
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate
r
f
(PRR) = 50 Mpps, pulse width = 10 0.2 ns.
B.
C
L
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
C. The measurement of V
is made on test equipment with a −3-dB bandwidth of at least 300 MHz.
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
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ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
49.9 Ω 1% (2 Places)
Y
Z
0.8 V or 2 V
Inputs
(see Note A)
1.2 V
G
C
= 10 pF
V
OY
V
OZ
L
G
(2 Places)
(see Note B)
1,2EN or 3,4EN
2 V
1.4 V
G, 1,2EN,
OR 3,4EN
0.8 V
2 V
1.4 V
0.8 V
G
t
t
t
PZH
PHZ
PLZ
V
OY
or
A at 2 V, G at V
or
and Input to G
100%, ≅1.4 V
50%
CC
V
OZ
G at GND and Input to G for ’LVDS31 Only
0%, 1.2 V
t
PZL
A at 0.8 V, G at V
or
G at GND and Input to G for ’LVDS31 Only
and Input to G
100%, 1.2 V
50%
0%, ≅1 V
CC
V
OZ
or
V
OY
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t < 1 ns, pulse repetition rate
r
f
(PRR) = 0.5 Mpps, pulse width = 500 10 ns.
includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
B.
C
L
Figure 4. Enable- and Disable-Time Circuit and Definitions
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
SN55LVDS31, SN65LVDS31
SUPPLY CURRENT
vs
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
FREQUENCY
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
35
Four Drivers Loaded Per
Figure 3 and Switching
Simultaneously
33
31
29
27
25
V
= 3.6 V
CC
V
CC
= 3.3 V
V
CC
= 3 V
V
= 3 V
CC
V
CC
= 3.3 V
23
21
V
= 3.6 V
CC
19
1.1
1
17
15
50
100
150
200
−40 −20
0
20
40
60
80
100
f − Frequency − MHz
T
A
− Free-Air Temperature − °C
Figure 5
Figure 6
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
V
CC
= 3 V
V
= 3.3 V
CC
V
= 3.6 V
CC
1.1
1
−40 −20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
Figure 7
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate − Mbps
NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 8. Typical Transmission Distance Versus Signaling Rate
3.3 V
1
16
1A
V
CC
0.1 µF
(see Note A)
0.001 µF
(see Note A)
2
3
15
14
1Y
1Z
4A
4Y
4Z
G
Z
Z
= 100 Ω
= 100 Ω
O
Z
O
= 100 Ω
4
5
13
12
V
CC
G
2Z
See Note B
O
6
7
11
10
9
2Y
3Z
3Y
Z
O
= 100 Ω
2A
8
GND
3A
NOTES: A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground
CC
plane. The capacitors should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to V
or GND, as appropriate.
CC
Figure 9. Typical Application Circuit Schematic
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
APPLICATION INFORMATION
1/4 ’LVDS31
Strb/Data_TX
Tp Bias on
Strb/Data_Enable
Twisted-Pair A
TP
’LVDS32
55 Ω
5 kΩ
Data/Strobe
1 Arb_RX
55 Ω
3.3 V
20 kΩ
TP
500 Ω
500 Ω
VG on
Twisted-Pair B
20 kΩ
3.3 V
20 kΩ
500 Ω
500 Ω
2 Arb_RX
20 kΩ
3.3 V
Twisted-Pair B Only
Port_Status
7 kΩ
7 kΩ
10 kΩ
3.3 kΩ
NOTES: A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown, but recommended.
C.
V
CC
is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
Figure 10. 100-Mbps IEEE 1394 Transceiver
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
APPLICATION INFORMATION
0.01 µF
≈3.6 V
1
16
1A
V
CC
5 V
0.1 µF
(see Note A)
1N645
(2 places)
2
3
15
14
1Y
1Z
4A
4Y
4Z
G
Z
Z
= 100 Ω
= 100 Ω
O
Z
O
= 100 Ω
4
5
13
12
V
CC
G
2Z
See Note B
O
6
7
11
10
2Y
3Z
3Y
Z
O
= 100 Ω
2A
9
8
GND
3A
NOTES: A. Place a 0.1-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground plane. The
CC
capacitor should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to V
CC
or GND, as appropriate.
Figure 11. Operation With 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
D
D
D
D
D
D
Low-Voltage Differential Signaling Design Notes (literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (literature number SLLA038)
Reducing EMI With LVDS (literature number SLLA030)
Slew Rate Control of LVDS Circuits (literature number SLLA034)
Using an LVDS Receiver With TIA/EIA-422 Data (literature number SLLA031)
Low Voltage Differential Signaling (LVDS) EVM (literature number SLLA033)
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
THERMAL PAD MECHANICAL DATA
PowerPADt PLASTIC SMALL-OUTLINE
DGN (S−PDSO−G8)
Top View
8
5
Exposed Pad
1,73 MAX
1
4
1,78 MAX
Not to Scale
PPTD041
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to
Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application
Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.
PowerPAD is a trademark of Texas Instruments
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
M
0,65
0,25
0,25
8
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°−6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
M
0,25
8
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°−6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073271/A 01/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
21
22
23
24
25
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
B SQ
A SQ
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
PINS **
14
16
18
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
0.785
0.910
0.975
(19,94) (19,94) (23,10) (24,77)
C
0.755
(19,18) (19,18)
0.755
0.930
(23,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.100 (2,54)
0°−15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040083/D 08/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢂꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀ ꢆ ꢇꢈ ꢀ ꢁꢉ ꢂ ꢃꢄ ꢅꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁꢉ ꢂ ꢃꢄꢅꢀ ꢍ ꢉ ꢆ ꢋ
ꢎ ꢏꢐ ꢎꢑꢀ ꢒꢓꢓ ꢅ ꢅ ꢏ ꢔꢔ ꢓꢕ ꢓꢁ ꢖꢏ ꢗ ꢃ ꢃꢏ ꢁ ꢓ ꢅꢕ ꢏ ꢄꢓ ꢕꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
M
0,10
0,65
14
0,19
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢇ ꢈ ꢀꢁ ꢉꢂ ꢃꢄꢅ ꢀꢆ ꢊ ꢋ ꢌ ꢈ ꢀꢁ ꢉꢂ ꢃꢄ ꢅꢀ ꢍꢉ ꢆꢋ
ꢎꢏ ꢐꢎ ꢑꢀꢒꢓ ꢓꢅ ꢅꢏ ꢔꢔ ꢓꢕ ꢓꢁꢖ ꢏꢗ ꢃ ꢃ ꢏꢁꢓ ꢅ ꢕꢏ ꢄ ꢓꢕ ꢀ
SLLS261K − JULY 1997 − REVISED MARCH 2004
MECHANICAL INFORMATION
W (R-GDFP-F16)
CERAMIC DUAL FLATPACK
Base and Seating Plane
0.285 (7,24)
0.245 (6,22)
0.006 (0,15)
0.004 (0,10)
0.085 (2,16)
0.045 (1,14)
0.045 (1,14)
0.026 (0,66)
0.305 (7,75)
0.275 (6,99)
0.355 (9,02)
0.235 (5,97)
0.355 (9,02)
0.235 (5,97)
0.019 (0,48)
1
16
0.015 (0,38)
0.050 (1,27)
0.440 (11,18)
0.371 (9,42)
0.025 (0,64)
0.015 (0,38)
8
9
1.025 (26,04)
0.745 (18,92)
4040180-3/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL-STD-1835 GDFP1-F16 and JEDEC MO-092AC
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9762101Q2A
5962-9762101QEA
5962-9762101QFA
5962-9762101VFA
SN55LVDS31W
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
16
16
16
16
16
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
W
W
D
CFP
CFP
SN65LVDS31D
SOIC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS31DR
SN65LVDS31DRG4
SN65LVDS31NSR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SO
D
D
16
16
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDS31PW
SN65LVDS31PWR
SN65LVDS3487D
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
D
16
16
16
90
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS3487DR
SN65LVDS9638D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS9638DGK
SN65LVDS9638DGKR
SN65LVDS9638DGN
ACTIVE
ACTIVE
ACTIVE
MSOP
MSOP
DGK
DGK
DGN
8
8
8
80
2500
80
TBD
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
MSOP-
Power
PAD
SN65LVDS9638DGNR
SN65LVDS9638DR
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
D
8
8
2500
TBD
CU NIPDAU Level-1-220C-UNLIM
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ55LVDS31FK
SNJ55LVDS31J
SNJ55LVDS31W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
16
16
1
1
1
TBD
TBD
TBD
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2005
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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dsp.ti.com
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www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
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power.ti.com
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Security
www.ti.com/opticalnetwork
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microcontroller.ti.com
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Video & Imaging
Wireless
www.ti.com/wireless
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