5962-9762101VEA [TI]
HIGH-SPEED DIFFERENTIAL LINE DRIVER; 高速差分线路驱动器
| 型号： | 5962-9762101VEA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE DRIVER |
| 文件： | 总13页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN55LVDS31-SP
www.ti.com
SLLSEB5 –MARCH 2012
HIGH-SPEED DIFFERENTIAL LINE DRIVER
Check for Samples: SN55LVDS31-SP
1
FEATURES
•
QML-V Qualified, SMD 5962-97621
•
Cold Sparing for Space and High Reliability
Applications Requiring Redundancy
•
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
J OR W PACKAGE
(TOP VIEW)
•
•
Low-Voltage Differential Signaling With Typical
Output Voltage of 350 mV and 100-Ω Load
Typical Output Voltage Rise and Fall Times of
500 ps (400 Mbps)
1A
1Y
VCC
4A
4Y
4Z
G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
•
•
•
Typical Propagation Delay Times of 1.7 ns
Operate From a Single 3.3-V Supply
1Z
G
Power Dissipation 25 mW Typical Per Driver at
200 MHz
2Z
2Y
3Z
•
Driver at High Impedance When Disabled or
With VCC = 0
2A
10 3Y
3A
GND
9
•
•
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
DESCRIPTION
The SN55LVDS31 is a differential line driver that implements the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard
levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a
3.3-V supply rail. This driver will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω
load when enabled.
The intended application of this device and signaling technique is both point-to-point and multidrop (one driver
and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of
data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN55LVDS31 is characterized for operation from –55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN55LVDS31-SP
SLLSEB5 –MARCH 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
CDIP - J
ORDERABLE PART NUMBER
TOP-SIDE MARKING
5962-9762101VEA
5962-9762101VFA
5962-9762101VEA
–55°C to 125°C
CFP - W
5962-9762101VFA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
xxx
Logic Symbol
SN55LVDS31 Logic Diagram (Positive Logic)
SN55LVDS31
4
G
≥ 1
12
4
G
G
2
3
EN
1
1Y
1Z
12
1A
G
6
5
2
3
7
2Y
2Z
1Y
1Z
1
2A
3A
4A
1A
10
11
6
5
9
3Y
3Z
2Y
2Z
3Y
3Z
4Y
4Z
7
2A
10
11
14
13
14
13
9
15
4Y
4Z
3A
15
4A
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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SLLSEB5 –MARCH 2012
FUNCTION TABLE
Table 1. SN55LVDS31(1)
ENABLES
OUTPUTS
INPUT
A
G
H
H
X
X
L
G
X
X
L
Y
H
L
Z
L
H
L
H
L
H
H
L
L
L
H
Z
H
H
X
H
X
L
Z
L
Open
Open
H
X
L
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off)
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH A INPUT
EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
V
CC
50 Ω
50 Ω
Input
Input
7 V
10 kΩ
5 Ω
Y or Z
Output
7 V
300 kΩ
7 V
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC
VI
Supply voltage range(2)
–0.5 V to 4 V
Input voltage range
–0.5 V to VCC + 0.5 V
See Dissipation Rating Table
260°C
Continuous total power dissipation
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature range
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
TA ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
TA = 85°C
TA = 125°C
PACKAGE
POWER RATING
POWER RATING
POWER RATING
POWER RATING
J
1375 mW
11 mW/°C
8 mW/°C
880 mW
640 mW
715 mW
520 mW
275 mW
200 mW
W
1000 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC
VIH
VIL
TA
Supply voltage
3
2
3.3
3.6
V
V
High-level input voltage
Low-level input voltage
Operating free-air temperature
0.8
V
–55
125
°C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VOD
Differential output voltage magnitude
RL = 100 Ω,
See Figure 2
See Figure 2
247
–50
340
454
50
mV
mV
ΔVOD
Change in differential output voltage magnitude RL = 100 Ω,
between logic states
VOC(SS)
ΔVOC(SS)
VOC(PP)
Steady-state common-mode output voltage
See Figure 3
See Figure 3
See Figure 3
1.125
–50
1.2 1.375
V
Change in steady-state common-mode output
voltage between logic states
50
mV
mV
Peak-to-peak common-mode output voltage
50
VI = 0.8 V or 2 V, Enabled, No load
9
25
20
35
ICC
Supply current
VI = 0.8 or 2 V,
RL = 100 Ω, Enabled
mA
VI = 0 or VCC
,
Disabled
0.25
4
1
IIH
IIL
High-level input current
Low-level input current
VIH = 2
20
μA
μA
VIL = 0.8 V
0.1
–4
10
VO(Y) or VO(Z) = 0
VOD = 0
–24
±12
±1
IOS
Short-circuit output current
mA
IOZ
High-impedance output current
Power-off output current
Input capacitance
VO = 0 or 2.4 V
VCC = 0,
μA
μA
pF
IO(OFF)
Ci
VO = 2.4 V
±4
3
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
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SLLSEB5 –MARCH 2012
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20% to 80%)
Differential output signal fall time (80% to 20%)
Pulse skew (|tPHL – tPLH|)
0.5
1
1.4
1.7
0.5
0.5
0.3
0.3
5.4
2.5
8.1
7.3
4
4.5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.4
0.4
RL = 100 Ω, CL = 10 pF,
See Figure 2
tf
1
tsk(p)
tsk(o)
tPZH
tPZL
tPHZ
tPLZ
0.6
0.6
15
15
17
15
Channel-to-channel output skew(2)
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
See Figure 4
(1) All typical values are at TA = 25°C and with VCC = 3.3 V.
(2) tsk(o) is the maximum delay time difference between drivers on the same device.
PARAMETER MEASUREMENT INFORMATION
I
OY
Y
Z
I
I
A
V
OD
V
OZ
I
OZ
V
OY
V
OC
(V + V )/2
V
I
OY
OZ
Figure 1. Voltage and Current Definitions
2 V
Input
1.4 V
0.8 V
t
t
PLH
PHL
Y
Z
Input
(see Note A)
100 Ω
± 1%
100%
80%
V
OD
V
OD
C
= 10 pF
L
0
(2 Places)
(see Note B)
20%
0%
t
f
t
r
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns.
B. C includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω ± 1% (2 Places)
3 V
0
Y
A
Input
(see Note A)
A
V
OC(PP)
(see Note C)
Z
V
OC(SS)
V
OC
C
L
= 10 pF
V
OC
(2 Places)
(see Note B)
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
pulse width = 10 ± 0.2 ns.
B. C includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
C. The measurement of V
is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω ± 1% (2 Places)
Y
0.8 V or 2 V
Inputs
Z
(see Note A)
1.2 V
G
C
= 10 pF
V
OY
V
OZ
L
G
(2 Places)
(see Note B)
1,2EN or 3,4EN
2 V
1.4 V
0.8 V
G, 1,2EN,
OR 3,4EN
2 V
1.4 V
0.8 V
G
t
t
t
PZH
PHZ
V
OY
or
A at 2 V, G at V and Input to G
or
G at GND and Input to G for ’LVDS31 Only
100%, 1.4 V
50%
CC
V
OZ
0%, 1.2 V
t
PZL
PLZ
A at 0.8 V, G at V and Input to G
or
G at GND and Input to G for ’LVDS31 Only
100%, 1.2 V
50%
0%, 1 V
CC
V
OZ
or
V
OY
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t or t < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 ± 10 ns.
B. C includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
L
Figure 4. Enable-/Disable-Time Circuit and Definitions
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREQUENCY
FREE-AIR TEMPERATURE
35
2.8
2.6
2.4
2.2
2
Four Drivers Loaded Per
Figure 3 and Switching
Simultaneously
33
31
29
27
25
V
= 3.6 V
CC
V
= 3.3 V
CC
V
CC
= 3.6 V
V
CC
= 3 V
V = 3 V
CC
V
CC
= 3.3 V
23
21
19
1.8
1.6
17
15
50
100
150
200
-55
-40 25
- Free-Air Temperature - °C
125
T
f − Frequency − MHz
A
Figure 5.
Figure 6.
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.5
3
V
= 3.3 V
V
= 3 V
CC
CC
2.5
2
V
= 3.6 V
CC
1.5
1
0.5
0
-55
-40 25
- Free-Air Temperature - °C
125
T
A
Figure 7.
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APPLICATION INFORMATION
The SN55LVDS31 is generally used as a building block for high-speed point-to-point data transmission where
ground differences are less than 1 V. The SN55LVDS31 can interoperate with RS-422, PECL, and IEEE-P1596.
Drivers/receivers approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate − Mbps
A. This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 8. Typical Transmission Distance Versus Signaling Rate
3.3 V
1
16
1A
V
CC
0.1 µF
0.001 µF
(see Note A)
(see Note A)
2
3
15
14
1Y
1Z
G
4A
4Y
4Z
G
Z
Z
= 100 Ω
= 100 Ω
O
Z
O
= 100 Ω
4
5
13
12
V
CC
2Z
See Note B
O
6
7
11
10
9
2Y
3Z
3Y
Z
O
= 100 Ω
2A
8
GND
3A
NOTES: A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V and the ground
CC
plane. The capacitors should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to V or GND, as appropriate.
CC
Figure 9. Typical Application Circuit Schematic
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1/4 ’LVDS31
Strb/Data_TX
Tp Bias on
Twisted-Pair A
Strb/Data_Enable
TP
TP
’LVDS32
55 Ω
5 kΩ
Data/Strobe
55 Ω
3.3 V
20 kΩ
500 Ω
500 Ω
VG on
Twisted-Pair B
1 Arb_RX
20 kΩ
3.3 V
20 kΩ
500 Ω
500 Ω
2 Arb_RX
20 kΩ
3.3 V
Twisted-Pair B Only
Port_Status
7 kΩ
7 kΩ
10 kΩ
3.3 kΩ
NOTES: A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown, but recommended.
C.
V
CC
is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
Figure 10. 100-Mbps IEEE 1394 Transceiver
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0.01 µF
≈3.6 V
1
16
1A
V
CC
5 V
0.1 µF
1N645
(see Note A)
(2 places)
2
3
15
14
1Y
1Z
4A
4Y
4Z
G
Z
Z
= 100 Ω
= 100 Ω
O
Z
O
= 100 Ω
4
5
13
12
V
CC
G
2Z
See Note B
O
6
7
11
10
9
2Y
3Z
3Y
Z
O
= 100 Ω
2A
8
GND
3A
A. Place a 0.1-μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 11. Operation With 5-V Supply
COLD SPARING
Systems using cold sparing have a redundant device electrically connected without power supplied. To support
this configuration, the spare must present a high-input impedance to the system so that it does not draw
appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.
When the device is powered off, VCC must be clamped to ground and the I/O voltages applied must be within the
specified recommended operating conditions.
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
•
•
•
•
•
Low-Voltage Differential Signaling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
5962-9762101VFA
ACTIVE
CFP
W
16
1
TBD
A42
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55LVDS31-SP :
Catalog: SN55LVDS31
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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