5962-9759501QRA [TI]
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 八路缓冲器/驱动器,具有三态输出型号: | 5962-9759501QRA |
厂家: | TEXAS INSTRUMENTS |
描述: | OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
文件: | 总21页 (文件大小:803K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
FEATURES
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.1 ns at 3.3 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
•
•
Typical VOHV (Output VOH Undershoot) > 2 V at
VCC = 3.3 V, TA = 25°C
– 1000-V Charged-Device Model (C101)
ABC
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC
)
SN54LVC541A . . . FK PACKAGE
SN54LVC541A . . . J OR W PACKAGE
SN74LVC541A . . . DB, DGV, DW, NS,
OR PW PACKAGE
SN74LVC541A . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
20
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
V
CC
3
9
2
1
20 19
18
Y1
Y2
Y3
Y4
A1
A2
A3
A4
A5
A6
A7
A8
OE2
A3
A4
A5
A6
A7
2
3
4
5
6
7
8
9
19
4
5
6
7
8
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18 Y1
17
16
15
A2
A3
A4
A5
17
16
15
14
13
12
Y2
Y3
Y4
Y5
Y6
Y7
14 Y5
10 11 12 13
A6
A7
A8
GND
10
11
DESCRIPTION/ORDERING INFORMATION
The SN54LVC541A octal buffer/driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC541A octal
buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVC541ARGYR
SN74LVC541ADW
TOP-SIDE MARKING
LC541A
QFN – RGY
SOIC – DW
Reel of 1000
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Reel of 2000
Tube of 20
Tube of 85
Tube of 55
LVC541A
SN74LVC541ADWR
SN74LVC541ANSR
SN74LVC541ADBR
SN74LVC541APW
SOP – NS
LVC541A
LC541A
–40°C to 85°C
SSOP – DB
TSSOP – PW
SN74LVC541APWR
SN74LVC541APWT
SN74LVC541ADGVR
SNJ54LVC541AJ
LC541A
TVSOP – DGV
CDIP – J
LC541A
SNJ54LVC541AJ
SNJ54LVC541AW
SNJ54LVC541AFK
–55°C to 125°C
CFP – W
SNJ54LVC541AW
LCCC – FK
SNJ54LVC541AFK
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The 'LVC541A devices are ideal for driving bus lines or buffering memory address registers.
These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board
layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output enable (OE1 or OE2)
input is high, all eight outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE1
L
OE2
L
A
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE1
19
OE2
2
18
A1
Y1
To Seven Other Channels
2
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DB package(4)
DGV package(4)
DW package(4)
NS package(4)
PW package(4)
RGY package(5)
92
58
θJA
Package thermal impedance
Storage temperature range
°C/W
°C
60
83
37
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
3
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
Recommended Operating Conditions(1)
SN54LVC541A
SN74LVC541A
UNIT
MIN
2
MAX
MIN
MAX
Operating
3.6
1.65
3.6
VCC
Supply voltage
V
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
2
0.35 × VCC
VIL
Low-level input voltage
0.7
0.8
5.5
VCC
5.5
–4
V
0.8
5.5
VI
Input voltage
0
0
0
0
0
0
V
V
High or low state
3-state
VCC
5.5
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
mA
–12
–24
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
Low-level output current
mA
°C
12
24
12
24
TA
Operating free-air temperature
–55
125
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC541A
MIN TYP(1) MAX
SN74LVC541A
MIN TYP(1) MAX
PARAMETER
TEST CONDITIONS
VCC
UNIT
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
VCC – 0.2
IOH = –100 µA
VCC – 0.2
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
2.2
2.4
2.2
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
2.3 V
0.2
0.2
IOL = 4 mA
0.45
0.7
0.4
0.55
±5
VOL
V
IOL = 8 mA
IOL = 12 mA
2.7 V
0.4
0.55
±5
IOL = 24 mA
3 V
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(2)
One input at VCC – 0.6 V,
3.6 V
µA
µA
µA
Ioff
IOZ
0
±10
±10
10
3.6 V
±15
10
ICC
IO = 0
3.6 V
µA
µA
10
10
∆ICC
2.7 V to 3.6 V
500
500
Other inputs at VCC or GND
Ci
VI = VCC or GND
3.3 V
3.3 V
4
4
pF
pF
Co
VO = VCC or GND
5.5
5.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVC541A
VCC = 3.3 V
± 0.3 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 2.7 V
UNIT
MIN
MAX
tpd
ten
tdis
A
Y
Y
Y
5.6
7.5
7.7
1
1
1
5.1
7
ns
ns
ns
OE
OE
7
5
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN74LVC541A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
UNIT
MIN
1
MAX
MIN
1
MAX
MIN
1
MAX
MIN MAX
tpd
ten
A
Y
Y
Y
15.7
17.5
16.5
7.8
10.5
9
5.6
7.5
7.7
1.5
1.5
1.5
5.1
7
ns
ns
ns
ns
OE
OE
1
1
1
tdis
1
1
1
7
tsk(o)
1
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
65
2
TYP
58
2
TYP
33
2
Outputs enabled
Outputs disabled
Power dissipation capacitance
per buffer/driver
Cpd
f = 10 MHz
pF
6
SN54LVC541A, SN74LVC541A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS298M–JANUARY 1993–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9759501Q2A
5962-9759501QRA
5962-9759501QSA
SN74LVC541ADBLE
SN74LVC541ADBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
W
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC541ADBRG4
SN74LVC541ADGVR
SN74LVC541ADGVRE4
SN74LVC541ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
TVSOP
TVSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
DB
DGV
DGV
DW
DW
DW
DW
DW
DW
NS
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC541ADWE4
SN74LVC541ADWG4
SN74LVC541ADWR
SN74LVC541ADWRE4
SN74LVC541ADWRG4
SN74LVC541ANSR
SN74LVC541ANSRE4
SN74LVC541ANSRG4
SN74LVC541APW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
PW
PW
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC541APWE4
SN74LVC541APWG4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC541APWLE
SN74LVC541APWR
OBSOLETE TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC541APWRE4
SN74LVC541APWRG4
SN74LVC541APWT
PW
PW
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC541APWTE4
SN74LVC541ARGYR
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LVC541ARGYRG4
ACTIVE
QFN
RGY
20
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SNJ54LVC541AFK
SNJ54LVC541AJ
SNJ54LVC541AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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