5962-9759802QYA [CYPRESS]
Flash PLD, 19ns, 128-Cell, CMOS, CQCC84, CERAMIC, LCC-84;型号: | 5962-9759802QYA |
厂家: | CYPRESS |
描述: | Flash PLD, 19ns, 128-Cell, CMOS, CQCC84, CERAMIC, LCC-84 时钟 输入元件 可编程逻辑 |
文件: | 总17页 (文件大小:640K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
75i
CY7C375i
UltraLogic™ 128-Macrocell Flash CPLD
Features
Functional Description
• 128 macrocells in eight logic blocks
• 128 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG Interface
The CY7C375i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C375i is de-
signed to bring the ease of use and high performance of the
22V10 to high-density PLDs.
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
Like all of the UltraLogic™ FLASH370i devices, the CY7C375i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally, be-
cause of the superior routability of the FLASH370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
— fMAX = 125 MHz
— tPD = 10 ns
— tS = 5.5 ns
— tCO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 160-pin TQFP, CQFP, and PGA packages
Logic Block Diagram
CLOCK
INPUTS
INPUTS
1
4
INPUT/CLOCK
MACROCELLS
INPUT
MACROCELL
4
4
16 I/Os
LOGIC
BLOCK
A
LOGIC
BLOCK
H
16 I/Os
I/O –I/O
36
16
36
16
0
15
I/O –I/O
112
127
PIM
LOGIC
BLOCK
B
LOGIC
BLOCK
G
16 I/Os
16 I/Os
16 I/Os
16 I/Os
36
16
36
16
I/O –I/O
I/O –I/O
96 111
16
31
47
LOGIC
BLOCK
C
LOGIC
BLOCK
F
36
16
36
16
I/O –I/O
I/O –I/O
80
32
95
79
16 I/Os
LOGIC
BLOCK
D
LOGIC
BLOCK
E
16 I/Os
36
16
36
16
I/O –I/O
I/O –I/O
64
48
63
64
64
7C375i–1
Selection Guide
7C375i–125 7C375i–100 7C375i–83 7C375iL–83 7C375i–66 7C375iL–66
Maximum Propagation Delay[1], tPD (ns)
Minimum Set-Up, tS (ns)
Maximum Clock to Output[1], tCO (ns)
10
5.5
6.5
125
12
6
15
8
15
8
20
10
20
10
10
75
7
8
8
10
Typical Supply Current, ICC (mA)
125
125
75
125
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03029 Rev. **
Revised September 4, 2001
CY7C375i
Pin Configurations
Top View
TQFP
GND
1
I/O
16
2
V
120
119
118
117
CCIO
I/O
111
I/O
17
I/O
18
I/O
19
I/O
110
3
I/O
109
I/O /SDI
108
I/O
107
4
5
116
115
I/O /SCLK
20
6
7
8
9
I/O
21
I/O
106
114
113
112
I/O
22
I/O
23
I/O
105
I/O
104
GND
GND
111
110
10
11
I/O
24
I/O
103
I/O
25
I/O
102
109
108
107
106
12
13
14
I/O
26
I/O
27
I/O
101
I/O
100
I/O
28
I/O
99
15
16
I/O
29
105
104
I/O
I/O
I/O
98
97
96
I/O
I/O
17
18
19
20
30
103
102
101
100
31
CLK /I
CLK /I
3
0
0
4
3
V
CCIO
GND
GND
V
CCIO
21
22
CLK /I
CLK /I
2
I/O
95
1
1
99
98
I/O
I/O
23
24
25
26
32
I/O
94
97
96
95
94
33
I/O
I/O
I/O
93
34
35
I/O
92
I/O
36
I/O
37
I/O
38
I/O
39
I/O
91
I/O
90
27
28
93
92
I/O
89
I/O
88
29
30
31
32
91
90
89
GND
GND
I/O
40
I/O
41
I/O
42
I/O
43
I/O
87
I/O
86
88
87
33
34
I/O
85
86
85
84
I/O
84
35
36
37
I/O
I/O
I/O
83
I/O
82
44
45
I/O
I/O
V
46
47
83
82
81
38
39
I/O
I/O
GND
81
80
CCIO
40
7C375i–2
Document #: 38-03029 Rev. **
Page 2 of 17
CY7C375i
Pin Configurations (continued)
Top View
CQFP
GND
1
I/O
16
2
V
120
119
118
117
CC
I/O
111
I/O
17
I/O
18
I/O
19
I/O
110
3
I/O
109
I/O /SDI
108
I/O
107
4
5
116
115
I/O /SCLK
20
6
7
8
9
I/O
21
I/O
106
114
113
112
I/O
22
I/O
23
I/O
105
I/O
104
GND
GND
111
110
10
11
I/O
24
I/O
103
I/O
25
I/O
102
109
108
107
106
12
13
14
I/O
26
I/O
27
I/O
101
I/O
100
I/O
28
I/O
99
15
16
I/O
29
105
104
I/O
98
I/O
97
I/O
96
I/O
I/O
17
18
19
20
30
103
102
101
100
31
CLK /I
CLK /I
3
0
0
4
3
V
CC
GND
V
CC
GND
21
22
CLK /I
CLK /I
2
I/O
95
1
I/O
I/O
1
99
98
23
24
25
32
33
I/O
94
97
96
95
94
I/O
I/O
I/O
93
34
35
I/O
92
26
27
28
I/O
36
I/O
37
I/O
38
I/O
39
I/O
I/O
91
93
92
90
I/O
89
I/O
88
29
30
31
32
91
90
89
GND
GND
I/O
40
I/O
41
I/O
42
I/O
43
I/O
87
I/O
86
88
87
33
34
I/O
85
86
85
84
I/O
84
35
36
I/O
I/O
I/O
83
I/O
82
44
45
37
38
39
I/O
I/O
V
46
47
83
82
81
I/O
I/O
81
80
GND
CC
40
7C375i–3
Document #: 38-03029 Rev. **
Page 3 of 17
CY7C375i
Pin Configurations (continued)
PGA
Bottom View
R
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
109
106
105
102
100
112
115
113
111
107
103
118
116
114
CC
121
119
117
123
122
120
126
125
124
CC
127
0
3
5
6
8
7
9
10
13
11
14
I/O
I/O
GND
I/O
I/O
I/O
I/O
110
1
4
15
17
16
19
108
N
ISR
EN
GND
GND
2
12
/SDI
I/O
/SCLK
M
20
I/O
V
V
GND
V
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
104
101
CC
18
21
24
22
25
27
30
31
32
34
36
38
41
42
45
L
I/O
I/O
I/O
I/O
23
26
29
K
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
98
96
95
94
91
89
86
83
80
78
99
97
CLK
/I
3
J
H
G
V
V
CLK
28
CC
CC
4
CLK
/I
CLK
0
2
GND
GND
GND
GND
/I
3
0
CLK1
/I1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
I/O
I/O
93
90
87
84
81
79
75
92
88
85
82
CC
CC
33
35
37
40
44
46
48
F
E
GND
I/O
I/O
I/O
I/O
39
43
47
49
51
D
C
V
GND
V
CC
GND
I/O
V
CC
CC
76
I/O
I/O
GND
I/O
I/O
I
I/O
I/O
56
I/O
I/O
GND
72
70
69
66
65
64
2
60
61
62
53
55
57
50
/SDO
I/O
/
52
B
A
I/O
I/O
I/O
GND I/O
I/O
I/O
I/O
I/O
77
74
73
71
68
67
58
59
SMODE
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
I/O
9
I/O
I/O
13
I/O
14
63
71
1
8
10
11
12
15
7C375i–4
Logic Block
Functional Description (continued)
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C375i includes eight logic blocks.
Each logic block is constructed of a product term array, a prod-
uct term allocator, and 16 macrocells.
The 128 macrocells in the CY7C375i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Product Term Array
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings flex-
ibility, routability, speed, and a uniform delay to the intercon-
nect.
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are avail-
able in both positive and negative polarity, making the overall
array size 72 x 86. This large array in each logic block allows
for very complex functions to be implemented in single passes
through the device.
Like all members of the FLASH370i family, the CY7C375i is rich
in I/O resources. Every macrocell in the device features an
associated I/O pin, resulting in 128 I/O pins on the CY7C375i.
In addition, there is one dedicated input and four input/clock
pins.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
Finally, the CY7C375i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect de-
lays, or expander delays. Regardless of the number of re-
sources used or the type of application, the timing parameters
on the CY7C375i remain the same.
Document #: 38-03029 Rev. **
Page 4 of 17
CY7C375i
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i PLDs. Note that product term allocation is han-
dled by software and is invisible to the user.
compatible with 5.0V systems. When VCCIO pins are connect-
ed to a 3.3V source, the input voltage levels are compatible
with both 5.0V and 3.3V systems, while the output voltage lev-
els are compatible with 3.3V systems. There will be an addi-
tional timing delay on all output buffers when operating in 3.3V
I/O mode. The added flexibility of 3.3V I/O capability is avail-
able in commercial and industrial temperature ranges.
I/O Macrocell
Each of the macrocells on the CY7C375i has a separate I/O
pin associated with it. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term alloca-
tor. The macrocell includes a register that can be optionally
bypassed, polarity control over the input sum-term, and four
global clocks to trigger the register. The macrocell also fea-
tures a separate feedback path to the PIM so that the register
can be buried if the I/O pin is used as an input.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus re-
ducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C375i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Design Tools
Programming
Development software for the CY7C375i is available from Cy-
press’s Warp™, Warp Professional™, and Warp Enterprise™
software packages. Please refer to the data sheets on these
products for more details. Cypress also actively supports al-
most all third-party design tools. Please refer to third-party tool
support for further information.
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An In-
troduction to In System Reprogramming with FLASH370i.”
Maximum Ratings
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term
distribution.
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
DC Input Voltage ............................................–0.5V to +7.0V
DC Program Voltage .................................................... 12.5V
Output Current into Outputs ........................................ 16 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Ambient
Temperature
VCC
VCCINT
Range
VCCIO
Commercial
0°C to +70°C
−40°C to +85°C
–55°C to +125°C
5V ± 0.25V
5V ± 0.5V
5V ± 0.5V
5V ± 0.25V
OR
3.3V ± 0.3V
Industrial
5V ± 0.5V
OR
3.3V ± 0.3V
Military[2]
Note:
2. TA is the “instant on” case temperature.
Document #: 38-03029 Rev. **
Page 5 of 17
CY7C375i
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
Description
Test Conditions
VCC = Min. IOH = –3.2 mA (Com’l/Ind)[5]
IOH = –2.0 mA (Mil)
Min. Typ. Max. Unit
VOH
Output HIGH Voltage
2.4
V
V
VOHZ
VOL
Output HIGH Voltage
with Output Disabled[9]
VCC = Max. IOH = 0 µA (Com’l/Ind)[5, 6]
IOH = –50 µA (Com’l/Ind)[5, 6]
VCC = Min. IOL = 16 mA (Com’l/Ind)[5]
IOL = 12 mA (Mil)
4.0
3.6
0.5
V
V
Output LOW Voltage
V
V
VIH
VIL
IIX
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Guaranteed Input Logical HIGH voltage for all inputs[7] 2.0
Guaranteed Input Logical LOW voltage for all inputs[7] –0.5
7.0
0.8
V
V
VI = Internal GND, VI = VCC
–10
+10
µA
µA
µA
mA
IOZ
Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled –50
+50
VCC = Max., VO = 3.3V, Output Disabled[6]
0
–70 –125
–160
IOS
ICC
Output Short
VCC = Max., VOUT = 0.5V
–30
Circuit Current[8, 9]
Power Supply
Current[10]
VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC
Com’l/Ind.
125
75
200
125
250
mA
mA
mA
µA
Com’l “L” –66
Military
125
IBHL
Input Bus Hold LOW
Sustaining Current
VCC = Min., VIL = 0.8V
VCC = Min., VIH = 2.0V
VCC = Max.
+75
IBHH
Input Bus Hold HIGH
Sustaining Current
–75
µA
µA
µA
IBHLO
IBHHO
Input Bus Hold LOW
Overdrive Current
+500
Input Bus Hold HIGH
Overdrive Current
VCC = Max.
–500
Capacitance[9]
Parameter
Description
Test Conditions
Min.
Max.
Unit
[11]
CI/O
Input/Output Capacitance
Clock Signal Capacitance
VIN = 5.0V at f=1 MHz
VIN = 5.0V at f = 1 MHz
8
pF
pF
CCLK
5
12
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT
.
5. IOH = –2 mA, IOL = 2 mA for SDO.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
11. CI/O for dedicated inputs, and for I/O pins with JTAG functionality is 12 pF,and for the ISREN pin is 15 pF Max.
Document #: 38-03029 Rev. **
Page 6 of 17
CY7C375i
Inductance[9]
160-Lead
TQFP
160-Pin
CQFP
160-Pin
CPGA
Parameter
Description
Test Conditions
Unit
L
Maximum Pin Inductance
VIN = 5.0V at 5 = 1 MHz
9
6
10
nH
Endurance Characteristics[9]
Parameter
Description
Maximum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Max.
Unit
N
100
Cycles
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
238Ω (COM’L)
319Ω (MIL)
ALL INPUT PULSES
90% 90%
10% 10%
5V
5V
3.0V
GND
OUTPUT
OUTPUT
170Ω (COM'L)
236Ω (MIL)
35 pF
5 pF
170Ω (COM’L)
236Ω (MIL)
<2ns
<2ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
7C375i–4
(b)
7C375i–5
Equivalent to:
THÉVENIN EQUIVALENT
99Ω (COM’L)
136Ω (MIL)
2.08V(COM'L)
2.13V(MIL)
OUTPUT
Parameter[12]
VX
Output Waveforms--Measurement Level
tER(–)
1.5V
VOH
0.5V
0.5V
VX
7C375i-6
tER(+)
tEA(+)
tEA(–)
2.6V
1.5V
Vthe
VX
VOL
7c375i-7
VOH
0.5V
0.5V
VX
7c375i-8
VX
VOL
7c375i-9
(d) Test Waveforms
Note:
12. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Document #: 38-03029 Rev. **
Page 7 of 17
CY7C375i
Switching Characteristics Over the Operating Range[13]
7C375i–83
7C375i–66
7C375i–125 7C375i–100 7C374iL–83 7C375iL–66
Parameter
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
10
13
12
15
15
18
20
22
ns
ns
tPDL
Input to Output Through Transparent Input
or Output Latch[1]
tPDLL
Input to Output Through Transparent Input
and Output Latches[1]
15
16
19
24
ns
tEA
tER
Input to Output Enable[1]
14
14
16
16
19
19
24
24
ns
ns
Input to Output Disable
Input Registered/Latched Mode Parameters
tWL
tWH
tIS
Clock or Latch Enable Input LOW Time[9]
Clock or Latch Enable Input HIGH Time[9]
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
tIH
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
14
16
16
18
19
21
24
26
tICOL
Input Register Clock or Latch Enable to
Output Through Transparent Output
Latch[1]
ns
Ouptut Registered/Latched Mode Parameters
tCO
tS
Clock or Latch Enable to Output[1]
6.5
14
7
8
10
24
ns
ns
Set-Up Time from Input to Clock or Latch
Enable
5.5
0
6
0
8
0
10
0
tH
Register or Latch Data Hold Time
ns
ns
tCO2
Output Clock or Latch Enable to Output
Delay (Through Memory Array)[1]
16
19
tSCS
Output Clock or Latch Enable to Output
Clock or Latch Enable (Through Memory
Array)
8
10
0
10
12
0
12
15
0
15
20
0
ns
ns
ns
tSL
Set-Up Time from Input Through Transpar-
ent Latch to Output Register Clock or Latch
Enable
tHL
Hold Time for Input Through Transparent
Latch from Output Register Clock or Latch
Enable
fMAX1
fMAX2
Maximum Frequency with Internal Feed-
125
100
143
83
66
MHz
MHz
[9]
back (Least of 1/tSCS, 1/(tS + tH), or 1/tCO
)
Maximum Frequency Data Path in Output 158.3
Registered/LatchedMode(Lesserof1/(tWL
125
100
+ tWH), 1/(tS + tH), or 1/tCO
Maximum Frequency with External Feed-
back (Lesser of 1/(tCO + tS) and 1/(tWL
tWH
)
fMAX3
83.3
0
76.9
0
62.5
0
50
0
MHz
ns
+
,
tOH–tIH
37x
Output Data Stable from Output Clock
Minus Input Register Hold Time for
7C37x[9, 14]
Notes:
13. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
14. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C375i. This specification is met
for the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03029 Rev. **
Page 8 of 17
CY7C375i
Switching Characteristics Over the Operating Range[13] (continued)
7C375i–83
7C375i–66
7C375i–125 7C375i–100 7C374iL–83 7C375iL–66
Parameter
Pipelined Mode Parameters
tICS Input Register Clock to Output Register
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
8
10
12
15
ns
Clock
fMAX4
Maximum Frequency in Pipelined Mode
(Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH),
125
100
83.3
66.6
MHz
1/(tIS + tIH), or 1/tSCS
)
Reset/Preset Parameters
tRW
tRR
tRO
tPW
tPR
tPO
Asynchronous Reset Width[9]
10
12
12
14
15
17
20
22
ns
ns
ns
ns
ns
ns
Asynchronous Reset Recovery Time[9]
Asynchronous Reset to Output[1]
Asynchronous Preset Width[9]
Asynchronous Preset Recovery Time[9]
Asynchronous Preset to Output[1]
16
16
18
18
21
21
26
26
10
12
12
14
15
17
20
22
Tap Controller Parameter
fTAP
Tap Controller Frequency
500
500
500
500
kHz
ns
3.3V I/O Mode Parameters
t3.3IO
3.3V I/O mode timing adder
1
1
1
1
Switching Waveforms
Combinatorial Output
INPUT
t
PD
COMBINATORIAL
OUTPUT
7C375i–10
Registered Output
INPUT
t
S
t
H
CLOCK
t
CO
REGISTERED
OUTPUT
t
t
WL
WH
CLOCK
7C375i–11
Document #: 38-03029 Rev. **
Page 9 of 17
CY7C375i
Switching Waveforms (continued)
Latched Output
INPUT
t
S
t
H
LATCHENABLE
t
t
CO
PDL
LATCHED
OUTPUT
7C375i–12
Registered Input
REGISTERED
INPUT
t
IS
t
IH
INPUT REGISTER
CLOCK
t
ICO
COMBINATORIAL
OUTPUT
t
t
WL
WH
CLOCK
7C375i–13
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK
t
t
ICS
SCS
OUTPUT
REGISTER CLOCK
7C375i–14
Document #: 38-03029 Rev. **
Page 10 of 17
CY7C375i
Switching Waveforms (continued)
Latched Input
LATCHED INPUT
t
IS
t
IH
LATCHENABLE
t
t
ICO
PDL
COMBINATORIAL
OUTPUT
t
t
WL
WH
LATCHENABLE
7C375i–15
Latched Input and Output
LATCHED INPUT
t
PDLL
LATCHED
OUTPUT
t
t
SL
ICOL
t
HL
INPUT LATCH
ENABLE
t
ICS
OUTPUT LATCH
ENABLE
t
t
WL
WH
LATCH ENABLE
7C375i–16
Document #: 38-03029 Rev. **
Page 11 of 17
CY7C375i
Switching Waveforms (continued)
Asynchronous Reset
t
RW
INPUT
t
RO
REGISTERED
OUTPUT
t
RR
CLOCK
7C375i–17
Asynchronous Preset
t
PW
INPUT
t
PO
REGISTERED
OUTPUT
t
PR
CLOCK
7C375i–18
OutputEnable/Disable
INPUT
t
t
EA
ER
OUTPUTS
7C375i–20
Document #: 38-03029 Rev. **
Page 12 of 17
CY7C375i
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
CY7C375i–125AC
CY7C375i–100AC
CY7C375i–100AI
CY7C375i–83AC
CY7C375i–83AI
Package Type
125
A160
A160
A160
A160
A160
G160
U162
A160
A160
A160
G160
U162
A160
160-Lead Thin Quad Flatpack
160-Lead Thin Quad Flatpack
160-Lead Thin Quad Flatpack
160-Lead Thin Quad Flatpack
160-Lead Thin Quad Flatpack
160-Pin Grid Array
160-Pin Ceramic Quad Flatpack[15]
160-Lead Thin Quad Flatpack
160-Lead Thin Quad Flatpack
160-Lead Thin Quad Flatpack
160-Pin Grid Array
Commercial
Commercial
Industrial
100
83
66
Commercial
Industrial
CY7C375i–83GMB
CY7C375i–83UMB
CY7C375iL–83AC
CY7C375i–66AC
CY7C375i–66AI
Military
Commercial
Commercial
Industrial
CY7C375i–66GMB
CY7C375i–66UMB
CY7C375iL–66AC
Military
160-Pin Ceramic Quad Flatpack[15]
160-Lead Thin Quad Flatpack
Commercial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
9, 10, 11
DC Characteristics
tPD
tCO
tICO
tS
Parameter
VOH
Subgroups
1, 2, 3
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
VOL
VIH
VIL
IIX
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tH
tIS
tIH
IOZ
ICC
tICS
Note:
15. Standard product ships trim and formed in a carrier. This product is also available in a molded carrier ring. Contact local Cypress office for package information.
ISR, UltraLogic, FLASH370 and FLASH370i are trademarks of Cypress Semiconductor Corporation.
Warp, Warp Professional, and Warp Enterprise are registered trademarks of Cypress Semiconductor Corporation.
Document #: 38-03029 Rev. **
Page 13 of 17
CY7C375i
Package Diagrams
160-Pin Thin Plastic Quad Flat Pack (TQFP) A160
51-85049-A
Document #: 38-03029 Rev. **
Page 14 of 17
CY7C375i
Package Diagrams (continued)
160-Pin PGA G160
Document #: 38-03029 Rev. **
Page 15 of 17
CY7C375i
Package Diagrams (continued)
160-Lead Ceramic Quad Flatpack (Cavity Up) U162
Document #: 38-03029 Rev. **
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C375i
Document Title: CY7C375i UltraLogic™ 128-Macrocell Flash CPLD
Document Number: 38-03029
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106374
09/15/01
SZV
Change from Spec number: 38-00494 to 38-03029
Document #: 38-03029 Rev. **
Page 17 of 17
相关型号:
5962-9760101HXX
DC-DC Regulated Power Supply Module, 3 Output, HERMETIC SEALED, HYBRID PACKAGE-17
WEDC
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