5962-9326101MEX [TI]
1.5A POWER FACTOR CONTROLLER, 200kHz SWITCHING FREQ-MAX, CDIP16;型号: | 5962-9326101MEX |
厂家: | TEXAS INSTRUMENTS |
描述: | 1.5A POWER FACTOR CONTROLLER, 200kHz SWITCHING FREQ-MAX, CDIP16 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 |
文件: | 总12页 (文件大小:312K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UC1854
UC2854
UC3854
High Power Factor Preregulator
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
Control Boost PWM to 0.99 Power Factor
The UC1854 provides active power factor correction for power sys-
tems that otherwise would draw non-sinusoidal current from sinusoi-
dal power lines. This device implements all the control functions
necessary to build a power supply capable of optimally using available
power-line current while minimizing line-current distortion. To do this,
the UC1854 contains a voltage amplifier, an analog multiplier/divider,
a current amplifier, and a fixed-frequency PWM. In addition, the
UC1854 contains a power MOSFET compatible gate driver, 7.5V ref-
erence, line anticipator, load-enable comparator, low-supply detector,
and over-current comparator.
Limit Line Current Distortion To <5%
World-Wide Operation Without Switches
Feed-Forward Line Regulation
Average Current-Mode Control
Low Noise Sensitivity
Low Start-Up Supply Current
Fixed-Frequency PWM Drive
Low-Offset Analog Multiplier/Divider
1A Totem-Pole Gate Driver
The UC1854 uses average current-mode control to accomplish fixed-
frequency current control with stability and low distortion. Unlike peak
current-mode, average current control accurately maintains sinusoidal
line current without slope compensation and with minimal response to
noise transients.
The UC1854’s high reference voltage and high oscillator amplitude
minimize noise sensitivity while fast PWM elements permit chopping
frequencies above 200kHz. The UC1854 can be used in single and
three phase systems with line voltages that vary from 75 to 275 volts
and line frequencies across the 50Hz to 400Hz range. To reduce the
burden on the circuitry that supplies power to this device, the UC1854
features low starting supply current.
Precision Voltage Reference
These devices are available packaged in 16-pin plastic and ceramic
dual in-line packages, and a variety of surface-mount packages.
BLOCK DIAGRAM
UDG-92055
6/98
UC1854
UC2854
UC3854
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V
GT Drv Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
GT Drv Current, 50% Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 1.5A
Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage, ISENSE, Mult Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . . . . . . 10mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65oC to +150oC
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . +300oC
Note 1: All voltages with respect to Gnd (Pin 1).
Note 2: All currents are positive into the specified termi-
nal.
Note 3: ENA input is internally clamped to approximately
14V.
Note 4: Consult Unitrode Integrated Circuits databook for
information regarding thermal specifications and limita-
CONNECTION DIAGRAMS
PACKAGE PIN FUNCTION
DIL–16 & SOIC-16
(Top View)
J, N & DW Packages
PLCC-20 & LCC-20
(Top View)
Q & L Packages
FUNCTION
N/C
PIN
1
Gnd
2
PKLMT
CA Out
ISENSE
N/C
Mult Out
IAC
VA Out
VRMS
N/C
VREF
ENA
VSENSE
RSET
N/C
SS
CT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
GT Drv
Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,
VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out,
VA Out, REF, GT Drv, –55oC<TA<125oC for the UC1854, –40oC<TA<85oC for the UC2854, and
0oC<TA<70oC for the UC3854, and TA=TJ.
ELECTRICAL
CHARACTERISTICS
PARAMETER
OVERALL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current, Off
ENA=0V
1.5
10
2.0
16
mA
mA
V
Supply Current, On
VCC Turn-On Threshold
VCC Turn-Off Threshold
ENA Threshold, Rising
ENA Threshold Hysteresis
ENA Input Current
14.5
9
16
17.5
11
10
V
2.4
2.55
0.25
–0.2
–.01
2.7
0.3
5.0
1.0
V
0.2
V
ENA=0V
VRMS=5V
–5.0
–1.0
µA
µA
VRMS Input Current
VOLTAGE AMPLIFIER
Voltage Amp Offset Voltage
VSENSE Bias Current
Voltage Amp Gain
VA Out=5V
–8
–500
70
8
mV
nA
dB
V
–25
100
500
Voltage Amp Output Swing
0.5 to 5.8
–20
Voltage Amp Short Circuit Current VA Out=0V
SS Current SS=2.5V
–36
–20
–5
–6
mA
µA
–14
2
UC1854
UC2854
UC3854
Unless otherwise stated, VCC=18V, RSET=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,
VRMS=1.5V, IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=7.5V, no load on SS, CA Out,
VA Out, REF, GT Drv, –55oC<TA<125oC for the UC1854, –40oC<TA<85oC for the UC2854, and
0oC<TA<70oC for the UC3854, and TA=TJ.
ELECTRICAL
CHARACTERISTICS
PARAMETER
CURRENT AMPLIFIER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Amp Offset Voltage
ISENSE Bias Current
–4
–500
4
mV
nA
V
–120
500
Input Range, ISENSE, Mult Out
Current Amp Gain
–0.3 to 2.5
80
110
0.5 to 16
–20
dB
V
Current Amp Output Swing
Current Amp Short Circuit Current CA Out=0V
–36
400
–5
mA
kHz
Current Amp Gain-BW Product
REFERENCE
TA=25oC (Note 6)
IREF=0mA, TA=25oC
800
Reference Output Voltage
7.4
7.35
–15
–10
–50
7.5
7.5
5
7.6
7.65
15
V
IREF=0mA, Over Temp.
–10mA<IREF<0mA
15V<VCC<35V
V
VREF Load Regulation
VREF Line Regulation
VREF Short Circuit Current
MULTIPLIER
mV
mV
mA
2
10
REF=0V
–28
–12
Mult Out Current IAC Limited
Mult Out Current Zero
Mult Out Current RSET Limited
Mult Out Current
IAC=100µA, RSET=10k, VRMS=1.25V
IAC=0µA, RSET=15k
–220
–2.0
–280
–50
–200
–0.2
–255
–42
–180
2.0
µA
µA
µA
µA
µA
µA
µA
µA
V
IAC=450µA, RSET=15k, VRMS=1V, VA Out = 6V
IAC=50µA, VRMS=2V, VA=4V
IAC=100µA, VRMS=2V, VA=2V
IAC=200µA, VRMS=2V, VA=4V
IAC=300µA, VRMS=1V, VA=2V
IAC=100µA, VRMS=1V, VA=2V
(Note 5)
–220
–33
–38
–27
–12
–165
–250
–95
–150
–225
–80
–105
–150
–60
Multiplier Gain Constant
OSCILLATOR
–1.0
Oscillator Frequency
RSET=15k
RSET=8.2k
46
86
55
102
5.4
1.1
62
118
5.9
1.3
kHz
kHz
V
CT Ramp Peak-to-Valley Amplitude
CT Ramp Valley Voltage
GATE DRIVER
4.9
0.8
V
Maximum GT Drv Output Voltage 0mA load on GT Drv, 18V<VCC<35V
13
12
14.5
12.8
0.9
1.0
0.1
1.0
35
18
V
V
GT Drv Output Voltage High
GT Drv Output Voltage Low, Off
GT Drv Output Voltage Low
–200mA load on GT Drv, VCC=15V
VCC=0V, 50mA load on GT Drv
200mA load on GT Drv
10mA load on GT Drv
1.5
2.2
0.4
V
V
V
Peak GT Drv Current
GT Drv Rise/Fall Time
GT Drv Maximum Duty Cycle
CURRENT LIMIT
10nF from GT Drv to Gnd
1nF from GT Drv to Gnd
VCA Out=7V
A
ns
%
95
PKLMT Offset Voltage
PKLMT Input Current
PKLMT to GT Drv Delay
–10
10
mV
µA
ns
PKLMT=–0.1V
–200
–100
175
PKLMT falling from 50mV to –50mV
k × IAC × (VA Out−1)
IMult Out =
Note 5: Multiplier Gain Constant (k) is defined by:
2
VRMS
Note 6: Guaranteed by design. Not 100% tested in production.
3
UC1854
UC2854
UC3854
PIN DESCRIPTIONS
(Pin Numbers Refer to DIL Packages)
Gnd (Pin 1) (ground): All voltages are measured with re- VRMS (Pin 8) (RMS line voltage): The output of a boost
spect to Gnd. VCC and REF should be bypassed directly PWM is proportional to the input voltage, so when the line
voltage into a low-bandwidth boost PWM voltage regula-
tor changes, the output will change immediately and
slowly recover to the regulated level. For these devices,
the VRMS input compensates for line voltage changes if it
is connected to a voltage proportional to the RMS input
line voltage. For best control, the VRMS voltage should
stay between 1.5V and 3.5V.
to Gnd with an 0.1µF or larger ceramic capacitor. The tim-
ing capacitor discharge current also returns to this pin, so
the lead from the oscillator timing capacitor to Gnd should
also be as short and as direct as possible.
PKLMT (Pin 2) (peak limit): The threshold for PKLMT is
0.0V. Connect this input to the negative voltage on the
current sense resistor as shown in Figure 1. Use a resis-
tor to REF to offset the negative current sense signal up
to Gnd.
REF (Pin 9) (voltage reference output): REF is the output
of an accurate 7.5V voltage reference. This output is ca-
pable of delivering 10mA to peripheral circuitry and is in-
ternally short circuit current limited. REF is disabled and
will remain at 0V when VCC is low or when ENA is low.
CA Out (Pin 3) (current amplifier output): This is the out-
put of a wide-bandwidth op amp that senses line current
and commands the pulse width modulator (PWM) to force
the correct current. This output can swing close to Gnd,
allowing the PWM to force zero duty cycle when neces-
Bypass REF to Gnd with an 0.1µF or larger ceramic ca-
pacitor for best stability.
sary. The current amplifier will remain active even if the IC ENA (Pin 10) (enable): ENA is a logic input that will en-
is disabled. The current amplifier output stage is an NPN able the PWM output, voltage reference, and oscillator.
emitter follower pull-up and an 8k resistor to ground.
ENA also will release the soft start clamp, allowing SS to
rise. When unused, connect ENA to a +5V supply or pull
ENA high with a 22k resistor. The ENA pin is not intended
to be used as a high speed shutdown to the PWM output.
ISENSE (Pin 4) (current sense minus): This is the inverting
input to the current amplifier. This input and the non-in-
verting input Mult Out remain functional down to and be-
low Gnd. Care should be taken to avoid taking these
V
SENSE
(Pin 11) (voltage amplifier inverting input): This is
inputs below –0.5V, because they are protected with di- normally connected to a feedback network and to the
odes to Gnd. boost converter output through a divider network.
Mult Out (Pin 5) (multiplier output and current sense RSET (Pin 12) (oscillator charging current and multiplier
plus): The output of the analog multiplier and the non-in- limit set): A resistor from RSET to ground will program os-
verting input of the current amplifier are connected to- cillator charging current and maximum multiplier output.
gether at Mult Out. The cautions about taking ISENSE Multiplier output current will not exceed 3.75V divided by
below –0.5V also apply to Mult Out. As the multiplier out- the resistor from RSET to ground.
put is a current, this is a high impedance input similar to
SS (Pin 13) (soft start): SS will remain at Gnd as long as
ISENSE, so the current amplifier can be configured as a
the IC is disabled or VCC is too low. SS will pull up to over
differential amplifier to reject Gnd noise. Figure 1 shows
8V by an internal 14µA current source when both VCC be-
an example of using the current amplifier differentially.
comes valid and the IC is enabled. SS will act as the ref-
IAC (Pin 6) (input AC current): This input to the analog
multiplier is a current. The multiplier is tailored for very
low distortion from this current input (IAC) to Mult Out, so
this is the only multiplier input that should be used for
sensing instantaneous line voltage. The nominal voltage
on IAC is 6V, so in addition to a resistor from IAC to recti-
fied 60Hz, connect a resistor from IAC to REF. If the resis-
tor to REF is one fourth of the value of the resistor to the
rectifier, then the 6V offset will be cancelled, and the line
current will have minimal cross-over distortion.
erence input to the voltage amplifier if SS is below REF.
With a large capacitor from SS to Gnd, the reference to
the voltage regulating amplifier will rise slowly, and in-
crease the PWM duty cycle slowly. In the event of a dis-
able command or a supply dropout, SS will quickly
discharge to ground and disable the PWM.
CT (Pin 14) (oscillator timing capacitor): A capacitor from
CT to Gnd will set the PWM oscillator frequency accord-
ing to this relationship:
1.25
F =
VA Out (Pin 7) (voltage amplifier output): This is the out-
put of the op amp that regulates output voltage. Like the
current amplifier, the voltage amplifier will stay active
even if the IC is disabled with either ENA or VCC. This
means that large feedback capacitors across the amplifier
will stay charged through momentary disable cycles. Volt-
age amplifier output levels below 1V will inhibit multiplier
output. The voltage amplifier output is internally limited to
approximately 5.8V to prevent overshoot. The voltage
amplifier output stage is an NPN emitter follower pull-up
and an 8k resistor to ground.
RSET × CT
VCC (Pin 15) (positive supply voltage): Connect VCC to a
stable source of at least 20mA above 17V for normal op-
eration. Also bypass VCC directly to Gnd to absorb supply
current spikes required to charge external MOSFET gate
capacitances. To prevent inadequate GT Drv signals,
these devices will be inhibited unless VCC exceeds the
upper under-voltage lockout threshold and remains
above the lower threshold.
4
UC1854
UC2854
UC3854
PIN DESCRIPTIONS (cont.)
GT Drv (Pin 16) (gate drive): The output of the PWM is a pedance and the GT Drv output driver that might cause
totem pole MOSFET gate driver on GT Drv. This output is the GT Drv output to overshoot excessively. Some over-
internally clamped to 15V so that the IC can be operated shoot of the GT Drv output is always expected when driv-
with VCC as high as 35V. Use a series gate resistor of at ing a capacitive load.
least 5 ohms to prevent interaction between the gate im-
TYPICAL CHARACTERISTICS at TA = TJ = 25°C
Current Amplifier Gain and Phase vs Frequency
Voltage Amplifier Gain and Phase vs Frequency
120
120
Phase
Margin
Phase
Margin
100
100
80
60
40
20
0
80
60
40
20
0
degrees
degrees
Open-Loop
Gain
Open-Loop
Gain
dB
dB
-20
-20
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
Frequency
kHz
Frequency
kHz
Gate Drive Rise and Fall Time
Gate Drive Maximum Duty Cycle
700
600
500
100%
95%
90%
Rise Time
Fall Time
400
ns
Duty
85%
Cycle
300
200
100
0
80%
75%
70%
1
10
100
0
0.01
0.02
0.03
0.04
0.05
R
SET, k Ω
Load Capacitance,
µF
Multiplier Output vs Voltage on Mult
Oscillator Frequency vs RSET and CT
1000
600
500
Mult Out=3V
Mult Out=2V
Mult Out=1
Mult Out=0V
400
100pF
Frequency
Multiplier
Output
µA
kHz
100
200pF
500pF
300
200
VRMS=2V, VA Out=5V
1nF
2nF
100
0
5nF
3nF
10nF
10
10
1
100
0
100 200 300 400 500 600 700
AC, µA
800
I
RSET, k Ω
5
UC1854
UC2854
UC3854
o
TYPICAL CHARACTERISTICS at TA = TJ = 25 C (cont.)
Multiplier Output vs Multiplier Inputs with Mult Out=0V
250
600
500
400
V
RMS=1.5V
VRMS=3V
VA Out=5V
200
150
VA Out=3.5V
VA Out=3V
300
Mult Out
VA Out=2.5V
VA Out=1.25V
Mult Out
µA
100
µA
200
VA Out=2V
50
0
100
0
VA Out=1.25V
0
100
200
300
400
500
0
100
200
300
AC, µA
400
500
I
AC, µA
I
140
160
140
120
100
V
RMS=5V
V
RMS=4V
VA Out=5V
120
100
VA Out=5V
VA Out=4V
VA Out=3V
Mult Out
80
Mult Out,
VA Out=3V
80
µA
µA
60
60
40
VA Out=2V
40
VA Out=1.5V
VA Out=1.25V
20
0
20
0
0
0
100
200
IAC,
300
400
500
100
200
300
µA
400
500
µ
A
IAC,
APPLICATIONS INFORMATION
A 250W PREREGULATOR
The circuit of Figure 1 shows a typical application of the
UC3854 as a preregulator with high power factor and effi-
ciency. The assembly consists of two distinct parts, the
control circuit centering on the UC3854 and the power
section.
The power section is a "boost" converter, with the induc-
tor operating in the continuous mode. In this mode, the
duty cycle is dependent on the ratio between input and
output voltages; also, the input current has low switching
frequency ripple, which means that the line noise is low.
Furthermore, the output voltage must be higher than the
peak value of the highest expected AC line voltage, and
all components must be rated accordingly.
cycle of this output is simultaneously controlled by four
separate inputs to the chip:
INPUT
PIN #
FUNCTION
VSENSE........................11 .......... Output DC Voltage
IAC.................................6 .......... LineVoltage Waveform
ISENSE/Mult Out .........4/5 .......... Line Current
VRMS.............................8 .......... RMS Line Voltage
Additional controls of an auxiliary nature are provided.
They are intended to protect the switching power MOS-
FETS from certain transient conditions, as follows:
INPUT
PIN #
FUNCTION
ENA ............................10 .......... Start-Up Delay
SS...............................13 .......... Soft Start
PKLIM...........................2 .......... Maximum Current Limit
In the control section, the UC3854 provides PWM pulses
(GT Drv, Pin 16) to the power MOSFET gate. The duty
6
UC1854
UC2854
UC3854
APPLICATIONS INFORMATION (cont.)
PROTECTION INPUTS
ISENSE/Mult Out (Line current): The voltage drop across
the 0.25 ohm current-sense resistor is applied to pins 4
and 5 as shown. The current-sense amplifier also oper-
ates with high low-frequency gain, but unlike the voltage
amplifier, it is set up to give the current-control loop a very
wide bandwidth. This enables the line current to follow the
line voltage as closely as possible. In the present exam-
ple, this amplifier has a zero at about 500Hz, and a gain
of about 18dB thereafter.
ENA (Enable): The ENA input must reach 2.5 volts be-
fore the REF and GT Drv outputs are enabled. This pro-
vides a means to shut down the gate in case of trouble, or
to add a time delay at power up. A hysteresis gap of
200mV is provided at this terminal to prevent erratic op-
eration. Undervoltage protection is provided directly at pin
15, where the on/off thresholds are 16V and 10V. If the
ENA input is unused, it should be pulled up to VCC
through a current limiting resistor of 100k.
VRMS (RMS line voltage): An important feature of the
UC3854 preregulator is that it can operate with a three-to-
one range of input line voltages, covering everything from
low line in the US (85VAC) to high line in Europe
(255VAC). This is done using line feedforward, which
keeps the input power constant with varying input voltage
(assuming constant load power). To do this, the multiplier
divides the line current by the square of the RMS value of
the line voltage. The voltage applied to pin 8, proportional
to the average of the rectified line voltage (and propor-
tional to the RMS value), is squared in the UC3854, and
then used as a divisor by the multiplier block. The multi-
plier output, at pin 5, is a current that increases with the
current at pin 6 and the voltage at pins 7, and decreases
with the square of the voltage at pin 8.
SS (Soft start): The voltage at pin 13 (SS) can reduce
the reference voltage used by the error amplifier to regu-
late the output DC voltage. With pin 13 open, the refer-
ence voltage is typically 7.5V. An internal current source
delivers approximately -14µA from pin 13. Thus a capaci-
tor connected between that pin and ground will charge
linearly from zero to 7.5V in 0.54C seconds, with C ex-
pressed in microfarads.
PKLIM (Peak current limit): Use pin 2 to establish the
highest value of current to be controlled by the power
MOSFET. With the resistor divider values shown in Figure
1, the 0.0V threshold at pin 2 is reached when the voltage
drop across the 0.25 ohm current sense resistor is
7.5V*2k/10k=1.5V, corresponding to 6A. A bypass capaci-
tor from pin 2 to ground is recommended to filter out very
high frequency noise.
PWM FREQUENCY: The PWM oscillator frequency in
Figure 1 is 100kHz. This value is determined by CT at pin
14 and RSET at pin 12. RSET should be chosen first be-
cause it affects the maximum value of IMULT according to
the equation:
CONTROL INPUTS
VSENSE (Output DC voltage sense): The threshold voltage
for the VSENSE input is 7.5V and the input bias current is
typically 50nA. The values shown in Figure 1 are for an
output voltage of 400V DC. In this circuit, the voltage am-
plifier operates with a constant low frequency gain for
minimum output excursions. The 47nF feedback capacitor
places a 15Hz pole in the voltage loop that prevents
120Hz ripple from propagating to the input current.
−3.75V
RSET
IMULT
=
MAX
This effectively sets a maximum PWM-controlled current.
With RSET=15k,
−3.75V
15k
IMULT
=
= −250µA
MAX
IAC (Line waveform): In order to force the line current
waveshape to follow the line voltage, a sample of the
power line voltage in waveform is introduced at pin 6. This
signal is multiplied by the output of the voltage amplifier in
the internal multiplier to generate a reference signal for
the current control loop.
Also note that the multiplier output current will never ex-
ceed twice IAC.
With the 4k resistor from Mult Out to the 0.25 ohm current
sense resistor, the maximum current in the current sense
resistor will be
This input is not a voltage, but a current (hence IAC). It is
set up by the 220k and 910k resistive divider (see Figure
1). The voltage at pin 6 is internally held at 6V, and the
two resistors are chosen so that the current flowing into
pin 6 varies from zero (at each zero crossing) to about
400µA at the peak of the waveshape. The following for-
mulas were used to calculate these resistors:
−IMULT
×4k
MAX
IMAX
=
= −4A
0.25Ω
Having thus selected RSET, the current sense resistor,
and the resistor from Mult Out to the current sense resis-
tor, calculate CT for the desired PWM oscillator frequency
from the equation
Vpk 260VAC × √2
1.25
CT =
RAC
=
=
= 910k
IACpk
400µA
F × RSET
RAC
4
RREF
=
= 220k
(where Vpk is the peak line voltage)
7
UC1854
UC2854
UC3854
FIGURE 1 - Typical Application
This diagram depicts a complete 250 Watt Preregulator. At full load, this preregulator will exhibit a power factor of 0.99
at any power line voltage between 80 and 260 VRMS. This same circuit can be used at higher power levels with minor
modifications to the power stage. See Design Note 39B and Application Note U-134 for further details.
UDG-92056-1
NOTE: Boost inductor can be fabricated with ARNOLD MPP toroidal core part number A-438381-2, using a 55 turn primary and a
13 turn secondary.
UNITRODE CORPORATION
•
7 CONTINENTAL BLVD. MERRIMACK, NH 03054
These products contain patented circuitry and are sold under license from Pioneer Magnetics, Inc.
ꢀ
TEL. (603) 424-2410 FAX (603) 424-3460
8
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9326101M2A
5962-9326101MEA
OBSOLETE
ACTIVE
TO/SOT
CDIP
L
J
20
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
1
5962-9326101ME
A
UC1854J/883B
UC1854J
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1854J
UC1854J883B
5962-9326101ME
A
UC1854J/883B
UC1854L
UC1854L883B
UC2854BJ
OBSOLETE
OBSOLETE
ACTIVE
TO/SOT
TO/SOT
CDIP
L
L
J
20
20
16
TBD
TBD
TBD
Call TI
Call TI
A42
Call TI
Call TI
-55 to 125
-55 to 125
-40 to 85
1
N / A for Pkg Type
UC2854BJ
UC2854DW
UC2854DWG4
UC2854DWTR
UC2854DWTRG4
UC2854N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
N
16
16
16
16
16
16
16
16
16
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
UC2854DW
40
2000
2000
25
Green (RoHS
& no Sb/Br)
UC2854DW
UC2854DW
UC2854DW
UC2854N
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2854NG4
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC2854N
UC3854DW
DW
DW
DW
DW
DW
40
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
UC3854DW
UC3854DW
UC3854DW
UC3854DW-F
UC3854DW
UC3854DWG4
UC3854DWTR
UC3854DWTR-FG4
UC3854DWTRG4
40
Green (RoHS
& no Sb/Br)
0 to 70
2000
2000
2000
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UC3854N
UC3854NG4
UC3854Q
ACTIVE
PDIP
PDIP
N
16
16
20
20
20
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU SN
N / A for Pkg Type
UC3854N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
25
46
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
UC3854N
UC3854Q
UC3854Q
UC3854Q
UC3854Q
PLCC
PLCC
PLCC
PLCC
FN
FN
FN
FN
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
UC3854QG3
UC3854QTR
UC3854QTRG3
46
Green (RoHS
& no Sb/Br)
CU SN
0 to 70
1000
1000
Green (RoHS
& no Sb/Br)
CU SN
0 to 70
Green (RoHS
& no Sb/Br)
CU SN
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1854, UC2854, UC2854BM, UC3854 :
Catalog: UC3854, UC2854B
•
Enhanced Product: UC2854B-EP
•
Military: UC2854M, UC1854
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
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