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5962-9326102MEA [TI]

ADVANCED HIGH-POWER FACTOR PREREGULATOR; 先进的高功率因数前置稳压器
5962-9326102MEA
型号： 5962-9326102MEA
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

ADVANCED HIGH-POWER FACTOR PREREGULATOR
先进的高功率因数前置稳压器

稳压器 开关式稳压器或控制器 电源电路 开关式控制器
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UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
ADVANCED HIGH-POWER FACTOR PREREGULATOR  
1
FEATURES  
DESCRIPTION  
•
Controls Boost PWM to Near-Unity Power  
Factor  
The UC3854A/B products are pin compatible  
enhanced versions of the UC3854. Like the UC3854,  
these products provide all of the functions necessary  
for active power factor corrected preregulators. The  
controller achieves near unity power factor by  
shaping the ac input line current waveform to  
correspond to the ac input line voltage. To do this the  
UC3854A/B uses average current mode control.  
Average current mode control maintains stable, low  
distortion sinusoidal line current without the need for  
slope compensation, unlike peak current mode  
control.  
•
•
•
•
Limits Line Current Distortion To <3%  
World-Wide Operation Without Switches  
Accurate Power Limiting  
Fixed-Frequency Average Current-Mode  
Control  
•
•
•
High Bandwidth (5 MHz), Low-Offset Current  
Amplifier  
Integrated Current- and Voltage-Amplifier  
Output Clamps  
Multiplier Improvements: Linearity, 500 mV VAC  
Offset (Eliminates External Resistor), 0 V to  
5 V Multout Common-Mode Range  
A 1%, 7.5-V reference, fixed frequency oscillator,  
PWM, voltage amplifierwith soft-start, line voltage  
feedforward (VRMS squarer), input supply voltage  
clamp, and over current comparator round out the lilst  
of feataures.  
•
•
VREF GOOD Comparator  
Faster and Improved Accuracy ENABLE  
Comparator  
Available in the 16-pin N (PDIP), DW (SOIC Wide),  
and J (CDIP) and 20-pin Q (PLCC) package. See  
Ordering Information table for availability by  
temperature range.  
•
•
UVLO Options (16 V/10 V or 10.5 V/10 V)  
300-µA Start-Up Supply Current  
BLOCK DIAGRAM  
VAO  
7
MOUT  
5
CAO PKLMT  
REF  
9
3
2
V
CC  
7.5 V REF  
(A) 16 V / 10 V  
(B) 10.5 V / 10 V  
RUN  
10  
ENA  
7.1 V  
IC  
POWER  
2.65 V / 2.15 V  
3 V  
15 VCC  
A
11  
6
VSENSE  
IAC  
R
R
S
B
C
16 GTDRV  
Q
2
X
8
VRMS  
SS  
RUN  
14 µA  
20 V  
13  
A   B  
+
I
OSC  
1
GND  
MOUT  
C
4
14  
CT  
12  
ISENSE  
RSET  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2008, Texas Instruments Incorporated  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
DESCRIPTION (CONTINUED)  
The UC3854A/B products improve upon the UC3854 by offering a wide bandwidth, low offset current amplifier, a  
faster responding and improved accuracy enable comparator, a VREF GOOD comparator, UVLO threshold  
options (16 V/10 V for offline, 10.5 V/10 V for startup from an auxiliary 12-V regulator), lower startup supply  
current, and an enhanced multiply/divide circuit. New features like the amplifier output clamps, improved amplifier  
current sinking capability, and low offset VAC pin reduce the external component count while improving  
performance. Improved common mode input range of the multiplier output/current amplifier input allow the  
designer greater flexibility in choosing amethod for current sensing. Unlike its predecessor, RSET controls only  
oscillator charging current and has no effect on clamping the maximum multiplier output current. This current is  
now clamped to a maximum of 2 × IAC at all times which simplifies the design process and provides foldback  
power limiting during brownout and extreme low line conditions.  
ORDERING INFORMATION  
UVLO  
TURN-ON  
(V)  
UVLO  
TURN-OFF  
(V)  
PART NUMBERS  
PDIP-16 SOIC-16  
TA  
CDIP-16  
(V)  
PLCC-20  
(Q)  
(N)  
(DW)  
16  
10.5  
16  
10  
10  
10  
10  
10  
10  
–
–
–
–
–55°C to 125°C  
–40°C to 85°C  
0°C to 70°C  
UC1854BJ  
UC2854AJ  
UC2854BJ  
–
–
–
–
UC2854AN  
UC2854BN  
UC2854AN  
UC2854BN  
UC2854ADW  
UC2854BDW  
UC2854ADW  
UC2854BDW  
UC2854AQ  
10.5  
16  
UC2854BQ  
–
–
10.5  
–
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)(1)  
UCX854A, UCX854B  
UNIT  
VCC  
Supply voltage  
GTDRV current  
22  
V
Continuous  
0.5  
IGTDRV  
A
V
50% duty cycle  
1.5  
VSENSE, VRMS, ISENSE MOUT  
PKLMT  
11  
Input voltage  
5
10  
Input current  
RSET, IAC, PKLMT, ENA  
mA  
W
Power dissipation  
Junction temperature  
Storage temperature  
1
TJ  
–55 to 150  
–65 to 150  
300  
Tstg  
Tsol  
°C  
Lead temperataure, 1,6 mm (1/16 inch) from case for 10 seconds  
(1) Stresses beyond those listed under absolutemaximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periodsmayaffect device reliability. All voltages  
arewith respect to GND. Currents are positive into and negative out of, the specified terminal. ENA input is internally clamped to  
approximately 10 V.  
2
Submit Documentation Feedback  
Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
10  
MAX UNIT  
VCC  
Supply voltage  
20  
125  
85  
V
UC1854X  
UC2854X  
UC3854X  
–55  
–40  
0
TJ  
Operating junction temperature  
°C  
70  
THERMAL RESISTANCE  
PACKAGED DEVICES  
PDIP-16  
(N)  
RESISTANCES  
CDIP-16  
SOP-16  
(DW)  
PLCC-20  
(Q)  
(J)  
θJC (°C/W)  
θJA (°C/W)  
28(1)  
45  
90(2)  
27  
50–130(2)  
34  
43–75(2)  
80–120  
(1) θJC data values stated are derived from MIL-STD-1835B which states gthe baseline values shown are worst case (mean +2s) for a 60 ×  
60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14,400 square mils. For device die sizes greater than  
14,400 square mils use the following values, dual-in-line, 11°C/W; flat pack and pin grid array, 10°C/W.are at the end of each trace.  
(2) θJA (junction-to-ambient) applies to devices mounted to five square inch FR4 PC board with one ounce copper where noted. When  
resitance range is given, lower values are for five square inch aluminum PC board. Test PWB is 0.062 inches thick and typically uses  
0,635 mm trace widths for power packages and 1,3 mm trace widths for non-power packages with a 100 × 100 mil probe land are at the  
end of each trace.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
ELECTRICAL CHARACTERISTICS  
VCC = 18 V, RT = 8.2 kΩ, CT = 1.5 nF, VPKLMT = 1 V, VVRMS = 1.5 V, IIAC = 100 µA, IISENSE = 0 V, VCAO = 3.5 V, VVAO = 5 V,  
VVSENSE = 3 V, –40°C < TA < 85°C for the UC2854A and UC2854B, and 0°C < TA < 70°C for the UC3854A and UC3854B,  
and TA = TJ (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OVERALL  
CAO = 0 V,  
VCC = VUVLO–0.3 V  
VAO = 0 V,  
Supply current, off  
Supply current, on  
250  
400  
µA  
12  
16.0  
10.5  
10  
18  
17.5  
11.2  
12  
mA  
UCx854A  
15.0  
8.0  
9
VCC turn-on threshold voltage  
VCC turn-off threshold voltage  
UCx854B  
UCx854A  
UCx854B  
7.8  
5
10.3  
6
11.0  
7
V
UCx854A  
VCC hysteresis  
VCC clamp  
UCx854B  
0.10  
18  
0.22  
20  
0.50  
22  
IVCC = IVCC(on) + 5 mA  
VOLTAGE AMPLIFIER  
Input voltage  
2.9  
–500  
70  
3.0  
—25  
100  
6
3.1  
V
VSENSE bias current  
Open loop gain  
500  
nA  
dB  
2 V ≤ VOUT ≤ 5 V  
ILOAD = –500 µA  
ILOAD = 500 µA  
VOUT = 0 V  
VOH  
VOL  
ISC  
High-level output voltage  
Low-level output voltage  
Output short-circuit current  
Gain bandwidth product(1)  
V
0.3  
1.5  
1
0.5  
3.5  
mA  
fIN = 100 kHz,  
10 mVp-p  
MHz  
CURRENT AMPLIFIER  
Input offset voltage  
Input bias current  
VCM = 0 V,  
TA = 25°C  
–4  
–5.5  
–500  
80  
0
0
mV  
VCM = 0 V,  
Overtemperature  
ISENSE  
VCM = 0 V  
500  
nA  
dB  
Open loop gain  
2 V ≤ VOUT = 6 V  
ILOAD = –500 µA  
ILOAD = 500 µA  
VOUT = 0 V  
110  
8
VOH  
VOL  
ISC  
High-level output voltage  
Low-level output voltage  
Output short-circuit current  
V
0.3  
1.5  
0.5  
3.5  
5.0  
mA  
V
CMRR Common mode rejection range  
Gain bandwidth product(1)  
REFERENCE  
–0.3  
3
fIN = 100 kHz,  
10 mVp-p  
5
MHz  
IREF = 0 mA,  
TA = 25°C  
7.4  
7.35  
0
7.5  
7.50  
8
7.6  
7.65  
20  
Output voltage  
V
IREF = 0 mA  
Load regulation  
Line regulation  
1 mA ≤ IREF ≤ 10 mA  
12 V ≤ VCC ≤ 18 V  
VREF = 0 V  
mV  
mA  
0
14  
25  
ISC  
Short circuit current  
25  
35  
60  
(1) Ensured by design. Not production tested.  
4
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Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
ELECTRICAL CHARACTERISTICS (Continued)  
VCC = 18 V, RT = 8.2 kΩ, CT = 1.5 nF, VPKLMT = 1 V, VVRMS = 1.5 V, IIAC = 100 µA, IISENSE = 0 V, VCAO = 3.5 V, VVAO = 5 V,  
VVSENSE = 3 V, –40°C < TA < 85°C for the UC2854A and UC2854B, and 0°C < TA < 70°C for the UC3854A and UC3854B,  
and TA = TJ (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
OSCILLATOR  
Initial accuracy  
TA = 25°C  
85  
100  
1%  
115  
kHz  
Voltage stability  
Total variation  
12 V ≤ VCC ≤ 18 V  
Line, temperature  
80  
4.9  
0.8  
120  
5.9  
1.3  
kHz  
V
Ramp amplitude (peak-to-peak)  
Ramp valley voltage  
V
ENABLE/SOFT-START/CURRENT LIMIT  
Enable threshold voltage  
Enaable hysteresis  
2.35  
2.55  
500  
–2  
2.80  
600  
–5  
V
VFAULT = 2.5 V  
VENA = 0 V  
mV  
µA  
ns  
Enable input bias current  
Propagation delay to disable time(1)  
Soft-start charge current  
Peak limit offset voltage  
Peak limit offset current  
Peak limit propagation delay time(1)  
MULTIPLIER  
Enable overdrive = 100 mV  
VSS = 2.5 V  
300  
14  
10  
–15  
24  
15  
µA  
mV  
µA  
ns  
VPKLMIT = –0.1 V  
–200  
–100  
150  
IAC = 100 µA,  
RSET = 10 kΩ  
VRMS = 1 V,  
Output current, IA limited  
–220  
–200  
–170  
µA  
Output current, zero  
IAC = 0 µA,  
RSET = 10 kΩ  
Va = 6 V  
–2.0  
–0.2  
–200  
–22  
2.0  
µA  
µA  
Output current, power limited  
VRMS = 1.5 V  
VRMS = 1.5 V  
VRMS = 1.5 V  
VRMS = 5 V  
VRMS = 5 V  
VRMS = 1.5 V  
–230  
–170  
Va = 2 V  
Va = 5 V  
–156  
–2  
Output current  
µA  
Va = 2 V  
Va = 5 V  
–14  
Gain constant(2)  
Va = 6 V, TA = 25°C  
–1.1  
12.0  
–1.0  
–0.9  
A/A  
GATE DRIVER  
VOH  
VOL  
High-level output voltage  
Low-level output voltage  
IOUT = –200 mA,  
IOUT = 200 mA  
IOUT = 10 mA  
IOUT = 50 mA,  
CLOAD = 1 nF  
CLOAD = 1 nF  
CLOAD = 10 nF  
VCC = 15 V  
VCC = 0 V  
12.8  
1.0  
300  
0.9  
35  
V
V
2.2  
500  
1.5  
mV  
V
Low-level UVLO voltage  
Output rise time(1)  
Output fall time(1)  
ns  
ns  
A
35  
Output peak current(1)  
1.0  
(1) Ensured by design. Not production tested.  
IIAC ´ V -1.5V  
(
)
VAO  
K =  
( )  
V
2 ´ I  
é
ù
(
)
VRMS  
MOUT  
ë
û
(2) Gain constant.  
Copyright © 2003–2008, Texas Instruments Incorporated  
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5
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
PACKAGE DESCRIPTION  
Q PACKAGE  
(TOP VIEW)  
J, N and DW PACKAGES  
(TOP VIEW)  
GND  
PKLMT  
CAO  
GTDRV  
VCC  
CT  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
3
2
1
20 19  
18  
CT  
5
4
6
7
8
ISENSE  
CAOUT  
N/C  
ISENSE  
MOUT  
IAC  
SS  
RSET  
VSENSE  
SS  
N/C  
RSET  
17  
16  
15  
14  
MOUT  
IAC  
VAO  
VRMS  
10 ENA  
VREF  
VSENSE  
9
9 10 11 12 13  
N/C − No connection  
6
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Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
TERMINAL FUNCTIONS  
TERMINAL  
PACKAGES  
I/O  
DESCRIPTION  
NAME  
J/N/DW  
Q/L  
Output of the wide bandwidth current amplifier and one of the inputs to the PWM duty-cycle  
comparator. The output signal generated by this amplifier commands the PWM to force the correct  
input current. The output can swing from 0.1 V to 7.5 V.  
CAO  
3
4
O
CT  
14  
10  
18  
13  
I
I
Capacitor from CT to GND sets the PWM oscillator frequency.  
A nominal voltage above 2.65 V on this pin allows the device to begin operating. Once operating,  
the device shuts off if this pin goes below 2.15 V nominal.  
ENA  
All bypass and timing capacitors connected to GND should have leads as short and direct as  
possible. All voltages are measured with respect GND.  
GND  
1
2
–
Output of the PWM is a 1.5-A peak totem-pole MOSFET gate driver on GTDRV. Use a series gate  
resistor of at least 5 Ω to prevent interaction between the gate impedance and the GTDRV output  
driver that might cause the GTDRV output to overshoot excessively. Some overshoot of the  
GTDRV output is always expected when driving a capacitive load.  
GTDRV  
16  
20  
O
Current input to the multiplier, proportional to the instantaneous line voltage. This input to the  
analog multiplier is a current. The multiplier is tailored for very low distortion from this current input  
(IAC) to MOUT, so this is the only multiplier input that should be used for sensing instantaneous  
line voltage.  
IAC  
6
4
8
5
I
I
Switch current sensing input. This is the inverting input to the current amplifier. This input and the  
non-inverting input MOUT remain functional down to and below GND. Care should be taken to  
avoid taking these inputs below –0.5 V, because they are protected with diodes to GND.  
ISENSE  
Multiplier output and current sense plus. The output of the analog multiplier and the non-inverting  
input of the current amplifier are connected together at MOUT. The cautions about taking ISENSE  
below –0.5 V also apply to MOUT. As the multiplier output is a current, this is a high-impedance  
input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject  
GND noise. IMOUT ≤ 2 × IAC  
MOUT  
5
7
I/O  
Peak limit. The threshold for PKLMT is 0.0 V. Connect this input to the negative voltage on the  
current sense resistor. Use a resistor to REF to offset the negative current sense signal up to GND.  
PKLMT  
RSET  
2
3
I
I
Oscillator charging current and multiplier limit set. A resistor from RSET to ground programs  
oscillator charging current.  
12  
15  
Soft-start. SS remains at GND as long as the device is disabled or VCC is too low. SS pulls up to  
over 3 V by an internal 14-µA current source when both VCC becomes valid and the device is  
enabled. SS acts as the reference input to the voltage amplifier if SS is below VREF. With a large  
capacitor from SS to GND, the reference to the voltage regulating amplifier rises slowly, and  
increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS  
will quickly discharge to ground and disable the PWM.  
SS  
13  
17  
I
VAO  
VCC  
7
9
I
I
Voltage amplifier output  
Positive supply rail  
15  
19  
Used to set the peak limit point and as an internal reference for various device functions. This  
voltage must be present for the device to operate.  
VREF  
9
8
12  
10  
14  
O
I
One of the inputs into the multiplier. This pin provides the input RMS voltage to the multiplier  
circuitry.  
VRMS  
This pin provides the feedback from the output. This input goes into the voltage error amplifier and  
the output of the error amplifier is another of the inputs into the multiplier circuit.  
VSENSE  
11  
I
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Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
FUNCTIONAL DESCRIPTION  
The UC3854A and UC3854B family of products are designed as pin compatible upgrades to the industry  
standard UC3854 active power factor correction circuits. The circuit enhancements allow the user to eliminate in  
most cases several external components currently required to successfully apply the UC3854. In addition,  
linearity improvements to the multiply, square and divide circuitry optimizes overall system performance. Detailed  
descriptions of the circuit enhancements are provided below. For in-depth design applications reference data  
refer to the application notes, UC3854 Controlled Power Factor Correction Circuit Design (SLUA144) and  
UC3854A and UC3854B Advanced Power Factor Correction Control ICs (SLUA177).  
Multiply/Square and Divide  
-1  
æ
ö
K =  
ç
è
÷
ø
V
The UC3854A/B multiplier design maintains the same gain constant  
relationship between the inputs and output current is given as:  
as the UC3854. The  
V
-1.5V  
(
)
VAO  
IMOUT = IIAC  
´
2
K ´ V  
(
)
VRMS  
(1)  
This is nearly the same as the UC3854, but circuit differences have improved the performance and application.  
The first difference is with the IAC input. The UC3854A/B regulated this pin voltage to the nominal 500 mV over  
the full operating temperature range, rather than the 6.0 V used on the UC3854. The low offset voltage  
eliminates the need for a line zero crossing compensating resistor to VREF from IAC that UC3854 designs  
require. The maximum current at high line into IAC should be limited to 250 µA for best performance.  
Therefore, if VVAC(max) = 270 V,  
270´1.414  
RIAC  
=
=1.53MW  
250mA  
(2)  
The VRMS pin linear operating range is improved with the UC3854A/B as well. The input range for VRMS extends  
from 0 V to 5.5 V. Since the UC3854A squaring circuit employs an analog multiplier, rather than a linear  
approximation, accuracy is improved, and discontinuities are eliminated. The external divider network connected  
to VRMS should produce 1.5 V at low line (85 VAC). This puts 4.77 V on VRMS at high line (270 VAC) which is  
well within its operating range.  
The voltage amplifier output forms the third input to the multiplier and is internally clamped to 6.0 V. This  
eliminated an external zener clamp often used in UC3854 designs. The offset voltage at this input to the  
multiplier has been raised on the UC3854A/B to 1.5 V.  
The multiplier output pin, which is also common to the current amplifier non-inverting input, has a –0.3 V to 5.0 V  
output range, compared to the –0.3 V to 2.5 V range of the UC3854. This improvement allows the UC3854A/B to  
be used in applications where the current sense signal amplitude is very large.  
8
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Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
Voltage Amplifier  
The UC3854A/B voltage amplifier design is essentially similar to the UC3854 with two exceptions. The first is  
with the internal connection. The lower voltage reduces the amount of charge on the compensation capacitors,  
which provides improved recovery form large signal events, such as line dropouts, or power interruption. It also  
minimizes the dc current flowing through the feedback. The output of the voltage amplifier is also changed. In  
addition to a 6.0-V temperature compensated clamp, the output short circuit current has been lowered to 2 mA  
typical, and an active pull down has replaced the passive pull down of the UC3854.  
Current Amplifier  
The current amplifier for an average current PFC controller needs a low offset voltage in order to minimize ac line  
current distortion. With this in mind, the UC3854A/B current amplifier has improved the input offset voltage from  
±4 mV to 0 V to ±3 mV. The negative offset of the UC3854A/B assures that the PWM circuit will not drive the  
MOSFET is the current command is zero (both current amplifier inputs zero.) Previous designs required an  
external offset cancellation network to implement this key feature. The bandwidth of the current amplifier has  
been improved as well to 5 MHz typical. While this is not generally an issue at 50 Hz or 60 Hz inputs, it is  
essential for 400 Hz input avionics applications.  
Miscellaneous  
Several other important enhancements have been implemented in the UC3854A/B. AVCC supply voltage clamp at  
20 V allows the controller to be current fed if desired. The lower startup supply current (250 µA typical),  
substantially reduces the power requirements of an offline startup resistor. The 10.5 V/10 V UVLO option  
(UC3854B) enables the controller to be powered off of an auxiliary 12-V supply.  
The VREF GOOD comparator assures that the MOSFET driver output remains low if the supply of the 7.5 V  
reference are not yet up. This improvement eliminates the need for external Schottky diodes on the PKLMT and  
Mult Out pins that some UC3854 designs require. The propagation delay of the disable feature has been  
improved to 300 ns typical. This delay was proportional to the size of the VREF capacitor on the UC3854, and is  
typically several orders of magnitude slower.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
TYPICAL CHARACTERISTICS  
GATE DRIVE TIMING  
vs  
LOAD CAPACITANCE  
GATE DRIVE MAXIMUM DUTY CYCLE  
vs  
OSCILLATOR CHARGING RESISTANCE  
800  
100  
95  
90  
85  
80  
700  
Fall Time  
600  
500  
400  
Rise Time  
300  
200  
100  
0
75  
70  
0
0.01  
0.02  
0.03  
0.04  
0.05  
1000  
10 k  
100 k  
R
SET  
− Oscillator Charging Resistance − Ω  
C
LOAD  
− Load Capacitance − µF  
Figure 1.  
Figure 2.  
MULTIPLIER GAIN CONSTANT  
MULTIPLIER GAIN CONSTANT  
vs  
vs  
SUPPLY CURRENT  
SUPPLY CURRENT  
1.20  
1.20  
VA Out = 3.5 V  
VA Out = 5 V  
1.16  
1.12  
1.08  
1.16  
1.12  
1.08  
V
RMS  
= 1.5 V  
V
RMS  
= 1.5 V  
V
RMS  
= 5 V  
1.04  
1.00  
1.04  
1.00  
0.96  
0.96  
0.92  
0.88  
V
RMS  
= 5 V  
0.92  
0.88  
V
RMS  
= 3 V  
V
RMS  
= 1.5 V  
0.84  
0.80  
0.84  
0.80  
0
50  
100  
150  
200  
250  
0
50  
I
100  
150  
200  
250  
− Supply Current − µA  
I
− Supply Current − µA  
AC  
AC  
Figure 3.  
Figure 4.  
10  
Submit Documentation Feedback  
Copyright © 2003–2008, Texas Instruments Incorporated  
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
UC1854A  
UC2854A, UC2854B  
UC3854A, UC3854B  
www.ti.com  
SLUS329E–MONTH 2003–REVISED JANUARY 2008  
TYPICAL CHARACTERISTICS (continued)  
CURRENT AMPLIFIER GAIN  
VOLTAGE AMPLIFIER GAIN  
vs  
vs  
FREQUENCY  
FREQUENCY  
120  
100  
140  
120  
100  
PHASE  
PHASE  
120  
100  
−90  
80  
80  
80  
60  
40  
20  
−45  
−0  
60  
40  
20  
60  
40  
20  
0
−20  
0
0
GAIN  
= 5.992 MHz  
−40  
f
CO  
−20  
10 M  
−20  
100  
−60  
10 k  
GAIN  
1000  
10 k  
1 M  
100 k  
1 M 10 M  
f − Frequency − Hz  
f − Frequency − Hz  
Figure 5.  
Figure 6.  
OSCILLATOR FREQUENCY  
vs  
LIMIT SET RESISTANCE AND  
TIMING CAPACITANCE  
1 k  
200 pF  
100 pF  
1 nF  
3 nF  
100  
500 pF  
10 nF  
10  
5 nF  
2 nF  
0
1
10  
100  
R
SET  
− Multiplier Limit Set Resistance − kΩ  
Figure 7.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Link(s): UC1854A UC2854A, UC2854B UC3854A, UC3854B  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
5962-9326102M2A  
5962-9326102MEA  
OBSOLETE  
ACTIVE  
LCCC  
CDIP  
FK  
J
20  
16  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-55 to 125  
1
-55 to 125 5962-9326102ME  
A
UC1854BJ/883B  
UC1854BJ  
ACTIVE  
ACTIVE  
CDIP  
CDIP  
J
J
16  
16  
1
1
TBD  
TBD  
A42  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125 UC1854BJ  
UC1854BJ883B  
-55 to 125 5962-9326102ME  
A
UC1854BJ/883B  
UC1854BL  
UC1854BL883B  
UC2854ADW  
OBSOLETE  
OBSOLETE  
ACTIVE  
TO/SOT  
TO/SOT  
SOIC  
L
L
20  
20  
16  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
-55 to 125  
-55 to 125  
DW  
40  
40  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
UC2854ADW  
UC2854ADW  
UC2854ADW  
UC2854ADW  
UC2854AN  
UC2854ADWG4  
UC2854ADWTR  
UC2854ADWTRG4  
UC2854AN  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
DW  
DW  
DW  
N
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
N / A for Pkg Type  
2000  
2000  
25  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
UC2854ANG4  
UC2854BDW  
N
25  
Green (RoHS  
& no Sb/Br)  
N / A for Pkg Type  
UC2854AN  
DW  
DW  
DW  
DW  
N
40  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
N / A for Pkg Type  
UC2854BDW  
UC2854BDW  
UC2854BDW  
UC2854BDW  
UC2854BN  
UC2854BDWG4  
UC2854BDWTR  
UC2854BDWTRG4  
UC2854BN  
40  
Green (RoHS  
& no Sb/Br)  
2000  
2000  
25  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
Orderable Device  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
UC2854BNG4  
UC2854BQ  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PLCC  
PLCC  
N
16  
20  
20  
25  
46  
46  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU SN  
N / A for Pkg Type  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
UC2854BN  
UC2854BQ  
UC2854BQ  
FN  
FN  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
UC2854BQG3  
Green (RoHS  
& no Sb/Br)  
CU SN  
-40 to 85  
UC2854J  
ACTIVE  
ACTIVE  
CDIP  
SOIC  
J
16  
16  
1
TBD  
A42  
N / A for Pkg Type  
-40 to 85  
0 to 70  
UC2854J  
UC3854ADW  
DW  
40  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
UC3854ADW  
UC3854ADWG4  
UC3854ADWTR  
UC3854ADWTRG4  
UC3854AN  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
OBSOLETE  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
DW  
DW  
DW  
N
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
20  
40  
2000  
2000  
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Call TI  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
N / A for Pkg Type  
N / A for Pkg Type  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
UC3854ADW  
UC3854ADW  
UC3854ADW  
UC3854AN  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
UC3854ANG4  
UC3854BDW  
N
25  
Green (RoHS  
& no Sb/Br)  
UC3854AN  
DW  
DW  
DW  
DW  
N
40  
Green (RoHS  
& no Sb/Br)  
UC3854BDW  
UC3854BDW  
UC3854BDW  
UC3854BDW  
UC3854BN  
UC3854BDWG4  
UC3854BDWTR  
UC3854BDWTRG4  
UC3854BN  
40  
Green (RoHS  
& no Sb/Br)  
2000  
2000  
25  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
UC3854BNG4  
UC3854BQ  
N
25  
Green (RoHS  
& no Sb/Br)  
UC3854BN  
UTR  
TBD  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) Only one of markings shown within the brackets will appear on the physical device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF UC1854B, UC2854B, UC2854M, UC3854A, UC3854B :  
Catalog: UC3854B, UC2854  
•
Enhanced Product: UC2854B-EP  
•
Military: UC2854BM, UC1854A, UC1854B  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications  
•
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
Military - QML certified for Military and Defense Applications  
•
Addendum-Page 4  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UC3854ADWTR  
SOIC  
DW  
16  
2000  
330.0  
16.4  
10.75 10.7  
2.7  
12.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC DW 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 38.0  
UC3854ADWTR  
2000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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VISHAY
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