5962-9165401MXA_技术文档

August 1998

100355

Low Power Quad Multiplexer/Latch

puts. A HIGH signal on the Master Reset (MR) input over-

rides all the other inputs and forces the Q outputs LOW. All

inputs have 50 kΩ pulldown resistors.

General Description

The 100355 contains four transparent latches, each of which

can accept and store data from two sources. When both En-

able (E_n) inputs are LOW, the data that appears at an output

is controlled by the Select (S_n) inputs, as shown in the Oper-

ating Mode table. In addition to routing data from either D₀or

D₁, the Select inputs can force the outputs LOW for the case

where the latch is transparent (both Enables are LOW) and

can steer a HIGH signal from either D₀or D₁to an output.

The Select inputs can be tied together for applications re-

quiring only that data be steered from either D₀or D₁. A

positive-going signal on either Enable input latches the out-

Features

n Greater than 40% power reduction of the 100155

n 2000V ESD protection

n Pin/function compatible with 100155

=

n Voltage compensated operating range −4.2V to −5.7V

n Standard Microcircuit Drawing

(SMD) 5962-9165401

Logic Symbol

DS100294-1

Pin Names

Description

E₁, E₂

S₀, S₁

MR

Enable Inputs (Active LOW)

Select Inputs

Master Reset

D

_na–D_nd

Data Inputs

Q_a–Q_d

Data Outputs

Complementary Data Outputs

Connection Diagrams

24-Pin DIP

24-Pin Quad Cerpak

DS100294-3

DS100294-2

DS100294

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Logic Diagram

DS100294-5

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2

Operating Mode Table

Controls

Outputs

E₁

H

X

L

E₂

X

H

L

S₁

X

L

S₀

X

L

Q_n

Latched (Note 1)

D_0x

D_0x+ D_1x

L

H

L

H

L

H

D_1x

=

H

L

HIGH Voltage Level

LOW Voltage Level

=

X

Don’t Care

Note 1: Stores data present before E went HIGH

Truth Table

Inputs

Outputs

MR

H

L

E₁

X

L

E₂

X

L

S₁

X

H

L

S₀D_1xD_0x

Q_x

H

L

Q_x

L

X

H

L

X

H

L

X

H

L

H

L

H

L

X

H

X

L

H

L

H

L

H

L

X

H

L

H

X

H

L

H

L

H

X

H

X

Latched (Note 1)

L

3

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Absolute Maximum Ratings (Note 2)

ESD (Note 3)

≥2000V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications. Above

which the useful life may be impaired.

Recommended Operating

Conditions

Case Temperature (T_C)

Military

Storage Temperature (T_STG

)

−65˚C to +150˚C

−55˚C to +125˚C

−5.7V to −4.2V

Maximum Junction Temperature (T_J)

Ceramic

Supply Voltage (V_EE

)

+175˚C

−7.0V to +0.5V

V_EEto +0.5V

−50 mA

Note 2: Absolute maximum ratings are those values beyond which the de-

vice may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

V_EEPin Potential to Ground Pin

Input Voltage (DC)

Note 3: ESD testing conforms to MIL-STD-883, Method 3015.

Output Current (DC Output HIGH)

Military Version

DC Electrical Characteristics

=

V_EE−4.2V to −5.7V, V_CCV_CCAGND, T_C−55˚C to +125˚C

Symbol

Parameter

Min

Max

Units

mV

T_C

0˚C to +125˚C

−55˚C

Conditions

Notes

V_OH

Output HIGH Voltage −1025 −870

−1085 −870

=

V_INV_{IH (Max)}

Loading with

(Notes 4, 5,

6)

V_OL

Output LOW Voltage

−1830 −1620

−1830 −1555

0˚C to +125˚C

−55˚C

or V_{IL (Min)}

50Ω to −2.0V

V_OHCOutput HIGH Voltage −1035

−1085

0˚C to +125˚C

−55˚C

=

V_INV_{IH (Min)}

Loading with

(Notes 4, 5,

6)

V_OLC

V_IH

V_IL

I_IL

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input LOW Current

−1610

−1555

0˚C to +125˚C

−55˚C

or V_{IL (Max)}

50Ω to −2.0V

−1165 −870

−55˚C to

+125˚C

Guaranteed HIGH Signal

for ALL Inputs

(Notes 4, 5,

6, 7)

−1830 −1475

0.50

mV

µA

−55˚C to

+125˚C

Guaranteed LOW Signal

for ALL Inputs

(Notes 4, 5,

6, 7)

=

V_EE−4.2V

−55˚C to

+125˚C

(Notes 4, 5,

6)

=

V_INV_{IL (Min)}

I_IH

Input HIGH Current

S₀, S₁

220

350

340

430

320

500

490

630

E₁, E₂

µA

0˚C to +125˚C

=

V_EE−5.7V

D

_na–D_nd

=

V_INV_{IH (Max)}

MR

(Notes 4, 5,

6)

S₀, S₁

E₁, E₂

µA

−55˚C

D

_na–D_nd

MR

I_EE

Power Supply Current

−95

−32

mA

−55˚C to +125˚C Inputs Open

(Notes 4, 5,

6)

Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately

without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case

condition at cold temperatures.

Note 5: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C Temp., Subgroups 1, 2, 3, 7, and 8.

Note 6: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25˚, +125˚C, and −55˚C Temp., Subgroups 1, 2, 3, 7, and 8.

Note 7: Guaranteed by applying specified input condition and testing V /V

.

OH OL

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4

Military Version

AC Electrical Characteristics

=

V_EE−4.2V to −5.7V, V_CCV_CCAGND

=

Symbol

Parameter

T_C−55˚C

T_C+25˚C

T_C+125˚C Units

Conditions

Notes

Min

Max

Min

Max

Min

Max

t_PLH

t_PHL

Propagation Delay

D_na–D_ndto Output

(Transparent Mode)

Propagation Delay

S₀, S₁to Output

(Transparent Mode)

Propagation Delay

E₁, E₂to Output

Propagation Delay

MR to Output

0.40

2.30

0.50

2.20

0.50

2.60

ns

t_PLH

t_PHL

Figures 1, 2

0.60

0.50

0.60

0.40

3.00

2.60

2.80

1.90

0.80

0.60

0.70

0.40

2.70

2.30

2.60

1.90

0.80

0.70

0.40

3.20

2.70

2.90

1.90

ns

(Notes 8, 9,

10)

t_PLH

t_PHL

t_PLH

t_PHL

t_TLH

t_THL

t_S

Figures 1, 3

Figures 1, 2

(Notes 8, 9,

10)

Transition Time

(Note 11)

20% to 80%, 80% to 20%

Setup Time

D

_na–D_nd

0.90

2.40

1.50

0.90

2.40

1.50

0.90

2.40

1.50

ns

Figure 4

Figure 3

Figure 4

(Note 11)

S₀, S₁

MR (Release Time)

Hold Time

t_H

D_na–D_nd

0.40

0.00

2.00

0.40

0.00

2.00

0.40

0.00

2.00

ns

(Note 11)

S₀, S₁

t_pw(L)

t_pw(H)

Pulse Width LOW E₁, E₂

Pulse Width HIGH MR

ns

Figure 2

Figure 3

(Note 11)

Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately

without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case

condition at cold temperatures.

Note 9: Screen tested 100% on each device at +25˚C, Temperature only, Subgroup A9.

Note 10: Sample tested (Method 5005, Table 1) on each Mfg. lot at +25˚, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 & A11.

Note 11: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).

5

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Test Circuit

DS100294-6

Notes:

=

EE

V

, V

CC

+2V, V

−2.5V

CCA

=

L1 and L2 equal length 50Ω impedance lines

=

R

50Ω terminator internal to scope

T

Decoupling 0.1 µF from GND to V and V

CC EE

All unused outputs are loaded with 50Ω to GND

=

C

L

Fixture and stray capacitance ≤ 3 pF

Pin numbers shown are for flatpak; for DIP see logic symbol

FIGURE 1. AC Test Circuit

(Using Quad Cerpak)

Switching Waveforms

DS100294-7

FIGURE 2. Enable Timing

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6

Switching Waveforms (Continued)

DS100294-8

FIGURE 3. Reset Timing

DS100294-9

Notes:

t

is the minimum time before the transition of the enable that information must be present at the data input.

is the minimum time after the transition of the enable that information must remain unchanged at the data input.

s

h

FIGURE 4. Data Setup and Hold Times

7

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8

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Ceramic Dual-In-Line Package (D)

NS Package Number J24E

24-Lead Ceramic Flatpak (F)

NS Package Number W24C

9

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LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-

VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-

CONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or sys-

tems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, and whose fail-

ure to perform when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5620-6175

Fax: 81-3-5620-6179

Fax: +49 (0) 1 80-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 1 80-530 85 85

English Tel: +49 (0) 1 80-532 78 32

Français Tel: +49 (0) 1 80-532 93 58

Italiano Tel: +49 (0) 1 80-534 16 80

Email: sea.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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Products > Military/Aerospace > Logic > ECL > 100355

100355 Product Folder

Low Power Quad Multiplexer/Latch

General

Description

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& Models

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& Pricing

Features

Datasheet

Title

Size in Kbytes Date

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100355 Low Power Quad

Multiplexer Latch

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148 Kbytes

108 Kbytes

17-Aug-98

100355 Mil-Aero Datasheet

MN100355-X

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Package Availability, Models, Samples & Pricing

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Std

Pack

Size

Package

Type Pins MSL

Models

Package

Marking

Part Number

Status

SPICE IBIS

Qty $US each

[logo]¢Z¢S¢4¢A$E

100355DMQB /Q

5962-

rail

of

15

Full

production

CERDIP

MSL

5962-9165401MXA

24

N/A

50+ $40.8000

Buy Now

9165401MXA

[logo]¢Z¢S¢4¢A

Q$E 100355

FMQB 5962

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rail

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14

Full

production

CERQUAD

CERDIP

MSL

5962-9165401MYA

5962-9165401VXA

100355WFQMLV

24

N/A

50+ $43.2000

MYA

rail [logo]¢Z¢S¢4¢A$E

50+ $265.0000 of 100355J-QMLV

Full

production

15 5962-9165401VXA

[logo]¢Z¢S¢4¢A

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of

N/A

100355WF

QMLV 5962

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CERQUAD

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rail

of

N/A

CERQUAD

MSL

RM100355WFQMLV

24

N/A

$E

[logo]¢Z¢S¢4¢A

100355W-

QMLV 5962

-9165401

rail

50+ $265.0000 of

14

Full

production

CERQUAD

MSL

5962-9165401VYA

24

N/A

VYA $E

General Description

The 100355 contains four transparent latches, each of which can accept and store data from two sources.

When both Enable (E#_n) inputs are LOW, the data that appears at an output is controlled by the Select (S_n)

inputs, as shown in the Operating Mode table. In addition to routing data from either D₀or D₁, the Select

inputs can force the outputs LOW for the case where the latch is transparent (both Enables are LOW) and

can steer a HIGH signal from either D₀or D₁to an output. The Select inputs can be tied together for

applications requiring only that data be steered from either D₀or D₁. A positive-going signal on either Enable

input latches the outputs. A HIGH signal on the Master Reset (MR) input overrides all the other inputs and

forces the Q outputs LOW. All inputs have 50 k Ohm pulldown resistors.

Features

●

Greater than 40% power reduction of the 100155

2000V ESD protection

Pin/function compatible with 100155

Voltage compensated operating range = -4.2V to -5.7V

Standard Microcircuit Drawing (SMD) 5962-9165401

[Information as of 5-Aug-2002]

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型号：	5962-9165401MXA
厂家：	TEXAS INSTRUMENTS
描述：	IC 100K SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP24, CERAMIC, DIP-24, FF/Latch CD 输出元件
文件：	总12页 (文件大小：188K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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