5962-9165501MXX [TI]

100K SERIES, DUAL 8 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDIP24, CERDIP-24;
5962-9165501MXX
型号: 5962-9165501MXX
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

100K SERIES, DUAL 8 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, CDIP24, CERDIP-24

CD 输出元件 逻辑集成电路
文件: 总8页 (文件大小:127K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
August 1998  
100363  
Low Power Dual 8-Input Multiplexer  
n 2000V ESD protection  
n Pin/function compatible with 100163  
n Voltage compensated operating range −4.2V to −5.7V  
n Standard Microcircuit Drawing  
(SMD) 5962-9165501  
General Description  
The 100363 is a dual 8-input multiplexer. The Data Select  
(Sn) inputs determine which bit (An and Bn) will be presented  
at the outputs (Za and Zb respectively). The same bit (0–7)  
will be selected for both the Za and Z b output. All inputs have  
50 kpulldown resistors.  
=
Features  
n 50% power reduction of the 100163  
Logic Symbol  
Pin Names  
S0–S2  
Description  
Data Select Inputs  
A0–A7  
B0–B7  
Za, Zb  
A Data Inputs  
B Data Inputs  
Data Outputs  
DS100310-1  
Connection Diagrams  
24-Pin Quad Cerpak  
24-Pin DIP  
DS100310-3  
DS100310-2  
© 1998 National Semiconductor Corporation  
DS100310  
www.national.com  
Logic Diagram  
DS100310-5  
www.national.com  
2
Truth Table  
Inputs  
Outputs  
Select  
Data  
S2  
S1  
S0  
A7  
B7  
A6  
B6  
A5  
B5  
A4  
A3  
B3  
A2  
B2  
A1  
B1  
A0  
B0  
L
Za  
Zb  
L
B4  
L
L
L
L
L
L
H
H
L
L
L
H
H
L
L
L
L
H
H
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
H
L
L
H
H
L
L
L
H
H
L
H
H
H
H
L
L
H
H
L
H
H
L
H
H
=
=
H
L
HIGH Voltage Level  
LOW Voltage Level  
=
=
Don’t Care  
Blank  
X
3
www.national.com  
Absolute Maximum Ratings (Note 1)  
ESD (Note 2)  
2000V  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
Recommended Operating  
Conditions  
Case Temperature (TC)  
Military  
Above which the useful life may be impared  
Storage Temperature (TSTG  
)
−65˚C to +150˚C  
−55˚C to +125˚C  
−5.7V to −4.2V  
Maximum Junction Temperature (TJ)  
Ceramic  
Supply Voltage (VEE  
)
+175˚C  
−7.0V to +0.5V  
VEE to + 0.5V  
−50 mA  
Note 1: Absolute maximum ratings are those values beyond which the de-  
vice may be damaged or have its useful life impaired. Functional operation  
under these conditions is not implied.  
VEE Pin Potential to Ground Pin  
Input Voltage (DC)  
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.  
Output Current (DC Output HIGH)  
Military Version  
DC Electrical Characteristics  
=
=
=
=
−55˚C to +125˚C  
C
VEE −4.2V to −5.7V, VCC VCCA GND, T  
Symbol  
Parameter  
Min  
Max Units  
TC  
Conditions  
Note  
VOH  
Output HIGH Voltage −1025 −870  
mV  
0˚C to  
+125˚C  
−55˚C  
0˚C to  
+125˚C  
−55˚C  
0˚C to  
+125˚C  
−55˚C  
0˚C to  
+125˚C  
−55˚C  
−55˚C to  
=
−1085 −870  
mV  
mV  
VIN VIH (Max)  
Loading with  
(Notes 3, 4, 5)  
VOL  
Output LOW Voltage −1830 −1620  
or VIL (Min)  
50to −2.0V  
−1830 −1555  
mV  
mV  
VOHC  
VOLC  
VIH  
Output HIGH Voltage −1035  
=
−1085  
mV  
mV  
VIN VIH (Min)  
Loading with  
(Notes 3, 4, 5)  
Output LOW Voltage  
Input HIGH Voltage  
−1610  
or VIL (Max)  
50to −2.0V  
−1555  
mV  
mV  
Guaranteed HIGH Signal for All  
Inputs  
−1165 −870  
(Notes 3, 4, 5, 6)  
+125˚C  
−55˚C to  
+125˚C  
−55˚C to  
+125˚C  
VIL  
Input LOW Voltage  
Input LOW Current  
−1830 −1475  
0.50  
mV  
µA  
Guaranteed LOW Signal for All Inputs (Notes 3, 4, 5, 6)  
=
IIL  
VEE −4.2V  
(Notes 3, 4, 5)  
=
VIN VIL (Min)  
IIH  
Input HIGH Current  
Sn  
An, Bn  
Sn  
265  
340  
385  
490  
µA  
µA  
0˚C to  
+125˚C  
−55˚C  
=
VEE −5.7V  
(Notes 3, 4, 5)  
(Notes 3, 4, 5)  
=
VIN VIH (Max)  
An, Bn  
IEE  
Power Supply  
Current  
−55˚C to  
+125˚C  
Inputs Open  
−87  
−30  
mA  
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately  
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case  
condition at cold temperatures.  
Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.  
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.  
Note 6: Guaranteed by applying specified input condition and testing V /V  
.
OH OL  
www.national.com  
4
AC Electrical Characteristics  
=
=
=
VEE −4.2V to −5.7V, VCC VCCA GND  
=
=
=
TC −55˚C  
TC +25˚C  
TC  
+125˚C  
Symbol  
Parameter  
Units  
Conditions  
Notes  
Min  
Max  
Min  
Max  
Min  
Max  
tPLH  
tPHL  
tPLH  
tPHL  
tTLH  
tTHL  
Propagation Delay  
A0–A7, B0–B7 to Output  
Propagation Delay  
S0–S2 to Output  
0.50  
2.40  
0.60  
2.30  
0.70  
0.80  
0.30  
3.00  
ns  
ns  
ns  
(Notes 7, 8, 9)  
(Note 10)  
0.80  
0.30  
3.00  
1.90  
0.90  
0.30  
2.80  
1.80  
3.40  
2.10  
Figure 1 and  
Figure 2  
Transition Time  
20% to 80%, 80% to 20%  
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately  
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.  
Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9.  
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C, temperatures, Subgroups A10 and A11.  
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).  
Test Circuitry  
DS100310-6  
Notes:  
=
=
EE  
V , V  
CC  
+2V, V  
−2.5V  
CCA  
=
L1 and L2 equal length 50impedance lines  
=
R
50terminator internal to scope  
T
Decoupling 0.1 µF from GND to V and V  
CC  
EE  
All unused outputs are loaded with 50to GND  
=
C
L
Fixture and stray capacitance 3 pF  
Pin numbers shown are for flatpak; for DIP see logic symbol  
FIGURE 1. AC Test Circuit  
5
www.national.com  
Switching Waveforms  
DS100310-7  
FIGURE 2. Propagation Delay and Transition Times  
www.national.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted  
24-Pin Ceramic Dual-In-Line Package (D)  
NS Package Number J24E  
24-Pin Quad Cerpak (F)  
NS Package Number W24B  
7
www.national.com  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-  
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-  
CONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or sys-  
tems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, and whose fail-  
ure to perform when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
National Semiconductor  
Corporation  
Americas  
Tel: 1-800-272-9959  
Fax: 1-800-737-7018  
Email: support@nsc.com  
National Semiconductor  
Europe  
National Semiconductor  
Asia Pacific Customer  
Response Group  
Tel: 65-2544466  
Fax: 65-2504466  
National Semiconductor  
Japan Ltd.  
Tel: 81-3-5620-6175  
Fax: 81-3-5620-6179  
Fax: +49 (0) 1 80-530 85 86  
Email: europe.support@nsc.com  
Deutsch Tel: +49 (0) 1 80-530 85 85  
English Tel: +49 (0) 1 80-532 78 32  
Français Tel: +49 (0) 1 80-532 93 58  
Italiano Tel: +49 (0) 1 80-534 16 80  
Email: sea.support@nsc.com  
www.national.com  
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.  

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