5962-8752501M2A [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET; 双上升沿触发的D型触发器具有清零和预设
| 型号： | 5962-8752501M2A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET |
| 文件： | 总16页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁꢇ ꢃꢄ ꢅꢆ ꢇꢃ
ꢉꢊꢄ ꢋ ꢌꢍ ꢀꢎ ꢆ ꢎꢏꢐ ꢑꢐꢉꢒ ꢐꢑꢆ ꢓꢎ ꢒ ꢒꢐ ꢓꢐꢉ ꢉꢑꢆ ꢔꢌ ꢐ ꢕ ꢋꢎ ꢌ ꢑꢕ ꢋꢍ ꢌꢀ
ꢖ ꢎꢆ ꢗ ꢅꢋ ꢐꢄꢓ ꢄꢁꢉ ꢌ ꢓꢐ ꢀ ꢐꢆ
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
D
D
4.5-V to 5.5-V V
Operation
D
Max t of 10.5 ns at 5 V
pd
Inputs Are TTL-Voltage Compatible
CC
Inputs Accept Voltages to 5.5 V
D
SN54ACT74 . . . J OR W PACKAGE
SN74ACT74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54ACT74 . . . FK PACKAGE
(TOP VIEW)
1CLR
1D
V
CC
13 2CLR
12 2D
1
2
3
4
5
6
7
14
3
2
1
20 19
18
2D
1CLK
NC
1CLK
1PRE
1Q
4
5
6
7
8
NC
17
16
15
14
11
10
9
2CLK
2PRE
2Q
2CLK
NC
1PRE
NC
1Q
2PRE
1Q
8
GND
2Q
9 10 11 12 13
NC − No internal connection
description/ordering information
The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at D can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74ACT74N
SN74ACT74N
Tube
SN74ACT74D
ACT74
Tape and reel
Tape and reel
Tape and reel
Tube
SN74ACT74DR
SN74ACT74NSR
SN74ACT74DBR
SN74ACT74PW
SN74ACT74PWR
SNJ54ACT74J
SNJ54ACT74W
SNJ54ACT74FK
SOP − NS
ACT74
AD74
−40°C to 85°C
SSOP − DB
TSSOP − PW
AD74
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54ACT74J
SNJ54ACT74W
SNJ54ACT74FK
Tube
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉ ꢊꢄꢋ ꢌꢍꢀ ꢎ ꢆ ꢎꢏ ꢐꢑ ꢐꢉ ꢒꢐ ꢑꢆꢓ ꢎ ꢒꢒ ꢐꢓꢐ ꢉ ꢉꢑ ꢆꢔ ꢌꢐ ꢕ ꢋꢎ ꢌꢑꢕ ꢋ ꢍ ꢌꢀ
ꢖꢎ ꢆ ꢗ ꢅ ꢋ ꢐꢄ ꢓ ꢄꢁ ꢉ ꢌ ꢓꢐ ꢀꢐ ꢆ
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR
PRE
L
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
TG
C
Q
C
TG
C
C
TG
C
C
TG
C
D
Q
CLR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉꢊꢄ ꢋ ꢌꢍ ꢀꢎ ꢆ ꢎꢏꢐ ꢑꢐꢉꢒ ꢐꢑꢆ ꢓꢎ ꢒ ꢒꢐ ꢓꢐꢉ ꢉꢑꢆ ꢔꢌ ꢐ ꢕ ꢋ ꢎꢌ ꢑ ꢕꢋꢍ ꢌ ꢀ
ꢖ ꢎꢆ ꢗ ꢅꢋ ꢐꢄꢓ ꢄꢁꢉ ꢌ ꢓꢐ ꢀ ꢐꢆ
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ACT74
SN74ACT74
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
8
mA
mA
ns/V
°C
OH
OL
∆t/∆v
8
T
−55
125
−40
85
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢈ ꢀꢁꢇ ꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉ ꢊꢄꢋ ꢌꢍꢀ ꢎ ꢆ ꢎꢏ ꢐꢑ ꢐꢉ ꢒꢐ ꢑꢆꢓ ꢎ ꢒꢒ ꢐꢓꢐ ꢉ ꢉꢑ ꢆꢔ ꢌꢐ ꢕ ꢋꢎ ꢌꢑꢕ ꢋ ꢍ ꢌꢀ
ꢖꢎ ꢆ ꢗ ꢅ ꢋ ꢐꢄ ꢓ ꢄꢁ ꢉ ꢌ ꢓꢐ ꢀꢐ ꢆ
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54ACT74
SN74ACT74
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.49
I
I
= −50 µA
OH
5.4
5.49
5.4
5.4
3.86
4.86
3.7
3.76
4.76
V
OH
= −24 mA
V
OH
4.7
†
†
I
I
= −50 mA
3.86
OH
= −75 mA
3.85
OH
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
OL
0.36
0.36
0.5
0.44
0.44
V
OL
I
= 24 mA
V
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
1
OL
I
I
V = V
or GND
or GND,
0.1
2
1
µA
µA
I
I
CC
V = V
I = 0
O
40
20
CC
I
CC
One input at 3.4 V,
Other inputs at GND or V
‡
∆I
CC
5.5 V
5 V
0.6
3
1.6
1.5
mA
pF
CC
C
V = V or GND
I CC
i
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
timing characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
SN54ACT74
SN74ACT74
A
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
145
85
125
MHz
clock
PRE or CLR low
CLK
5
5
3
0
1
7
7
6
6
ns
w
Data
4
3.5
0
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
PRE or CLR inactive
0.5
1
1
h
switching characteristics over recommended operating free-air temperature (unless otherwise
noted) (see Figure 1)
SN54ACT74
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
210
5.5
6
PARAMETER
UNIT
MIN
MAX
MIN
145
1
MAX
f
t
t
t
t
85
1
MHz
ns
max
PLH
PHL
PLH
PHL
9.5
10
11
11.5
12.5
14
PRE or CLR
CLK
Q or Q
Q or Q
1
1
1
7.5
6
1
ns
1
10
1
12
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃ
ꢉꢊꢄ ꢋ ꢌꢍ ꢀꢎ ꢆ ꢎꢏꢐ ꢑꢐꢉꢒ ꢐꢑꢆ ꢓꢎ ꢒ ꢒꢐ ꢓꢐꢉ ꢉꢑꢆ ꢔꢌ ꢐ ꢕ ꢋ ꢎꢌ ꢑ ꢕꢋꢍ ꢌ ꢀ
ꢖ ꢎꢆ ꢗ ꢅꢋ ꢐꢄꢓ ꢄꢁꢉ ꢌ ꢓꢐ ꢀ ꢐꢆ
SCAS520H − AUGUST 1995 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature (unless otherwise
noted) (see Figure 1)
SN74ACT74
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
210
5.5
6
PARAMETER
UNIT
MIN
MAX
MIN
145
3
MAX
f
t
t
t
t
125
2.5
3
MHz
ns
max
PLH
PHL
PLH
PHL
9.5
10
11
10.5
11.5
13
PRE or CLR
CLK
Q or Q
Q or Q
3
4
7.5
6
4
ns
3.5
10
3
11.5
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
C
= 50 pF,
f = 1 MHz
45
pF
pd
L
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
S1
Open
500 Ω
From Output
Under Test
TEST
S1
C
= 50 pF
L
t
/t
Open
PLH PHL
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.5 V
3 V
0 V
1.5 V
1.5 V
Input
3 V
0 V
Input
1.5 V
VOLTAGE WAVEFORMS
t
t
t
PHL
PLH
V
OH
3 V
In-Phase
Output
50% V
50% V
CC
CC
Timing Input
Data Input
1.5 V
V
OL
0 V
t
h
t
PHL
PLH
t
su
V
OH
3 V
0 V
Out-of-Phase
Output
50% V
50% V
1.5 V
1.5 V
CC
CC
V
OL
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-8752501M2A
5962-8752501MCA
5962-8752501MDA
SN74ACT74D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
D
SOIC
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ACT74DBLE
SN74ACT74DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ACT74DBRE4
SN74ACT74DE4
SN74ACT74DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
D
14
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ACT74DRE4
SN74ACT74N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ACT74NE4
SN74ACT74NSR
SN74ACT74NSRE4
SN74ACT74PW
SN74ACT74PWE4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ACT74PWLE
SN74ACT74PWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ACT74PWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ACT74FK
SNJ54ACT74J
SNJ54ACT74W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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