5962-8752501SCA [NSC]
IC ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14, FF/Latch;
| 型号： | 5962-8752501SCA |
| 厂家： | 
National Semiconductor |
| 描述： | IC ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14, FF/Latch CD 输出元件 |
| 文件： | 总8页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54AC74 • 54ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
Asynchronous Inputs:
General Description
The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Clear and Set inputs and complementary (Q, Q) outputs. In-
formation at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive-going pulse. After the Clock
Pulse input threshold voltage has been passed, the Data in-
put is locked out and information present will not be trans-
ferred to the outputs until the next rising edge of the Clock
Pulse input.
Features
n ICC reduced by 50%
n Output source/sink 24 mA
n ’ACT74 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC74: 5962-88520
— ’ACT74: 5962-87525
Logic Symbols
DS100266-2
DS100266-1
Pin Names
D1, D2
CP1, CP2
D1, CD2
D1, SD2
Q1, Q1, Q2, Q2
Description
Data Inputs
IEEE/IEC
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
C
S
DS100266-3
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100266
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Connection Diagrams
Pin Assignment for DIP
and Flatpak
Pin Assignment for LCC
DS100266-4
DS100266-5
Truth Table
(Each Half)
Inputs
Outputs
SD
L
CD
H
L
CP
X
D
X
X
X
H
L
Q
Q
H
L
L
H
H
L
X
L
X
H
H
L
H
N
H
H
H
H
H
H
L
N
H
L
X
Q0
Q0
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
N =
LOW-to-HIGH Clock Transition
=
Q (Q ) Previous Q(Q) before LOW-to-HIGH Transition of Clock
0
0
Logic Diagram
DS100266-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
2.1
=
VIH
Minimum High
Level Input
Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
VOUT 0.1V
3.15
3.85
0.9
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low
Level Input
Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High
Level Output
Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
−12 mA
V
V
IOH
−24 mA
−24 mA
=
IOUT 50 µA
VOL
Maximum Low
Level Output
Voltage
(Note 2)
=
VIN VIL or VIH
3.0
4.5
5.5
5.5
0.5
0.5
0.5
12 mA
V
IOL
24 mA
24 mA
=
VI VCC, GND
±
IIN
Maximum Input
Leakage Current
1.0
µA
3
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DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
=
VOLD 1.65V Max
IOLD
IOHD
ICC
(Note 3) Minimum
Dynamic Output
Current
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
=
Maximum Quiescent
Supply Current
40.0
VIN VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed
Limits
=
VIH
Minimum High
Level Input
Voltage
4.5
5.5
4.5
5.5
2.0
VOUT 0.1V
V
2.0
0.8
0.8
or VCC − 0.1V
=
VIL
Maximum Low
Level Input
Voltage
VOUT 0.1V
V
V
or VCC − 0.1V
=
VOH
Minimum High
Level Output
Voltage
4.5
5.5
4.4
5.4
IOUT −50 µA
(Note 5)
=
VIN VIL or VIH
IOH −24 mA
−24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
VOL
Maximum Low
Level Output
Voltage
IOUT 50 µA
0.1
(Note 5)
=
VIN VIL or VIH
IOL 24 mA
24 mA
VI VCC, GND
4.5
5.5
5.5
0.50
0.50
V
=
±
IIN
Maximum Input
Leakage Current
Maximum
1.0
µA
mA
=
VI VCC − 2.1V
ICCT
5.5
1.6
I
CC/Input
=
VOLD 1.65V Max
IOLD
IOHD
ICC
(Note 6) Minimum
Dynamic Output
Current
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
40.0
=
Maximum Quiescent
Supply Current
VIN VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
I for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 7:
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4
AC Electrical Characteristics
VCC
(V)
54AC
TA −55˚C to +125˚C
=
Symbol
Parameter
Units
Fig.
No.
=
(Note 8)
CL 50 pF
Min
70
Max
fmax
Maximum Clock
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
MHz
ns
Frequency
95
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
13.0
9.5
14.0
10.5
17.5
12.0
13.5
10.0
ns
ns
Propagation Delay
CPn to Qn or Qn
ns
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
Fig.
No.
=
CL 50 pF
(Note 9)
3.3
Guaranteed Limits
ts
Set-up Time, HIGH or LOW
Dn to CPn
5.0
4.0
0.5
0.5
8.0
5.5
0.5
0.5
ns
ns
ns
ns
5.0
th
Hold Time, HIGH or LOW
Dn to CPn
3.3
5.0
tw
CPn or CDn or SDn
Pulse Width
3.3
5.0
trec
Recovery Time
3.3
CDn or SDn to CP
5.0
±
Note 9: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
=
VCC
TA −55˚C
Symbol
Parameter
(V)
to +125˚C
Units
=
CL 50 pF
(Note 10)
Min
Max
fmax
Maximum Clock
5.0
5.0
5.0
5.0
5.0
85
MHz
ns
Frequency
tPLH
tPHL
tPLH
tPHL
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
1.0
1.0
1.0
1.0
11.5
12.5
14.0
12.0
ns
ns
Propagation Delay
CPn to Qn or Qn
ns
5
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AC Electrical Characteristics (Continued)
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
=
Symbol
Parameter
TA
Units
VCC
(V)
Fig.
No.
−55˚C
=
CL 50
pF
Guaranteed
Limits
(Note 11)
5.0
ts
Set-up Time, HIGH or
LOW
4.0
ns
ns
Dn to CPn
th
Hold Time, HIGH or
LOW
5.0
1.0
Dn to CPn
tw
CPn or CDn or SDn
Pulse Width
5.0
5.0
7.0
0.5
ns
ns
trec
Recovery Time
CDn or SDn to CP
±
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
=
VCC 5.0V
CPD
35.0
pF
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
14-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J14A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Ceramic Flatpak (F)
NS Package Number W14B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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