5962-01-210-8634 [TI]
IC,LINE DRIVER,4 DRIVER,BIPOLAR,DIP,14PIN,PLASTIC;
| 型号： | 5962-01-210-8634 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,LINE DRIVER,4 DRIVER,BIPOLAR,DIP,14PIN,PLASTIC 驱动 光电二极管 驱动器 |
| 文件： | 总18页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈꢈ ꢂ ꢄ ꢄ ꢅ ꢆ ꢇꢉ ꢈꢂ ꢄꢄ
ꢊ ꢋꢌꢍꢎ ꢋꢏꢐ ꢑ ꢐ ꢒꢇꢑ ꢍ ꢎꢒ ꢓ ꢑꢎ ꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
SN55188 . . . J OR W PACKAGE
SN75188 . . . D, N, OR NS PACKAGE
MC1488 . . . N PACKAGE
(TOP VIEW)
D
Meet or Exceed the Requirements of ANSI
TIA/EIA-232-E and ITU Recommendation
V.28
D
D
D
D
D
Current-Limited Output: 10 mA Typical
V
V
CC +
4B
1
2
3
4
5
6
7
14
13
12
Power-Off Output Impedance: 300 Ω
Minimum
CC−
1A
1Y
2A
2B
2Y
4A
Slew Rate Control by Load Capacitor
Flexible Supply-Voltage Range
11 4Y
10 3B
Input Compatible With Most TTL Circuits
9
8
3A
3Y
GND
description/ordering information
The MC1488, SN55188, and SN75188 are
monolithic quadruple line drivers designed to
interface data terminal equipment with data
communications equipment in conformance with
ANSI TIA/EIA-232-E, using a diode in series with
each supply-voltage terminal as shown under
typical applications.
SN55188 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
1Y
NC
2A
4A
17 NC
4
5
6
7
8
The SN55188 is characterized for operation over
the full military temperature range of −55°C to
125°C. The MC1488 and SN75188 are
characterized for operation from 0°C to 70°C.
16
15
14
4Y
NC
3B
NC
2B
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 25
MC1488N
MC1488N
PDIP (N)
Tube of 25
Tube of 50
Reel of 2500
Reel of 2000
SN75188N
SN75188N
SN75188D
0°C to 70°C
SOIC (D)
SOP (NS)
SN75188
SN75188DR
SN75188NSR
SN55188J
SN75188
SN55188J
SNJ55188J
SNJ55188W
SNJ55188FK
CDIP (J)
Tube of 25
SNJ55188J
SNJ55188W
SNJ55188FK
−55°C to 125°C
CFP (W)
Tube of 150
Tube of 55
LCCC (FK)
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ ꢆꢇ ꢈ ꢈꢂ ꢄꢄ ꢅ ꢆ ꢇꢉ ꢈ ꢂꢄ ꢄ
ꢊꢋ ꢌ ꢍꢎ ꢋ ꢏꢐ ꢑ ꢐ ꢒ ꢇꢑ ꢍꢎ ꢒ ꢓꢑ ꢎꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
FUNCTION TABLE
(drivers 2−4)
A
H
L
B
H
X
L
Y
L
H
H
X
H = high level, L = low level,
X = irrelevant
logic diagram (positive logic)
3
2
1A
1Y
4
5
2A
2B
6
2Y
9
3A
3B
8
3Y
10
12
13
4A
4B
11
4Y
Positive logic
Y = A (driver 1)
Y = AB or A + B (drivers 2 thru 4)
schematic (each driver)
To Other
Drivers
V
CC+
8.2 kΩ
6.2 kΩ
A
B
Input(s)
70 Ω
300 Ω
Output
3.6 kΩ
GND
To
Other
Drivers
10 kΩ
3.7 kΩ
70 Ω
V
CC−
To Other Drivers
Resistor values shown are nominal.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈꢈ ꢂ ꢄ ꢄ ꢅ ꢆ ꢇꢉ ꢈꢂ ꢄꢄ
ꢊ ꢋꢌꢍꢎ ꢋꢏꢐ ꢑ ꢐ ꢒꢇꢑ ꢍ ꢎꢒ ꢓ ꢑꢎ ꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
Supply voltage, V
at (or below) 25°C free-air temperature (see Notes 1 and 2) . . . . . . . . . . . . . . . . . 15 V
at (or below) 25°C free-air temperature (see Notes 1 and 2) . . . . . . . . . . . . . . . . −15 V
CC+
CC−
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 7 V
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V
O
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Package thermal impedance, θ (see Notes 3 and 4): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package . . . . . . . . . . . . . . . . 300°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. For operation above 25°C free-air temperature, refer to the maximum supply voltage curve, Figure 6. In the J package, SN55188
chips are alloy mounted.
3. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
JA
J
A
ambient temperature is P = (T (max) − T )/θ . Selecting the maximum of 150°C can affect reliability.
D
J
A
JA
4. The package thermal impedance is calculated in accordance with JESD 51-7.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 125°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
FK
J
1375 mW
1375 mW
1000 mW
11.0 mW/°C
11.0 mW/°C
8.0 mW/°C
880 mW
880 mW
640 mW
275 mW
275 mW
200 mW
W
recommended operating conditions
SN55188
MC1488, SN75188
UNIT
MIN NOM
MAX
15
MIN NOM
MAX
V
V
V
V
Supply voltage
7.5
−7.5
1.9
9
7.5
−7.5
1.9
9
15
V
V
CC+
CC−
IH
Supply voltage
−9
−15
−9
−15
High-level input voltage
Low-level input voltage
Operating free-air temperature
V
0.8
0.8
70
V
IL
T
A
−55
125
0
°C
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ ꢆꢇ ꢈ ꢈꢂ ꢄꢄ ꢅ ꢆ ꢇꢉ ꢈ ꢂꢄ ꢄ
ꢊꢋ ꢌ ꢍꢎ ꢋ ꢏꢐ ꢑ ꢐ ꢒ ꢇꢑ ꢍꢎ ꢒ ꢓꢑ ꢎꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
electrical characteristics over operating free-air temperature range, V
noted)
= 9 V (unless otherwise
CC
SN55188
MC1488, SN75188
UNIT
PARAMETER
TEST CONDITIONS
†
TYP
†
MIN
MAX
MIN TYP
MAX
V
V
= 9 V,
= −9 V
CC+
CC−
6
7
6
7
V
R
= 0.8 V,
= 3 kΩ
IL
L
V
V
High-level output voltage
V
V
OH
V
CC+
V
CC−
= 13.2 V,
= −13.2 V
9
10.5
9
10.5
−7
V
V
= 9 V,
= −9 V
CC+
CC−
‡
−7
−6
−9
−6
−9
V
R
= 1.9 V,
= 3 kΩ
IH
Low-level output voltage
OL
V
CC+
V
CC−
= 13.2 V,
= −13.2 V
L
‡
−10.5
−10.5
I
I
High-level input current
Low-level input current
Short-circuit output
V = 5 V
10
10
µA
IH
I
V = 0
I
−1
−1.6
−1
−9
−1.6
mA
IL
I
V = 0.8 V,
I
V
= 0
−4.6
4.6
−9 −13.5
−6
6
−12
12
mA
mA
Ω
OS(H)
O
§
current at high level
Short-circuit output
I
V = 1.9 V,
I
V
V
= 0
= 0,
9
13.5
9
OS(L)
O
§
current at low level
Output resistance,
power off
V
= 0,
CC+
CC−
r
300
300
o
V
O
= −2 V to 2 V
All inputs at 1.9 V
All inputs at 0.8 V
All inputs at 1.9 V
All inputs at 0.8 V
All inputs at 1.9 V
All inputs at 0.8 V
All inputs at 1.9 V
All inputs at 0.8 V
All inputs at 1.9 V
All inputs at 0.8 V
All inputs at 1.9 V
All inputs at 0.8 V
15
4.5
19
20
6
15
4.5
19
20
6
V
= 9 V,
CC+
No load
25
25
Supply current from
V
= 12 V,
CC+
No load
I
mA
CC+
V
CC+
5.5
7
5.5
7
34
34
V
= 15 V,
CC+
No load, T = 25°C
12
12
A
−13
−18
−17
−0.5
−23
−0.5
−34
−2.5
−13
−18
−17
−0.015
−23
−0.015
−34
−2.5
V
= −9 V,
CC−
No load
V
= −12 V,
CC−
No load
I
Supply current from I
CC−
mA
CC−
V
= −15 V,
CC−
No load, T = 25°C
A
V
= 9 V,
V
= −9 V,
CC+
No load
CC−
333
576
333
576
P
D
Total power dissipation
mW
V
= 12 V,
V
CC−
= −12 V,
CC+
No load
†
‡
All typical values are at T = 25°C.
A
The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for logic voltage
levels only, e.g., if −6 V is a maximum, the typical value is a more negative voltage.
Not more than one output should be shorted at a time.
§
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈꢈ ꢂ ꢄ ꢄ ꢅ ꢆ ꢇꢉ ꢈꢂ ꢄꢄ
ꢊ ꢋꢌꢍꢎ ꢋꢏꢐ ꢑ ꢐ ꢒꢇꢑ ꢍ ꢎꢒ ꢓ ꢑꢎ ꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
switching characteristics, V
= 9 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
220
100
55
MAX
350
175
100
75
UNIT
ns
t
t
t
t
t
t
Propagation delay time, low- to high-level output
PLH
PHL
TLH
THL
TLH
THL
Propagation delay time, high- to low-level output
ns
R
= 3 kΩ,
See Figure 1
C
C
= 15 pF,
L
L
L
†
Transition time, low- to high-level output
ns
†
‡
‡
Transition time, high- to low-level output
Transition time, low- to high-level output
Transition time, high- to low-level output
45
ns
2.5
3.0
µs
R
= 3 kΩ to 7 kΩ,
= 2500 pF,
L
See Figure 1
µs
†
‡
Measured between 10% and 90% points of output waveform
Measured between 3 V and −3 V points on the output waveform (TIA/EIA-232-E conditions)
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
Input
1.5 V
1.5 V
t
t
PHL
90%
PLH
90%
Pulse
Generator
(see Note A)
V
OH
OL
Output
50%
10%
50%
10%
Output
R
C
L
L
V
(see Note B)
t
t
THL
TLH
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: t = 0.5 µs, PRR ≤ 1 MHz, Z = 50 Ω.
w
O
B.
C includes probe and jig capacitance.
L
Figure 1. Test Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄꢄ ꢅ ꢆꢇ ꢈ ꢈꢂ ꢄꢄ ꢅ ꢆ ꢇꢉ ꢈ ꢂꢄ ꢄ
ꢊꢋ ꢌ ꢍꢎ ꢋ ꢏꢐ ꢑ ꢐ ꢒ ꢇꢑ ꢍꢎ ꢒ ꢓꢑ ꢎꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
†
TYPICAL CHARACTERISTICS
OUPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE TRANSFER CHARACTERISTICS
12
9
20
V
= 12 V, V
= −12 V
CC−
V
= 9 V
= −9 V
CC+
CC+
CC+
V
16
12
CC−
= 25°C
V
= 9 V, V
= −9 V
= −6 V
T
CC−
A
V
OL
(V = 1.9 V)
I
6
8
V
CC+
= 6 V, V
CC−
3
4
0
0
−4
−8
−12
−16
−20
−3
−6
−9
−12
3-kΩ
Load Line
V
OH
(V = 0.8 V)
R
T
A
= 3 kΩ
= 25°C
I
L
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
−16 −12
−8
−4
0
4
8
12
16
V − Input Voltage − V
I
V
O
− Output Voltage − V
Figure 2
Figure 3
SHORT-CIRCUT OUTPUT CURRENT
SLEW RATE
vs
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
12
1000
100
10
V
V
= 9 V
= −9 V
CC+
CC−
9
6
R
= ∞
= 25°C
I
(V = 1.9 V)
I
L
OS(L)
T
A
3
0
V
V
V
= 9 V
CC+
CC−
O
= −9 V
−3
= 0
−6
−9
I
(V = 0.8 V)
I
OS(H)
1
−12
10
100
1000
10000
−100 −75 −50 −25
0
25 50 75 100 125 150
T
A
− Free-Air Temperature − °C
C
− Load Capacitance − pF
L
Figure 4
Figure 5
†
Data for temperatures below 0°C and above 70°C are applicable to SN55188 circuit only.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢄ ꢅ ꢆꢇ ꢈꢈ ꢂ ꢄ ꢄ ꢅ ꢆ ꢇꢉ ꢈꢂ ꢄꢄ
ꢊ ꢋꢌꢍꢎ ꢋꢏꢐ ꢑ ꢐ ꢒꢇꢑ ꢍ ꢎꢒ ꢓ ꢑꢎ ꢆ
SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004
†
THERMAL INFORMATION
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
16
14
12
10
8
6
4
2
R
≥ 3 kΩ (from each output to GND)
L
0
−75 −50 −25
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
Figure 6
†
Data for temperatures below 0°C and above 70°C are applicable to the SN55188 circuit only.
APPLICATION INFORMATION
V
CC+
V
CC−
= 12 V
= −12 V
Output to RTL
−0.7 V to 3.7 V
V
CC+
1/4 SN55188
or SN75188
V
CC+
3 V
5 V
Output
Output to DTL
−0.7 V to 5.7 V
’188
’188
15 V
1/4 SN55188
or SN75188
V
CC−
V
CC−
Output to HNIL
−0.7 V to 10 V
1/4 SN55188
or SN75188
Diodes placed in series with the V
CC+
and V leads protect
CC−
Output to MOS
−10 V to 0 V
the SN55188/SN75188 in the fault condition in which the device
outputs are shorted to 15 V, and the power supplies are at low
voltage and provide low-impedance paths to ground.
1 kΩ
1/4 SN55188
or SN75188
10 kΩ
−12 V
Figure 8. Power-Supply Protection to Meet
Power-Off Fault Conditions of
ANSI TIA/EIA-232-E
Figure 7. Logic Translator Applications
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-86889012A
5962-8688901CA
5962-8688901DA
MC1488N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
N
1
PDIP
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
MC1488NE4
ACTIVE
PDIP
N
14
25
1
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN55188J
SN75188D
ACTIVE
ACTIVE
CDIP
SOIC
J
14
14
TBD
A42 SNPB
N / A for Pkg Type
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75188DE4
SN75188DG4
SN75188DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75188DRE4
SN75188DRG4
SN75188N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75188NE4
SN75188NSR
SN75188NSRE4
SN75188NSRG4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ55188FK
SNJ55188J
SNJ55188W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
SN75188DR
D
14
14
MLA
MLA
6.5
8.2
9.0
2.1
2.5
8
16
16
Q1
Q1
SN75188NSR
NS
330
16
10.5
12
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN75188DR
D
14
14
MLA
MLA
346.0
346.0
346.0
346.0
33.0
33.0
SN75188NSR
NS
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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