5962-01-212-7377 [RENESAS]
Clock Generator, CMOS;
| 型号： | 5962-01-212-7377 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Clock Generator, CMOS |
| 文件： | 总11页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C84A
®
Data Sheet
December 6, 2005
FN2974.3
CMOS Clock Generator Driver
Features
The Intersil 82C84A is a high performance CMOS Clock
Generator-driver which is designed to service the requirements
of both CMOS and NMOS microprocessors such as the
80C86, 80C88, 8086 and the 8088. The chip contains a crystal
controlled oscillator, a divide-by-three counter and complete
“Ready” synchronization and reset logic.
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
Static CMOS circuit design permits operation with an external
frequency source from DC to 25MHz. Crystal controlled
operation to 25MHz is guaranteed with the use of a parallel,
fundamental mode crystal and two small load capacitors.
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
All inputs (except X1 and RES) are TTL compatible over
temperature and voltage ranges.
• Operating Temperature Ranges
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design with
respect to power and/or speed requirements.
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
- M82C84A . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
Pinouts
82C84A (PDIP, CERDIP)
PART
PART
TEMP.
PKG.
TOP VIEW
NUMBER
MARKING RANGE (°C) PACKAGE DWG. #
CSYNC
PCLK
AEN1
1
2
3
4
5
6
7
8
9
18
V
CC
CP82C84A
CP82C84A
0 to +70
0 to +70
18 Ld PDIP
E18.3
17 X1
CP82C84AZ
(See Note)
CP82C84AZ
18 Ld PDIP* E18.3
(Pb-free)
16 X2
IP82C84A
CS82C84A
IP82C84A
-40 to +85 18 Ld PDIP
E18.3
15 ASYNC
RDY1
CS82C84A
CS82C84AZ
0 to +70
0 to +70
20 Ld PLCC
N20.35
N20.35
EFI
READY
RDY2
14
CS82C84AZ
(Note)
20 Ld PLCC
(Pb-free)
13 F/C
CS82C84AZ96 CS82C84AZ
(Note)
0 to +70
20 Ld PLCC
Tape and Reel
(Pb-free)
N20.35
12 OSC
11 RES
10 RESET
AEN2
CLK
GND
IS82C84A
CD82C84A
ID82C84A
IS82C84A
CD82C84A
ID82C84A
-40 to +85 20 Ld PLCC
0 to +70
-40 to +85 18 Ld CERDIP F18.3
N20.35
18 Ld CERDIP F18.3
82C84A (PLCC, CLCC)
TOP VIEW
MD82C84A/B MD82C84A/B -55 to +125 18 Ld CERDIP F18.3
8406801VA
8406801VA
-55 to +125 18 Ld CERDIP F18.3
SMD#
MR82C84A/B MR82C84A/B -55 to +125 20 Pad CLCC J20.A
3
2
1
20 19
84068012A
84068012A
-55 to +125 20 Pad CLCC J20.A
18
17
16
15
14
X2
4
5
6
7
8
RDY1
READY
RDY2
AEN2
NC
SMD#
ASYNC
EFI
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
F/C
NC
9
10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1997, 2002, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
82C84A
Functional Diagram
11
10
12
2
D
RES
Q
RESET
OSC
CK
17
16
X1
X2
XTAL
OSCILLATOR
13
÷ 3
÷ 2
F/C
PCLK
SYNC
SYNC
14
1
EF1
CSYNC
RDY1
4
3
8
5
CLK
AEN1
6
7
RDY2
AEN2
CK
CK
READY
D
Q
D
Q
FF1
FF2
15
ASYNC
CONTROL PIN
F/C
LOGICAL 1
External Clock
Normal
LOGICAL 0
Crystal Drive
Reset
RES
RDY1, RDY2
AEN1, AEN2
ASYNC
Bus Ready
Bus Not Ready
Address Enable
Address Disabled
1 Stage Ready
Synchronization
2 Stage Ready
Synchronization
FN2974.3
2
December 6, 2005
82C84A
Pin Des cription
SYMBOL
NUMBER
TYPE
DESCRIPTION
AEN1,
AEN2
3, 7
I
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready
Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are
useful in system configurations which permit the processor to access two Multi-Master System Busses.
In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW).
RDY1,
RDY2
4, 6
15
I
I
BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device
located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
ASYNC
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of
the READY logic. When ASYNC is low, two stages of READY synchronization are provided. When
ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY
X1, X2
F/C
5
O
I O
I
READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is
cleared after the guaranteed hold time to the processor has been met.
17, 16
13
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times
the desired processor clock frequency, (Note 1).
FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits the
processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated for the
EFI input, (Note 1).
EFI
14
8
I
EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input frequency
appearing on this pin. The input signal is a square wave 3 times the frequency of the desired CLK
output.
CLK
O
PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which directly
connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crystal or EFI
input frequency and a 1/3 duty cycle.
PCLK
OSC
RES
2
O
O
I
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK
and has a 50% duty cycle.
12
11
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to
that of the crystal.
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A provides a
Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper
duration.
RESET
CSYNC
10
1
O
I
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing
characteristics are determined by RES.
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be
synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset.
When CSYNC goes LOW the internal counters are allowed to resume counting. CSYNC needs to be
externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to
ground.
GND
9
Ground
V
18
V
: The +5V power supply pin. A 0.1µF capacitor between V
and GND is recommended for
CC
CC
CC
decoupling.
NOTE:
1. If the crystal inputs are not used X1 must be tied to V
or GND and X2 should be left open.
CC
FN2974.3
December 6, 2005
3
82C84A
Clock Outputs
Functional Des cription
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a
peripheral clock signal whose output frequency is 1/2 that of
CLK. PCLK has a 50% duty cycle.
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
Reset Logic
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The
output of the oscillator is buffered and brought out on OSC
so that other system timing signals can be derived from this
stable, crystal-controlled source.
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to
accommodate two system busses. Each input has a qualifier
(AEN1 and AEN2, respectively). The AEN signals validate
their respective RDY signals. If a Multi-Master system is not
being used the AEN pin should be tied LOW.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER
Frequency
TYPICAL CRYSTAL SPEC
2.4 - 25MHz, Fundamental, “AT” cut
Parallel
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in
normally ready systems do not require synchronization but
must satisfy RDY setup and hold as a matter of proper system
design.
Type of Operation
Unwanted Modes
Load Capacitance
6dB (Minimum)
18 - 32pF
Capacitors C1, C2 are chosen such that their combined
The ASYNC input defines two modes of READY
synchronization operation.
capacitance
C1 x C2
---------------------
CT =
(Including stray capacitance)
C1 + C2
When ASYNC is LOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized to flip-
flop one of the rising edge of CLK (requiring a setup time
tR1VCH) and the synchronized to flip-flop two at the next
falling edge of CLK, after which time the READY output will go
active (HIGH). Negative-going asynchronous READY inputs
will be synchronized directly to flip-flop two at the falling edge
of CLK, after which the READY output will go inactive. This
mode of operation is intended for use by asynchronous
(normally not ready) devices in the system which cannot be
guaranteed by design to meet the required RDY setup timing,
TR1VCL, on each bus cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is
available for synchronous devices that can be guaranteed to
meet the required RDY setup time.
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is
accomplished with two flip-flops. (See Figure 1). The counter
output is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the clock for the ÷ 3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
FN2974.3
4
December 6, 2005
82C84A
EFI
82C84A
CLOCK
SYNCHRONIZE
D
Q
D
CSYNC
Q
EFI
>
>
(TO OTHER 82C84As)
NOTE: If EFI input is used, then crystal input X1 must be tied to V
or GND and X2 should be left open. If the crystal inputs are used,
CC
then EFI should be tied to V
or GND.
CC
FIGURE 1. CSYNC SYNCHRONIZATION
FN2974.3
5
December 6, 2005
82C84A
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance. . . . . . . . . . . . . . . . .
CERDIP Package. . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
PDIP Package* . . . . . . . . . . . . . . . . . .
PLCC Package. . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
80
95
85
85
20
28
N/A
CC
N/A
Operating Conditions
o
o
Storage Temperature Range. . . . . . . . . . . . . . . . . -65 C to +150 C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+175 C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300 C
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
o
o
o
o
C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
(PLCC - Lead Tips Only)
o
o
I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
o
o
M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications V = +5.0V ±10%,
CC
o
o
T
T
T
= 0 C to +70 C (C82C84A),
= -40 C to +85 C (I82C84A),
= -55 C to +125 C (M82C84A)
A
A
A
o
o
o
o
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
Logical One Input Voltage
2.0
2.2
-
V
V
C82C84A, I82C84
M82C84A, Notes 1, 2
IH
V
Logical Zero Input Voltage
Reset Input High Voltage
Reset Input Low Voltage
-
0.8
V
V
V
-
Notes 1, 2, 3
IL
V
V
-0.8
CC
-
0.5
-
IHR
V
-
ILR
VT+ - VT- Reset Input Hysteresis
0.2 V
CC
-0.4
V
Logical One Output Current
Logical Zero Output Voltage
Input Leakage Current
V
-
V
I
I
= -4.0mA for CLK Output
= -2.5mA for All Others
OH
CC
OH
OH
V
-
0.4
1.0
40
V
I
I
= +4.0mA for CLK Output
= +2.5mA for All Others
OL
OL
OL
II
-1.0
-
µA
mA
V
= V
or GND except ASYNC,
CC
IN
X1: (Note 4)
I
Operating Power Supply Current
Crystal Frequency = 25MHz
Outputs Open, Note 5
CCOP
NOTES:
1. F/C is a strap option and should be held either ≤ 0.8V or ≥ 2.2V. Does not apply to X1 or X2 pins.
2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is
guaranteed.
3. CSYNC pin is tested with V ≤ 0.8V.
IL
4. ASYNC pin includes an internal 17.5kΩ nominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage current = 300µA
nominal, X1 - crystal feedback input.
5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz.
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
Input Capacitance
TYPICAL
UNITS
pF
TEST CONDITIONS
C
10
15
FREQ = 1MHz, all measurements are
referenced to device GND
IN
C
Output Capacitance
pF
OUT
FN2974.3
December 6, 2005
6
82C84A
AC Electrical Specifications
V
= +5V± 10%,
CC
= 0 C to +70 C (C82C84A),
o
o
T
T
T
A
A
A
o
o
= -40 C to +85 C (I82C84A),
o
o
= -55 C to +125 C (M82C84A)
LIMITS
(NOTE 1)
TEST
SYMBOL
PARAMETER
MIN
MAX
UNITS
CONDITIONS
TIMING REQUIREMENTS
(1) TEHEL
(2) TELEH
(3) TELEL
External Frequency HIGH Time
External Frequency LOW Time
EFI Period
13
13
36
2.4
35
35
35
0
-
-
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
90%-90% V
IN
IN
10%-10% V
-
XTAL Frequency
25
-
Note 2
(4) TR2VCL
(5) TR1VCH
(6) TR1VCL
(7) TCLR1X
(8) TAYVCL
(9) TCLAYX
(10) TA1VR1V
(11) TCLA1X
(12) TYHEH
(13) TEHYL
(14) TYHYL
(15) TI1HCL
(16) TCLI1H
TIMING RESPONSES
(17) TCLCL
(18) TCHCL
(19) TCLCH
RDY1, RDY2 Active Setup to CLK
RDY1, RDY2 Active Setup to CLK
RDY1, RDY2 Inactive Setup to CLK
RDY1, RDY2 Hold to CLK
ASYNC Setup to CLK
ASYNC = HIGH
ASYNC = LOW
-
-
-
50
0
-
ASYNC Hold to CLK
-
AEN1, AEN2 Setup to RDY1, RDY2
AEN1, AEN2 Hold to CLK
CSYNC Setup to EFI
15
0
-
-
20
20
-
CSYNC Hold to EFI
-
CSYNC Width
2 TELEL
65
-
RES Setup to CLK
-
Note 3
Note 3
RES Hold to CLK
20
-
CLK Cycle Period
CLK HIGH Time
125
(1/3 TCLCL) +2.0
(2/3 TCLCL) -15.0
-
-
-
ns
ns
ns
ns
Note 6
Note 6
CLK LOW Time
-
Note 6
(20) TCH1CH2
(21) TCL2CL1
CLK Rise or Fall Time
10
1.0V to 3.0V
(22) TPHPL
(23) TPLPH
(24) TRYLCL
(25) TRYHCH
(26) TCLIL
(27) TCLPH
(28) TCLPL
(29) TOLCH
(30) TOLCL
NOTES:
PCLK HIGH Time
TCLCL-20
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6
Note 6
Note 4
Note 5
PCLK LOW Time
TCLCL-20
-
Ready Inactive to CLK (See Note 4)
Ready Active to CLK (See Note 3)
CLK to Reset Delay
-8
-
(2/3 TCLCL) -15.0
-
-
-
40
22
22
22
35
CLK to PCLK HIGH Delay
CLK to PCLK LOW Delay
OSC to CLK HIGH Delay
OSC to CLK LOW Delay
-
-5
2
1. Tested as follows: f = 2.4MHz, V = 2.6V, V = 0.4V, C = 50pF, V
IH IL OH
≥ 1.5V, V ≤ 1.5V, unless otherwise specified. RES and F/C must switch
OL
L
between 0.4V and V
CC
-0.4V. Input rise and fall times driven at 1ns/V. V ≤ V (max) - 0.4V for CSYNC pin. V = 4.5V and 5.5V.
IL IL CC
2. Tested using EFI or X1 input pin.
3. Setup and hold necessary only to guarantee recognition at next clock.
4. Applies only to T2 states.
5. Applies only to T3 TW states.
6. Tested with EFI input frequency = 4.2MHz.
FN2974.3
7
December 6, 2005
82C84A
Timing Waveforms
(2)
(1)
tELEH
tEHEL
(3)
tELEL
NAME
EFI
I/O
I
OSC
O
O
O
(19)
tOLCH
tCL2CL1
(21)
tCHCL
(18)
tCLCH
(29)
(17) tCLCL
CLK
tCH1CH2
(20)
tCLPL
(28)
tCLPH
(27)
PCLK
(13)
(30)
tOLCL
(22)
tEHYL
tPLPH
(23)
tPHPL
tYHEH
(12)
(16)
tCLI1H
(15)
tI1HCL
CSYNC
I
(14)
tYHYL
(26)
RES
I
tCLIL
RESET
O
NOTE: All timing measurements are made at 1.5V, unless otherwise noted.
FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS
CLK
(7)
tR1VCH
(5)
tCLR1X
tR1VCL
(6)
RDY1, 2
(10)
tA1VR1V
tCLR1X
tCLA1X
(7)
AEN1, 2
(11)
tAYVCL
(8)
ASYNC
(9)
tCLAYX
READY
(25)
tRYHCH
(24) tRYLCL
FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
CLK
(7)
(4)
tCLR1X
tR1VCL
(6)
tR1VCL
RDY 1, 2
(7)
(10)
tA1VRIV
tCLR1X
tCLA1X
AEN1, 2
ASYNC
(11)
tAYVCL
(8)
tCLAYX
(9)
READY
(24)
tRYLCL
(25)
tRYHCH
FIGURE 4. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES)
FN2974.3
December 6, 2005
8
82C84A
Tes t Load Circuits
2.25V
R = 740Ω FOR ALL OUTPUTS
EXCEPT CLK
463Ω FOR CLK OUTPUT
OUTPUT FROM
DEVICE UNDER TEST
C
L
(SEE NOTE 3)
NOTES:
1. C =100pF for CLK output.
L
2. C = 50pF for all outputs except CLK.
L
3. C = Includes probe and jig capacitance.
L
FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 1)
PULSE
GENERATOR
CLK
CLK
X1
EF1
C1
V
CC
X2
C2
F/C
F/C
CSYNC
CSYNC
FIGURE 6. TCHCL, TCLCH LOAD CIRCUITS
V
CC
LOAD
LOAD
PULSE
AEN1
CLK
CLK
EF1
F/C
(SEE NOTE 1)
(SEE NOTE 1)
GENERATOR
X1
V
CC
C1
C2
LOAD
24MHz
PULSE
READY
OSC
(SEE NOTE 2)
X2
AEN1
RDY2
TRIGGER
PULSE
GENERATOR
LOAD
(SEE NOTE 2)
READY
AEN2
CSYNC
GENERATOR
TRIGGER
RDY2
F/C
AEN2
CSYNC
FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS
AC Testing Input, Output Waveform
INPUT
OUTPUT
V
+ 0.4V
V
IH
OH
1.5V
1.5V
V
- 0.4V
V
OL
IL
NOTE: Input test signals must switch between V (maximum) -0.4V and V (minimum) +0.4V. RES and F/C must switch between 0.4V
IL IH
and V
-0.4V. Input rise and fall times driven at 1ns/V. V ≤ V (max) -0.4V for CSYNC pin. V
IL IL
-4.5V and 5.5V.
CC
CC
FN2974.3
9
December 6, 2005
82C84A
Burn-In Circuits
MD82C84A CERDIP
V
CC
C1
R1
1
18
17
16
15
14
13
12
11
10
F9
R1
R2
R2
R2
V
CC
2
3
4
5
6
7
8
9
F0
GND
F6
R1
R1
OPEN
F10
R3
F5
R2
R2
R1
R1
V
CC
F1
GND
F7
R1
R1
F11
R2
R2
V
CC
F8
CC
R2
R2
GND
F12
R1
V
R2
R2
GND
V
CC
GND
MR82C84A CLCC
V
CC
C1
3
2
1
20 19
R4
R4
18
F5
/ 2
4
OPEN
R4
17
16
V
5
6
7
8
F10
CC
R4
R4
R4
R4
F7
F8
F1
15
14
F11
OPEN
OPEN
9
10 11 12 13
NOTES:
V
V
V
= 5.5V ±0.5V, GND = 0V.
= 4.5V ±10%.
= -0.2 to 0.4V.
CC
IH
IL
R1 = 47kΩ, ±5%.
R2 = 10kΩ, ±5%.
R3 = 2.2kΩ, ±5%.
R4 = 1.2kΩ, ±5%.
C1 = 0.01µF (minimum).
F0 = 100kHz ±10%.
F1 = F0/2, F2 = F1/2, . . . F12 = F11/2.
FN2974.3
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December 6, 2005
82C84A
Die Characteris tics
DIE DIMENSIONS:
66.1 x 70.5 x 19 ± 1mils
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ± 1kÅ
METALLIZATION:
Type: Si - AI
Thickness: 11kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
5
2
1.42 x 10 A/cm
Metallization Mas k Layout
82C84A
AEN1
PCLK
CSYNC
V
X1
CC
X2
RDY1
ASYNC
READY
RDY2
EFI
AEN2
CLK
F/C
GND
RESET
RES
OSC
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN2974.3
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December 6, 2005
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