54ACT534DM [TI]

ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP16, CERAMIC, DIP-16;
54ACT534DM
型号: 54ACT534DM
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

ACT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP16, CERAMIC, DIP-16

驱动 CD 输出元件 逻辑集成电路
文件: 总9页 (文件大小:189K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
July 1998  
54ACT534  
Octal D Flip-Flop with TRI-STATE® Outputs  
n Edge-triggered D-type inputs  
n Buffered positive edge-triggered clock  
n TRI-STATE outputs for bus-oriented applications  
n Outputs source/sink 24 mA  
n ’ACT534 has TTL-compatible inputs  
n Inverted output version of ’ACT374  
n Standard Microcircuit Drawing (SMD) 5962-8965801  
General Description  
The ’ACT534 is  
a high-speed, low-power octal D-type  
flip-flop featuring separate D-type inputs for each flip-flop  
and TRI-STATE outputs for bus-oriented applications. A buff-  
ered Clock (CP) and Output Enable (OE) are common to all  
flip-flops. The ’ACT534 is the same as the ’ACT374 except  
that the outputs are inverted.  
Features  
n ICC and IOZ reduced by 50%  
Logic Symbols  
IEEE/IEC  
DS100292-1  
DS100292-2  
Pin Names  
D0–D7  
Description  
Data Inputs  
CP  
Clock Pulse Input  
OE  
TRI-STATE Output Enable Input  
Complementary TRI-STATE Outputs  
O0–O7  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100292  
www.national.com  
Connection Diagrams  
Pin Assignment  
for DIP and Flatpak  
Pin Assignment  
for LCC  
DS100292-4  
DS100292-3  
Functional Description  
The ’ACT534 consists of eight edge-triggered flip-flops with  
individual D-type inputs and TRI-STATE complementary out-  
puts. The buffered clock and buffered Output Enable are  
common to all flip-flops. The eight flip-flops will store the  
state of their individual D inputs that meet the setup and hold  
times requirements on the LOW-to-HIGH Clock (CP) transi-  
tion. With the Output Enable (OE) LOW, the contents of the  
eight flip-flops are available at the outputs. When the OE is  
HIGH, the outputs go to the high impedance state. Operation  
of the OE input does not affect the state of the flip-flops.  
Logic Diagram  
DS100292-5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
Function Table  
Inputs  
Output  
CP  
N
N
OE  
L
D
H
L
O
L
L
H
L
L
X
X
O0  
Z
X
H
=
=
=
H
L
X
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
N =  
LOW-to-HIGH Clock Transition  
High Impedance  
=
Z
=
O
Value stored from previous clock cycle  
0
www.national.com  
2
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales Office/  
Distributors for availability and specifications.  
Junction Temperature (TJ)  
CDIP  
175˚C  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
)
−0.5V to +7.0V  
DC Input Diode Current (IIK  
)
Supply Voltage (VCC  
)
=
VI −0.5V  
−20 mA  
+20 mA  
’ACT  
4.5V to 5.5V  
0V to VCC  
0V to VCC  
=
VI VCC + 0.5V  
Input Voltage (VI)  
DC Input Voltage (VI)  
−0.5V to VCC + 0.5V  
Output Voltage (VO  
)
DC Output Diode Current (IOK  
)
Operating Temperature (TA)  
54ACT  
=
VO −0.5V  
−20 mA  
+20 mA  
−55˚C to +125˚C  
=
VO VCC + 0.5V  
Minimum Input Edge Rate (V/t)  
’ACT Devices  
DC Output Voltage (VO  
DC Output Source  
)
−0.5V to VCC + 0.5V  
VIN from 0.8V to 2.0V  
±
±
or Sink Current (IO  
)
50 mA  
@
VCC 4.5V, 5.5V  
125 mV/ns  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
Note 1: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, without  
exception, to ensure that the system design is reliable over its power supply,  
temperature, and output/input loading variables. National does not recom-  
)
50 mA  
Storage Temperature (TSTG  
)
−65˚C to +150˚C  
mend operation of FACT circuits outside databook specifications.  
DC Characteristics for ’ACT Family Devices  
54ACT  
=
Symbol  
Parameter  
VCC  
(V)  
TA  
Units  
Conditions  
−55˚C to +125˚C  
Guaranteed Limits  
=
VIH  
VIL  
Minimum High Level  
Input Voltage  
4.5  
5.5  
4.5  
5.5  
4.5  
5.5  
2.0  
2.0  
0.8  
0.8  
4.4  
5.4  
V
V
V
VOUT 0.1V  
or VCC − 0.1V  
=
Maximum Low Level  
Input Voltage  
VOUT 0.1V  
or VCC − 0.1V  
=
VOH  
Minimum High Level  
Output Voltage  
IOUT −50 µA  
(Note 2)  
=
VIN VIL or VIH  
4.5  
5.5  
4.5  
5.5  
3.70  
4.70  
0.1  
V
V
IOH = −24 mA  
IOH = −24 mA  
=
VOL  
Maximum Low Level  
Output Voltage  
IOUT 50 µA  
0.1  
(Note 2)  
=
VIN VIL or VIH  
4.5  
5.5  
5.5  
0.50  
0.50  
V
IOL = 24 mA  
IOL = 24 mA  
=
±
IIN  
Maximum Input Leakage  
Current  
1.0  
µA  
µA  
VI VCC, GND  
=
±
IOZ  
Maximum TRI-STATE  
Current  
5.5  
5.0  
VI VIL, VIH  
=
VO VCC, GND  
=
VI VCC − 2.1V  
ICCT  
IOLD  
IOHD  
ICC  
Maximum ICC/Input  
Minimum Dynamic  
Output Current (Note 3)  
Maximum Quiescent  
Supply Current  
5.5  
5.5  
5.5  
5.5  
1.6  
mA  
mA  
mA  
µA  
=
VOLD 1.65V Max  
50  
=
VOHD 3.85V Min  
−50  
80.0  
=
VIN VCC  
or GND  
Note 2: All outputs loaded; thresholds on input associated with output under test.  
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.  
@ @  
I for 54ACT 25˚C is identical to 74ACT 25˚C.  
CC  
Note 4:  
3
www.national.com  
AC Electrical Characteristics  
54ACT  
=
VCC  
(V)  
TA −55˚C  
Fig.  
No.  
Symbol  
Parameter  
to +125˚C  
Units  
=
(Note 5)  
CL 50 pF  
Min  
Max  
fmax  
Maximum Clock  
5.0  
5.0  
5.0  
85  
MHz  
ns  
Frequency  
tPLH  
Propagation Delay  
CP to Qn  
1.5  
1.5  
14.0  
13.0  
tPHL  
Propagation Delay  
CP to Qn  
ns  
tPZH  
tPZL  
tPHZ  
tPLZ  
Output Enable Time  
Output Enable Time  
Output Disable Time  
Output Disable Time  
5.0  
5.0  
5.0  
5.0  
1.5  
1.5  
1.5  
1.5  
14.0  
13.0  
14.5  
11.5  
ns  
ns  
ns  
ns  
±
Note 5: Voltage Range 5.0 is 5.0V 0.5V  
AC Operating Requirements  
54ACT  
=
VCC  
(V)  
TA −55˚C  
Fig.  
No.  
Symbol  
Parameter  
to +125˚C  
Units  
=
CL 50 pF  
(Note 6)  
Guaranteed Minimum  
ts  
Setup Time, HIGH or LOW  
Dn to CP  
5.0  
5.0  
5.0  
5.0  
ns  
ns  
ns  
th  
Hold Time, HIGH or LOW  
Dn to CP  
3.0  
5.0  
tw  
CP Pulse Width  
HIGH or LOW  
±
Note 6: Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Power Dissipation  
Capacitance  
Typ  
4.5  
Units  
Conditions  
=
VCC OPEN  
CIN  
pF  
pF  
=
VCC 5.0V  
CPD  
40.0  
www.national.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
20 Terminal Ceramic Leadless Chip Carrier (L)  
NS Package Number E20A  
16 Lead Ceramic Dual-In-Line Package (D)  
NS Package Number J16A  
5
www.national.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16 Lead Ceramic Flatpak (F)  
NS Package Number W16A  
LIFE SUPPORT POLICY  
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-  
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-  
CONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or sys-  
tems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, and whose fail-  
ure to perform when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
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Products > Military/Aerospace > Logic > FACT ACT > 54ACT534  
Product Folder  
54ACT534  
Octal D Flip-Flop with TRI-STATE Outputs  
Contents  
l
l
l
l
General Description  
Features  
Datasheet  
Package Availability, Models, Samples  
& Pricing  
General Description  
The 'ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type  
inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered  
Clock (CP) and Output Enable (OE#) are common to all flip-flops. The 'ACT534 is the  
same as the 'ACT374 except that the outputs are inverted.  
Features  
l
I
and I reduced by 50%  
CC OZ  
l
l
l
l
l
l
l
Edge-triggered D-type inputs  
Buffered positive edge-triggered clock  
TRI-STATE outputs for bus-oriented applications  
Outputs source/sink 24 mA  
'ACT534 has TTL-compatible inputs  
Inverted output version of 'ACT374  
Standard Microcircuit Drawing (SMD) 5962-8965801  
Datasheet  
Size  
(in Kbytes)  
Title  
Date  
Receive via Email  
Download  
View Online  
54ACT534 Octal D Flip-Flop with TRI-STATE Outputs 149 Kbytes 6-Aug-98 View Online Download Receive via Email  
Please use Adobe Acrobat to view PDF file(s).  
If you have trouble printing, see Printing Problems.  
Package Availability, Models, Samples & Pricing  
Samples  
Package  
Models  
Budgetary Pricing  
Quantity $US each  
Std  
Pack  
Size  
&
Package  
Marking  
Part Number  
Status  
Electronic  
Orders  
Type # pins  
SPICE IBIS  
[logo]¢Z¢S¢4¢A  
54ACT534  
LMQB /Q¢M$E  
5962-  
tube  
50  
5962-89658012A LCC  
20 Full production N/A N/A  
.
50+  
$8.0000 of  
89658012A  
tube  
[logo]¢Z¢S¢4¢A$E  
5962-8965801RA Cerdip 20 Full production N/A N/A  
.
.
50+  
50+  
$6.0000 of 54ACT534DMQB /Q¢M  
20  
5962-8965801RA  
[logo]¢Z¢S¢4¢A$E  
54ACT534FMQB  
Q¢M 5962-  
tube  
$9.0000 of  
19  
5962-8965801SA Cerpack 20 Full production N/A N/A  
8965801SA  
[Information as of 1-Sep-2000]  
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