54ACT534DMX [NSC]
Octal D Flip-Flop with TRI-STATE Outputs; 八路D触发器具有三态输出
| 型号： | 54ACT534DMX |
| 厂家： | 
National Semiconductor |
| 描述： | Octal D Flip-Flop with TRI-STATE Outputs |
| 文件： | 总8页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1993
54ACT/74ACT534
Octal D Flip-Flop with TRI-STATE Outputs
É
General Description
Features
Y
CC
I
and I
reduced by 50%
OZ
The ’ACT534 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to all
flip-flops. The ’ACT534 is the same as the ’ACT374 except
that the outputs are inverted.
Y
Y
Y
Y
Y
Y
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
Outputs source/sink 24 mA
’ACT534 has TTL-compatible inputs
Inverted output version of ’ACT374
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
TL/F/9965–1
TL/F/9965–2
TL/F/9965–3
Pin Assignment
for LCC
Pin Names
Description
D –D
0
Data Inputs
7
CP
OE
Clock Pulse Input
TRI-STATE Output Enable Input
Complementary TRI-STATE Outputs
O –O
0
7
TL/F/9965–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9965
RRD-B30M75/Printed in U. S. A.
Functional Description
The ’ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE complementary
outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
TL/F/9965–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Function Table
Inputs
OE
Output
O
CP
D
L
L
L
L
L
H
L
L
H
L
X
X
O
0
X
H
Z
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
e
LOW-to-HIGH Clock Transition
High Impedance
L
e
Z
e
O
0
Value stored from previous clock cycle
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’ACT
)
CC
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
Input Voltage (V )
I
0V to V
0V to V
CC
DC Input Diode Current (I
)
IK
Output Voltage (V
)
O
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Operating Temperature (T )
A
e
V
CC
0.5V
b
b
a
40 C to 85 C
74ACT
54ACT
§
55 C to 125 C
§
§
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
a
§
DC Output Diode Current (I
)
OK
Minimum Input Edge Rate (DV/Dt)
’ACT Devices
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
e
V
CC
0.5V
V
V
from 0.8V to 2.0V
@
IN
a
DC Output Voltage (V
DC Output Source
)
O
0.5V
50 mA
50 mA
CC
4.5V, 5.5V
125 mV/ns
CC
g
g
or Sink Current (I
)
O
DC V
or Ground Current
CC
per Output Pin (I or I
CC
)
GND
)
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
Junction Temperature (T )
J
CDIP
PDIP
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
74ACT
54ACT
74ACT
e
25 C
e
e
T
A
V
T
T
CC
A
A
Symbol
Parameter
Units
Conditions
a
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
2.0
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
0.1V
IL
b
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
4.5 4.49
5.5 5.49
4.4
5.4
4.4
5.4
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
b
b
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
24 mA
V
V
I
OH
24 mA
e
e
V
OL
Maximum Low Level
Output Voltage
4.5 0.001
5.5 0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V or V
IL IH
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
24 mA
V
I
OL
24 mA
e
e
g
g
g
g
g
I
I
Maximum Input Leakage Current 5.5
0.1
1.0
5.0
1.0
2.5
mA
mA
V
V
, GND
CC
IN
I
Maximum TRI-STATE
V
V
V , V
IL IH
É
OZ
I
g
5.5
0.25
e
Current
V
, GND
CC
O
e
b
2.1V
I
Maximum
/Input
V
I
V
CC
CCT
5.5
0.6
1.6
1.5
mA
I
CC
*All outputs loaded; thresholds on input associated with output under test.
3
DC Characteristics for ’ACT Family Devices (Continued)
74ACT
54ACT
74ACT
e
25 C
e
e
T
A
V
T
T
CC
A
A
Symbol
Parameter
Units
Conditions
a
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
§
Typ
Guaranteed Limits
e
²
I
I
I
Minimum Dynamic
5.5
5.5
50
75
mA
mA
V
V
V
1.65V Max
OLD
OHD
CC
OLD
Output Current
b
b
e
3.85V Min
OHD
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
4.0
80.0
40.0
mA
or GND
²
Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25 C is identical to 74ACT 25 C.
§ §
Note: I
CC
AC Electrical Characteristics
74ACT
e a
54ACT
e b
74ACT
e b
40 C
T
55 C
T
A
§
to 125 C
§
A
V *
CC
(V)
T
25 C
§
A
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
50 pF
L
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
t
Maximum Clock
Frequency
max
PLH
PHL
5.0
5.0
5.0
100
6.5
6.0
85
120
MHz
ns
Propagation Delay
2.5
2.0
11.5
10.5
1.5
1.5
14.0
13.0
2.0
2.0
12.5
12.0
CP to Q
n
Propagation Delay
CP to Q
ns
n
t
t
t
t
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.5
2.0
1.5
1.5
6.5
6.0
7.0
5.5
12.0
11.0
12.5
10.5
1.5
1.5
1.5
1.5
14.0
13.0
14.5
11.5
2.0
2.0
1.0
1.0
12.5
11.5
13.5
10.5
ns
ns
ns
ns
PZH
PZL
PHZ
PLZ
g
*Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
74ACT
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V *
CC
(V)
T
25 C
§
50 pF
a
e
a
Symbol
Parameter
to 85 C
Units
§
50 pF
§
e
C
L
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
Setup Time, HIGH or LOW
s
5.0
5.0
5.0
1.0
3.5
5.0
4.0
ns
ns
ns
D
n
to CP
Hold Time, HIGH or LOW
to CP
h
w
b
1.0
1.0
3.5
3.0
5.0
1.5
3.5
D
n
CP Pulse Width
HIGH or LOW
2.0
g
*Voltage Range 5.0 is 5.0V 0.5V
4
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
e
C
C
Input Capacitance
4.5
pF
V
V
OPEN
5.0V
IN
CC
Power Dissipation
Capacitance
PD
CC
40.0
pF
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT 534
P
C
QR
Temperature Range Family
e
Special Variations
e
e
74ACT
54ACT
Commercial TTL-Compatible
Military TTL-Compatible
X
QR
Devices shipped in 13 reels
×
Commercial grade device with
burn-in
e
Device Type
e
QB
Military grade device with
environmental and burn-in
processing shipped in tubes
Package Code
e
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline (SOIC)
Temperature Range
e
e
b a
C
M
Commercial ( 40 C to 85 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
S
Physical Dimensions inches (millimeters)
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
16 Lead Small Outline Integrated Circuit (S)
NS Package Number M16A
6
Physical Dimensions inches (millimeters) (Continued)
16 Lead Plastic Dual-In-Line Package (P)
NS Package Number N16E
7
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
Tel: 1(800) 272-9959
TWX: (910) 339-9240
National Semiconductor
GmbH
Livry-Gargan-Str. 10
D-82256 Furstenfeldbruck
Germany
Tel: (81-41) 35-0
Telex: 527649
Fax: (81-41) 35-1
National Semiconductor National Semiconductor
National Semiconductores
Do Brazil Ltda.
Rue Deputado Lacorda Franco
120-3A
Sao Paulo-SP
Brazil 05418-000
Tel: (55-11) 212-5066
Telex: 391-1131931 NSBR BR
Fax: (55-11) 212-1181
National Semiconductor
(Australia) Pty, Ltd.
Building 16
Business Park Drive
Monash Business Park
Nottinghill, Melbourne
Victoria 3168 Australia
Tel: (3) 558-9999
Japan Ltd.
Hong Kong Ltd.
Sumitomo Chemical
Engineering Center
Bldg. 7F
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
1-7-1, Nakase, Mihama-Ku Hong Kong
Chiba-City,
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Ciba Prefecture 261
Tel: (043) 299-2300
Fax: (043) 299-2500
Fax: (3) 558-9998
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
54ACT534FMQB
Bus Driver, ACT Series, 1-Func, 8-Bit, Inverted Output, CMOS, CDFP20, CERAMIC, FP-20
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明