M02040-15EVM [TE]
3.3 5V Limiting Amplifier for Applications to 2.125 Gbps;
| 型号： | M02040-15EVM |
| 厂家： | 
TE CONNECTIVITY |
| 描述： | 3.3 5V Limiting Amplifier for Applications to 2.125 Gbps |
| 文件： | 总31页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Features
Applications
• Operates with a 3.3V or 5V supply
• 2 mV typical input sensitivity at 1.25 Gbps
• PECL outputs
• 1.0625 and 2.125 Gbps Fibre Channel
• 1.25 Gbps Ethernet
• 1.25 Gbps SDH/SONET
• Average Receive power monitor output (RSSIAVG
)
• Peak-to-peak Receive power monitor output (RSSIPP
• On-chip DC offset cancellation circuit
)
• Offset cancellation circuit can be disabled for Burst mode applications
• Low power (170 mW at 3.3V)
• Output Jam function
• 16-pin 3x3 mm QFN package
The M02040-15 is an integrated high-gain limiting amplifier. Featuring PECL outputs, the M02040-15 is useable in
applications to 2.125 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02040-15 can
operate with a 3.3V or 5V supply.
DC_Servo supports applications requiring instantaneous output response.
The M02040-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-
nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
Other available solutions: M02050-15 3.3/5V Limiting Amplifier for Applications to 2.5 Gbps (PECL outputs)
M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
1.25 Gbps and 4.25 Gbps SFP reference designs are available from your MACOM representative.
Typical Applications Diagram
DC_Servo Control
12.1 kΩ
optional
DC_Servo
Jam
I
REF
Biasing
+3.3 V
V
TT
AC-Coupled
to TIA
PECLP
PECLN
DINP
Clock Data
Recovery
Unit
Limiting
Amplifier
M02016
Photodiode
DINN
MON
Offset cancel
Level
Detect
RSSI
PP
AC or DC Coupled
(as described in
Applications Information)
Comparator
RxAVG
IN
Level
Shift
Threshold
Setting
Circuit
Regulator
RSSI
AVG
LOS
R
EXT
ST
V
V
SET
CC3 CC
R
ST
1
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Ordering Information
Part Number
Package
Operating Temperature
M02040-15
M02040-15 in QFN16 package
Evaluation board with M02040-15
–40 °C to 85 °C
–40 °C to 85 °C
M02040-15EVM
Revision History
Revision
Level
Date
Description
V4
Release
Release
Release
May 2015
December 2005
August 2005
Updated logos and page layout. No content changes.
H (V3)
G (V2)
Clarify comments on the use of the DC_Servo pin in the applications information.
Correct Jam connection in block diagram and typical applications figures. Correct I
(reference current generation).
figure
REF
F (V1)
Release
June 2005
In the DC specifications, update R DIFF and RSSIavg; added note 1; moved RSSIavg from ac
IN
specifications. In the ac specifications update V
, V , DJ and tr/tf; add specifications for
IN(MIN) LOS
LOS assert and deassert. Updated R values and the typical LOS curve (Figure 4-3 -
ST
Figure 4-5). Added typical hysteresis curve (Figure 4-6).
E
D
Preliminary
Preliminary
March 2005
Update the DC specification V . Update the ac specifications V
, v , T
, and
LOS_ON
OH
IN(MIN)
n
T
. Corrected the EVM ordering number.
LOS_OFF
December 2004
Update the DC specifications R DIFF and V . Update R values, update RSSI information.
IN IH ST
Remove peaking circuit applications information as this is not necessary for the -15 revision.
2
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Typical Eye Diagram
Pin Configuration
16
13
GND
VCC
RxAvgIN
1
4
12
GND
Center Pad
Connect to GND
PECLN
PECLP
DINN
DINP
9
8
5
10 mVPP differential input
1.25 Gbps
160 mV/div
140 ps/div
3
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
1.0 Product Specification
1.1
Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged. Reli-
able operation at these extremes for any length of time is not implied.
NOTE:
The package bottom should be adequately grounded to ensure correct thermal performance,
and it is recommended that vias are inserted through to a lower ground plane.
Table 1-1.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
V
Power supply voltage (V -GND)
-0.5 to +5.75
-65 to +150
V
°C
V
CC
CC
T
Storage temperature
STG
PECLP, PECLN
I(PECLP), I(PECLN)
|DINP - DINN|
PECL Output pins voltage
V
- 2 to V + 0.4
CC
CC
PECL Output pins maximum continuous current (delivered to load)
Data input pins differential voltage
30
mA
V
0.80
DINP, DINN
Data input pins voltage meeting |DINP - DINN| requirement
Signal detect threshold setting pin voltage
Output enable pin voltage
GND to V
GND to V
+ 0.4
+ 0.4
V
CC3
CC3
ST
V
SET
JAM
LOS
GND to V + 0.4
V
CC
Status Output pins voltage
GND to V + 0.4
V
CC
DC_Servo
DC_Servo disable input pin voltage
Current into Reference input
Current into RSSIavg input
GND to V + 0.4
V
CC
I
+0 to -120
+0 to -3
µA
mA
V
REF
I(RSSI
)
AVG
RSSI
RSSI pin voltage
GND to V
+ 0.4
CC3
PP
PP
I(LOS)
Current into Loss of Signal pin
+3000 to -100
µA
4
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
1.2
Recommended Operating Conditions
Table 1-2.
Recommended Operating Conditions
Parameter
Rating
Units
Power supply: (V -GND) (apply no potential to V ) or
+5V ± 7.5% or +3.3V
± 7.5%
V
CC
CC3
(V -GND) (connect V to same potential as V )
CC3
CC3
CC
Junction temperature
-40 to +110
-40 to +85
°C
°C
Operating ambient
1.3
DC Characteristics
V
CC = +3.3V 7.5% or +5V 7.5%, TA = -40°C to +85°C, unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-3.
DC Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
I
Supply Current
Outputs terminated into 50 Ω to V
–
52
61
mA
CC
CC
(includes PECL load)
(1)
(1)
V
PECL Output Low Voltage
(PECLP, PECLN)
Single ended; 50 Ω load to V -2V
V
-1.81
V
-1.71
V
V
-1.62
V
V
OUTLpecl
CC
CC
CC
CC
CC
V
PECL Output High Voltage
(PECLP, PECLN)
Single ended; 50 Ω load to V -2V
V
-1.025
90
V -0.952
CC
-0.88
OUTHpecl
CC
CC
R DIFF
Differential Input Resistance
LOS Output High Voltage
LOS Output Low Voltage
Measured between DINP and DINN
110
130
Ω
V
IN
V
External 4.7-10 kΩ pull up to V
2.75
0
V
–
OH_CMOS
CC
CC
V
External 4.7-10 kΩ pull up to V
–
–
0.4
V
OL_CMOS
CC
V
Logic Input High Voltage
JAM, DC_Servo
2.7
V
V
IH
CC
V
Logic Input Low Voltage
JAM, DC_Servo
–
5
–
–
0.8
V
IL
RSSIavg
Average received signal strength 15% accuracy
indicator range
2000
μA
Notes:
1. Limits apply between 0°C to +85°C. Below 0 °C the minimum decreases by up to 40 mV.
5
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
1.4
AC Characteristics
V
CC = +3.3V 7.5% or +5V 7.5%, TA = -40°C to +85°C, input bit rate = 1.25 Gbps 223-1 PRBS unless
otherwise noted. Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-4.
AC Characteristics
Parameter
Symbol
Conditions
Min
–
Typ
2
Max
2.75
5
Units
mV
-12
V
Differential Input Sensitivity
1.25 Gbps, BER < 10
IN(MIN)
-12
2.125 Gbps, BER < 10
–
3.5
–
mV
-12
V
Input Overload
BER < 10 , differential input 1.25 Gbps
1200
600
–
–
mV
I(MAX)
-12
BER < 10 , single-ended input, 1.25 Gbps
–
–
mV
v
RMS Input Referred Noise
140
–
–
μV
n
RMS
RSSIpp
Peak-to-peak received signal strength
indicator range
4
100
mV
kHz
ps
BW
Small-Signal –3dB Low Frequency Excluding AC coupling capacitors
Cutoff
–
–
25
14
–
LF
DJ
RJ
Deterministic Jitter
(includes DCD)
K28.5 pattern at 1.25 Gbps, 10 mV input
60
PP
Random Jitter
10 mV input
–
–
5
ps
RMS
PP
t / t
Data Output Rise and Fall Times
20% to 80%; outputs terminated into 50 Ω;
145
180
ps
r
f
10 mV input
PP
V
LOS Programmable Range
Differential inputs
5
2
–
55
5.5
–
mV
dB
LOS
HYS
Signal Detect Hysteresis
electrical; across LOS programmable range
3.5
ASSERT
Low Input LOS Assert threshold
Low Input LOS De-Assert threshold
Medium Input LOS Assert threshold
R
R
R
R
= 7.50 kΩ, differential input
= 7.50 kΩ, differential input
= 6.81 kΩ, differential input
= 6.81 kΩ, differential input
3.5
–
4.9
mV
LOW
ST
ST
ST
ST
PP
PP
PP
PP
DEASSERT
ASSERT
7.8
11.3
–
mV
mV
mV
LOW
8.4
–
11.7
17.0
MED
DEASSERT
Medium Input LOS De-Assert
threshold
24.6
MED
ASSERT
High Input LOS Assert threshold
R
R
= 6.19 kΩ, differential input
= 6.19 kΩ, differential input
16.6
–
23.2
33.4
–
–
mV
mV
HI
ST
PP
DEASSERT
High Input LOS De-Assert threshold
48.4
80
HI
ST
PP
T
Time from LOS state until LOS output LOS assert time after 1 V input signal is turned
2.3
μs
LOS_ON
PP
(1)
is asserted
off; signal detect level set to 10 mV
T
Time from non-LOS state until LOS is LOS deassert time after input crosses signal detect
2.3
–
80
μs
LOS_OFF
(2)
deasserted
level; signal detect set to 10 mV with applied input
signal of 20 mV
PP
Notes:
1. With V
2. With V
= 1 V , typical times decrease as V
PP IN_DIFF
decreases.
IN_DIFF
= 20 mVpp, typical times decrease as V
increases.
IN_DIFF
IN_DIFF
6
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 1-1.
Data Input Requirements
Differential Input
DINP
2 - 600 mV
DINN
4 - 1200 mV
Single-ended Input
DINP or DINN
Unused Input
4 - 600 mV
NOTE:
For single-ended input connections.
When connecting to the used input with AC-coupling, the unused input should be AC-coupled through
50Ω to the supply voltage of the TIA;
When connecting to the used input with DC-coupling, the unused input should be DC-coupled through
50Ω to a voltage equal to the common mode level of the used input.
7
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
1.5
Typical Eye Diagrams
Figure 1-2. M02040 1.25 Gbps
Figure 1-3. M02040 2.125 Gbps
10 mVPP differential input
1.25 Gbps
10 mVPP differential input
2.125 Gbps
160 mV/div
140 ps/div
160 mV/div
80 ps/div
8
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
2.0 Pin Definitions
Table 2-1.
Pin Descriptions
QFN Pin#
Name
Function
1
2
3
4
5
6
7
GND
Ground.
V
Power supply. Connect to either +5V or +3.3V.
Inverting data output (PECL).
Non-inverting data output (PECL).
CC
PECLN
PECLP
I
Internal LOS reference current. Must be connected to ground through a 12.1 kΩ 1% resistor.
Loss of signal threshold setting input. Connect a 1% resistor between this pin and V to set loss of signal threshold.
REF
ST
SET
CC3
CC3
V
Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when V = 5V. Connect
CC
directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power supply if V = 5V.
CC
DC Servo disable. When high, the DC servo circuit is disabled, allowing the limiting amplifier to be used with data that has
changes quickly in amplitude and phase. Also useful for data containing significant low-speed or DC signals. When low or
floating, DC servo is enabled. Internal 80 kΩ resistor to ground. Drive with a current limited source as described in
Section 4.1.4.
8
DC_Servo
9
DINP
DINN
GND
Non-inverting data input. Internally terminated with 50 Ω to V (see Figure 3-2).
TT
10
11
12
Inverting data input. Internally terminated with 50 Ω to V (see Figure 3-2).
TT
Ground.
RxAVG
Average power monitor input. Connect to monitor output of TIAs that produce a current (sink) mirror replica of the
photodiode current. Leave floating if not used.
IN
13
JAM
Output disable. When high, data outputs are disabled (with non-inverting output held high and inverting output held low).
Connect to LOS output to disable outputs with loss of signal. Outputs are enabled when JAM is low or floating. Internal 150
kΩ resistor to ground.
14
15
16
17
LOS
Loss of signal output. Goes high when input signal falls below threshold set by ST . Open collector TTL with internal 80
SET
kΩ pull-up resistor to V
.
CC
RSSI
Receiver average input power monitor. Provides a current source mirror of the current at RxAVG . Connect a resistor to
AVG
IN
ground to set the full scale voltage to the desired level at maximum average input power.
RSSI
Receiver peak-to-peak input voltage monitor. Provides a DC voltage (ground referenced) proportional to the peak-to-peak
input voltage swing.
PP
Center Pad
Ground to PCB for thermal dissipation.
9
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 2-1. M02040-15 Pinout
16
13
GND
VCC
RxAvgIN
GND
1
4
12
Center Pad
Connect to GND
PECLN
PECLP
DINN
DINP
9
8
5
10
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
3.0 Functional Description
3.1
Overview
The M02040-15 is a high-gain limiting amplifier for applications up to 2.125 Gbps and incorporates a limiting ampli-
fier, an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not
require any external components. The M02040-15 features PECL data outputs.
The M02040-15 provides the user with the flexibility to set the signal detect threshold. Optional output buffer dis-
able (squelch/jam) can be implemented using the JAM input.
Figure 3-1. M02040-15 Block Diagram
DC_Servo
Jam
I
REF
V
TT
Biasing
DINP
DINN
PECLP
PECLN
Limiting
Amplifier
Output
Buffer
Offset cancel
RSSI
PP
Level
Detect
LOS
Comparator
RxAVG
Level
Shift
Threshold
Setting
Circuit
IN
Regulator
V
RSSI
AVG
ST
V
SET
CC3
CC
11
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
3.2
Features
•
•
•
•
Operates with a 3.3V or 5V supply
2 mV typical input sensitivity at 1.25 Gbps
PECL outputs
Average Receive power monitor output (RSSI
)
AVG
•
Peak-to-peak Receive power monitor output (RSSI
)
PP
•
•
•
•
•
On-chip DC offset cancellation circuit
Offset cancellation circuit can be disabled for Burst mode applications
Low power (170 mW at 3.3V)
Output Jam function
16-pin 3x3 mm QFN package
3.3
General Description
The M02040-15 is an integrated high-gain limiting amplifier. Featuring PECL outputs, the M02040-15 is useable in
applications to 2.125 Gbps. Full output swing is achieved even at minimum input sensitivity. The M02040-15 can
operate with a 3.3V or 5V supply.
DC_Servo supports applications requiring instantaneous output response.
The M02040-15 also includes two analog RSSI outputs proportional to either the average or peak to peak input sig-
nal and a programmable signal-level detector allowing the user to set thresholds at which the logic outputs are
enabled.
12
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
3.3.1
Inputs
The data inputs are internally connected to V via 50 Ω resistors, and generally need to be AC coupled. Referring
TT
to Figure 3-2, the nominal V voltage is 2.85V because of the internal resistor divider to V
, which means this is
TT
CC3
the DC potential on the data inputs. See the applications information section for further details on choosing the AC-
coupling capacitor.
Figure 3-2. CML Data Inputs
V
V
V
CC3
CC
CC
1.3 kΩ
8.3 kΩ
V
TT
50 Ω
50 Ω
DINN
DINP
3.3.2
DC Offset Compensation
The M02040-15 contain an internal DC autozero circuit that can remove the effect of DC offsets without using
external components. This circuit is configured such that the feedback is effective only at frequencies well below
the lowest frequency of interest. The low frequency cut off is typically 25 kHz.
13
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
3.3.3
Data Outputs
The M02040-15 features 100k/300k PECL compliant outputs as shown in Figure 3-3. The outputs may be termi-
nated using any standard AC or DC-coupling PECL termination technique. AC-coupling is used in applications
where the average DC content of the data is zero. The advantage of this approach is lower power consumption, no
susceptibility to DC drive and compatibility with non-PECL interfaces.
Figure 3-3. PECL Data Outputs
V
CC
PECLP
PECLN
50 Ω
50 Ω
V
- 2V
CC
14
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
3.3.4
Loss of Signal (LOS)
The M02040-15 features input signal level detection over an extended range. Using an external resistor, R ,
ST
between pin ST
and V
(Figure 3-5) the user can program the input signal threshold. The signal detect status
CC3
SET
is indicated on the LOS output pin shown in Figure 3-4. The LOS signal is active when the signal is below the
threshold value. The signal detection circuitry has the equivalent of 3.5 dB (typical) electrical hysteresis.
Figure 3-4. LOS Output
VCC
LOS
80 kΩ
R
establishes a threshold voltage at the ST
pin as shown in Figure 3-5. Internally, the input signal level is
SET
ST
monitored by the Level Detector (which also outputs the RSSI voltage). As described in the RSSI section, this
PP
PP
voltage is proportional to the input signal peak to peak value. The voltage at ST
is internally compared to the
SET
signal level from the Level Detector. When the Level Detect voltage is less than V
, LOS is asserted and will
(STSET)
stay asserted until the input signal level increases by a predefined amount of hysteresis. When the input level
increases by more than this hysteresis above V , LOS is deasserted. See the applications information sec-
(STSET)
tion for the selection of R .
ST
Note that ST
low.
can be left open if the loss of signal detector function is not required. In this case LOS would be
SET
15
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 3-5. ST
Input
SET
VCC3
VCC
RST
VSTSET
STSET
3.3.5
Peak to Peak Received Signal Strength Indicator (RSSIPP)
The RSSI output voltage is logarithmically proportional to the peak to peak level of the input signal. It is not nec-
PP
essary to connect an external capacitor to this output. Internally, the RSSI voltage is compared with a user select-
able reference to determine loss of signal as described in the previous section.
Figure 3-6. RSSI Output
PP
VCC3
VCC
RSSIPP
4 kΩ
I(RSSIPP
)
16
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 3-7. Typical RSSI Transfer Function
PP
275
250
225
200
175
150
125
100
75
50
25
0
0
25
50
75
100
125
150
175
200
Differential Input Level (mV )
PP
17
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 3-8. Typical RSSI Transfer Function (Low Input Level Range)
PP
225
200
175
150
125
100
75
50
25
0
0
5
10
15
20
25
30
35
40
45
50
Differential Input Level (mV )
PP
18
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 3-9. Typical RSSI Transfer Function (Log Scale)
PP
275
250
225
200
175
150
125
100
75
50
25
0
1
10
100
Differential Input Level (mV )
PP
3.3.6
JAM Function
When asserted, the active high power down (JAM) pin forces the outputs to a logic “one” state. This ensures that
no data is propagated through the system. The loss of signal detection circuit can be used to automatically force
the data outputs to a high state when the input signal falls below the threshold. The function is normally used to
allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the
data outputs toggling due to noise when there is no signal present (“squelch”).
In order to implement this function, LOS should be connected to the JAM pin shown in Figure 3-10, thus forcing the
data outputs to a logic “one” state when the signal falls below the threshold.
3.3.7
DC Servo Function
When the DC_Servo pin (shown in Figure 3-10) is driven high, the M02040-15 internal DC servo loop (described in
Section 3.3.2) is disabled and the part will pass DC signals. This is useful when using signals with an unequal mark
and space ratio, when the signal contains significant low speed or DC information, or when the input to the part
must be DC coupled to a TIA that will change its common mode output voltage very quickly. Note that when the
servo loop is disabled, any offset from the TIA or within the M02040-15 will cause DCD at the output which is a
function of the offset and the input PP amplitude (large offsets and low amplitude input signals create the largest
output DCD). When this pin is tied low or floating the 2040-15 servo loop operates as described in Section 3.3.2.
19
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 3-10. JAM and DC_Servo Input
VCC
JAM and
R1
DC_Servo
R2
R1 = 55 kΩ for JAM, 30 kΩ for DC_Servo
R2 = 100 kΩ for JAM, 50 kΩ for DC_Servo
3.3.8
Average Received Signal Strength Indicator (RSSIAVG)
The RSSI
output current is a mirrored version of the RxAVG current from compatible TIAs. It sources rather
IN
AVG
than sinks the current making it compatible with DDMI type interfaces.
Figure 3-11. RSSI Output
AVG
VCC
VCC3
VCC
RxAVGIN
RSSIAVG
REXT
(From TIA)
3.3.9
Voltage Regulation
The M02040-15 contains an on-chip voltage regulator to allow both 5V and 3.3V operation. When used at 5V, the
on-chip regulator is enabled and the digital inputs and outputs are compatible with TTL 5V logic levels.
20
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
4.0 Applications Information
4.1
Applications
•
•
•
1.0625 and 2.125 Gbps Fibre Channel
1.25 Gbps Ethernet
1.25 Gbps SDH/SONET
Figure 4-1. Typical Applications Circuit
DC_Servo Control
12.1 kΩ
optional
DC_Servo
Jam
I
REF
Biasing
+3.3 V
V
TT
AC-Coupled
to TIA
PECLP
PECLN
DINP
Clock Data
Limiting
Amplifier
M
02
0
16
Recovery
Unit
Photodiode
DINN
MON
Offset cancel
Level
Detect
RSSI
PP
AC or DC Coupled
(as described in
Applications Information)
Comparator
RxAVG
IN
Level
Shift
Threshold
Setting
Circuit
Regulator
RSSI
AVG
LOS
R
EXT
ST
V
V
SET
CC3 CC
R
ST
21
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
4.1.1
Reference Current Generation
The M02040-15 contain an accurate on-chip bias circuit that requires an external 12.1 kΩ 1% resistor, R , from
REF
pin I
to ground to set the LOS threshold voltage at ST
precisely.
REF
SET
Figure 4-2. Reference Current Connection
VCC3
RST
STSET
VSET
LOS
VLVL_Det
BG_Ref
IREF
RREF
4.1.2
Connecting VCC and VCC3
For 5V operation, the V pin is connected to an appropriate 5V 7.5% supply. No potential should be applied to
CC
the V
pin. The only connection to V
should be R as shown in Figure 3-5.
CC3 ST
CC3
When V = 5V all logic outputs and the data outputs are 5V compatible while the CML data inputs are still refer-
CC
enced to 3.3V from the internal regulator (see Figure 3-2). For low power operation, V and V
should be con-
CC3
CC
nected to an appropriate 3.3V 7.5% supply. In this case all I/Os are 3.3V compatible.
4.1.3
Choosing an Input AC-Coupling Capacitor
When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of
interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. For Ethernet
or Fibre Channel data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than
1/(1,000) of the input data rate. For example, for 1.25 Gbps data, the coupling capacitor should be chosen as:
22
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
9
3
6
f
≤ (1.25x10 / 1x10 ) = 1.25x10
CUTOFF
The -3 dB cutoff frequency of the low pass filter at the 50 Ω input is found as:
= 1/ (2 * π * 50 Ω * C
f
)
AC
3dB
so solving for C where f
= f
CUTOFF
3dB
C
= 1/ (2 * π * 50 Ω * f
)
EQ.1
AC
CUTOFF
and in this case the minimum capacitor is 2.5 nF.
For 2.125 Gbps Fibre Channel, this results in a minimum capacitor of 1.5 nF.
4.1.3.1
Multirate applications down to 155 Mbps
6
In this case, the input coupling capacitor needs to be large enough to pass 15 kHz (155x10 /10,000) which results
in a capacitor value of 0.2 μF. However, because this low pass frequency is close to the 25 kHz low pass frequency
of the internal DC servo loop, it is preferable to use a larger input coupling capacitor such as 1 μF which provides
an input cutoff frequency of 3.1 kHz. This separates the two poles sufficiently to allow them to be considered inde-
pendent. This capacitor should also have a 10 nF capacitor in parallel to pass the higher frequency data (in the
multirate application) without distortion.
In all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input
data stream.
4.1.4
Using DC_Servo
When the DC_Servo pin (shown in Figure 3-10) is tied high, the M02040-15 disables the internal servo loop which
allows the device to pass signals with DC content resulting in instantaneous response to changes in the input data
stream (e.g. data amplitude and phase). However, there is no correction for limit amp offset when the servo loop is
disabled which results in degraded sensitivity and increased duty cycle distortion.
Because of the nature of the ESD structure on this pin, if it is driven by a device with I or I > 2 mA then a 1 kΩ
OL
OH
to 10 kΩ resistor should be used in series with the DC_Servo pin. If the internal servo loop is never going to be dis-
abled, DC_Servo should be should be connected to ground using a 1kΩ to 10kΩ resistor. If the internal servo loop
is going to be continuously disabled, the DC_Servo pin should be connected to V using a 1 kΩ to 10 kΩ resistor.
CC
4.1.5
Using RSSIAVG
As shown in the typical applications circuit (front page), when interfacing to a TIA that features a “MON” output
such as the M02010 or M02016, the M02040-15 can reference the current sunk into the TIA “MON” output and pro-
duce a proportional current at the 2040 RSSI
output. The current is sourced into resistor R
to ground creat-
AVG
EXT
ing a voltage suitable for DDMI applications. R
should be chosen as:
EXT
R
= 1/(maximum current into RSSI
)
EQ.2
EXT
AVG
This keeps the voltage at RSSI
between 0 and 1 V.
AVG
23
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
4.1.6
Setting the Signal Detect Level
Using Figure 4-3, the value for R is chosen to set the LOS threshold at the desired value. The resulting hystere-
ST
sis is also shown in Figure 4-3.
From Figure 4-3, it is apparent that small variations in R cause significant variation in the LOS threshold level,
ST
particularly for low input signal levels. This is because of the logarithmic relationship between the RSSI voltage and
the input signal level. It is recommended that a 1% resistor be used for R and that allowance is provided for LOS
ST
variation, particularly when the LOS threshold is near the sensitivity limit of the M02040-15.
Example R resistor values are given in Table 4-1.
ST
Table 4-1.
Typical LOS Assert and De-assert Levels for Various 1% R Resistor Values
ST
VIN (mV pp) differential
LOS De-Assert
R
(kΩ)
ST
LOS Assert
4.9
7.50
7.8
6.81
6.19
5.49
11.7
17.0
33.4
77.3
23.2
55.0
Figure 4-3. Typical Loss of Signal Characteristic (Full Input Signal Range)
80
Conditions:
1.25 Gbps, 231 - 1
Vcc = 3.3V, Temp = 25C
70
60
50
40
30
20
10
0
De-assert
Assert
Optical Hysteresis
= 10*log10(De-assert/Assert)
5.5
5.7
5.9
6.1
6.3
6.5
6.7
6.9
7.1
7.3
7.5
RST (kΩ)
24
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 4-4. Typical Loss of Signal Characteristic (Low Input Signal Range)
30
Conditions:
1.25 Gbps, 231 - 1
Vcc = 3.3V, Temp = 25C
20
10
0
De-assert
Assert
Optical Hysteresis = 10*log10(De-assert/Assert)
6.5
6.7
6.9
7.1
7.3
7.5
RST (kΩ)
25
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 4-5. Typical Loss of Signal Characteristic (High Input Signal Range)
80
Conditions:
1.25 Gbps, 231 - 1
Vcc = 3.3V, Temp = 25C
70
60
50
40
30
20
10
0
De-assert
Assert
Optical Hysteresis
= 10*log10(De-assert/Assert)
5.5
5.7
5.9
6.1
6.3
6.5
RST (kΩ)
26
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 4-6. Typical Loss of Signal Hysteresis Characteristic (Full Input Signal Range)
5.0
4.5
Electrical Hysteresis
= 20*log10(De-assert/Assert)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Conditions:
1.25 Gbps, 231 - 1
Vcc = 3.3V, Temp = 25C
5.5
5.7
5.9
6.1
6.3
6.5
6.7 6.9
7.1
7.3 7.5
RST (kΩ)
4.1.7
PECLP and PECLN Termination
The outputs of the M02040-15 are PECL compatible and any standard AC or DC-coupling termination technique
can be used. Figure 4-7 and Figure 4-8 illustrate typical AC and DC terminations.
AC-coupling is used in applications where the average DC content of the data is zero e.g. SONET. The advantage
of this approach is lower power consumption, no susceptibility to DC drift and compatibility with non-PECL inter-
faces. Figure 4-7 shows the circuit configuration and Table 4-2 lists the resistor values. If using transmission lines
other than 50 Ω, the shunt terminating resistance Z should equal twice the impedance of the transmission line
T
(Z ).
O
DC-coupling can be used when driving PECL interfaces and has the advantage of a reduced component count. A
Thevenin termination is used at the receive end to give a 50 Ω load and the correct DC bias. Figure 4-8 shows the
circuit configuration and Table 4-2 the resistor values.
Alternatively, if available, terminating to V - 2V as shown in Figure 4-9 has the advantage that the resistance
CC
value is the same for 3.3 V and 5 V operation and it also has performance advantages at high data rates.
27
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Table 4-2.
PECL Termination Resistor Values
Output
Impedance
R
Z
R
/ R
R / R
T B
Supply
PULL-DOWN
T
TA
TB
5V
50 Ω
50 Ω
270 Ω
150 Ω
100 Ω
100 Ω
2.7 kΩ / 7.8 kΩ
2.7 kΩ / 4.3 kΩ
82 Ω / 130 Ω
130 Ω / 82 Ω
3.3V
Figure 4-7. AC-Coupled PECL Termination
VCC
VCC
RTA
RTA
0.1µF
0.1µF
Zo
Zo
PECLP
ZT
PECL
PECLN
M02040
RTB
RTB
RPULL-DOWN
Figure 4-8. DC-Coupled PECL Termination
VCC
VCC
10 nF
RT
RT
Zo
Zo
PECLP
PECL
PECLN
M02040
RB
RB
28
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
Figure 4-9. Alternative PECL Termination
VCC
VCC
Zo
PECLP
PECL
Zo
M02040
PECLN
50 Ω
50 Ω
10 nF
VCC - 2V
4.1.8
Using JAM
As shown in the typical applications circuit (Figure 1-2), the LOS output pin can optionally be connected to the Jam
input pin. When LOS asserts the Jam function sets the data outputs to a fixed “one” state (PECLP is held high and
PECLN is held low). This is normally used to allow data to propagate only when the signal is above the users' bit
error rate (BER) requirement. It prevents the outputs from toggling due to noise when no signal is present.
From the LOS assert and deassert figures above (Figure 4-2 - Figure 4-4), when an input signal is below the LOS
assert threshold, LOS asserts (LOS high) causing Jam to assert. When Jam asserts, the data outputs and the
internal servo loop of the M02040-15 are disabled. If the input signal reaches or exceeds the LOS deassert
threshold, LOS deasserts (LOS low) causing Jam to deassert, and hence enables the data outputs and the internal
servo loop. If, however, the input signal is slowly increasing to a level that does not exceed the LOS deassert
threshold (operating in the hysteresis region), the internal servo loop may not be fully established and this may
cause partial enabling of the data outputs. To avoid this the input signal needs to fully reach or exceed the LOS
deassert level to fully enable the data outputs.
29
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
5.0 Package Specification
Figure 5-1. Package Information
Note: View is for a 12 pin package. All dimensions in the
tables apply for the 16 pin package
16
4
4
1.35
1.35
1.50
1.50
1.65
1.65
30
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M02040-15
3.3/5V Limiting Amplifier for Applications to 2.125 Gbps
Rev V4
M/A-COM Technology Solutions Inc. All rights reserved.
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products. These materials are provided by MACOM as a service to its customers and may be used for
informational purposes only. Except as provided in MACOM's Terms and Conditions of Sale for such products or
in any separate agreement related to this document, MACOM assumes no liability whatsoever. MACOM assumes
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product descriptions at any time, without notice. MACOM makes no commitment to update the information and
shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its
specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any
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WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
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