M02044CG-31 [TE]
3.3/5V Limiting Amplifier for Applications from 100 Mbps to 622 Mbps;
| 型号： | M02044CG-31 |
| 厂家： | 
TE CONNECTIVITY |
| 描述： | 3.3/5V Limiting Amplifier for Applications from 100 Mbps to 622 Mbps |
| 文件： | 总22页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M02044CG-31
3.3/5V Limiting Amplifier for Applications from 100 Mbps to
622 Mbps
The M02044 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and foot-
print as the MC2044C (refer to 02044-APP-001-A where A is the revision which will change if the application note is
revised). Featuring PECL outputs, the M02044 is intended for use in applications from 100 Mbps to 622 Mbps. Full
output swing is achieved even at minimum input sensitivity. The M02044 can operate with a 3.3V or 5V supply.
Included in the M02044 is a programmable signal-level detector, allowing the user to set thresholds at which the
logic outputs are enabled. The signal detect function has typically 2 dB (optical) of hysteresis which prevents chatter
at low input levels. A squelch function, which turns off the output when no signal is present, is provided by externally
connecting the LOS Status output to the JAM input.
The M02044 has CMOS Status and LOS outputs.
Other available solutions: M02046-15 3.3/5V Limiting Amplifier for Applications to 1.25 Gbps (PECL outputs)
M02040-15 3.3/5V Limiting Amplifier for Applications to 2.125 Gbps (PECL outputs)
M02050-15 3.3/5V Limiting Amplifier for Applications to 2.5 Gbps (PECL outputs)
M02049-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
M02043-15 3.3/5V Limiting Amplifier for Applications to 4.3 Gbps (CML outputs)
Features
Applications
• Pin compatible with the MC2044C
• Operates with a 3.3V or 5V supply
• 2.8 mV typical input sensitivity at 622 Mbps
• Programmable input-signal level detect
• On-chip DC offset cancellation circuit
• CMOS Signal Detect and LOS outputs
• Output Jam Function
• 622 Mbps SDH/SONET
• 100 Mbps Ethernet
• SDH/SONET 155 Mbps Transceivers
• FTTx and Media Converters
• Fast Ethernet Receivers
• FDDI 125 Mbps Receivers
• ESCON Receivers
• Low power (< 200 mW at 3.3V including PECL load)
Typical Applications Diagram
12.1 kΩ
optional
Jam
I
REF
+3.3 V
V
TT
AC-Coupled
to TIA
Biasing
100nF
PECLP
PECLN
DINP
Clock Data
Recovery
Unit
Limiting
Amplifier
Output
Buffer
M
02
0
11
6.8pF*
DINN
Photodiode
100nF
MON
Offset cancel
Level
Detect
* The shunt capacitance is optional
but can improve receiver sensitivity
by ~0.5 dB
AC or DC Coupled
(as described in
Applications Information)
Comparator
Regulator
Threshold
Setting
Circuit
ST
LOS
V
CC
ST
SET
V
CC3
R
ST
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Ordering Information
Part Number
Package
Operating Temperature
–40 °C to 85 °C
M02044CG-31*
16 pin QSOP
–40 °C to 85 °C
M02044CG-31EVM
Evaluation board with M02044CG-31
* The letter “G” designator in the part number indicates that the device is RoHS-compliant. Refer to www.mindspeed.com for additional information.
Revision History
ASIC
Revision
Revision
Level
Date
Description
A
Released
March 2008
-31
Initial Release
Typical Eye Diagram
Pin Configuration
ST
I
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SET
REF
V
NC
CC3
V
GND
DINP
DINN
NC
CC
PECLP
M02044CG-31
Date Code
PECLN
GND
V
ST
CC3
JAM
LOS
10 mVPP differential input
622 Mbps
150 mV/div
250 ps/div
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1.0 Product Specification
1.1
Absolute Maximum Ratings
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged.
Reliable operation at these extremes for any length of time is not implied.
Table 1-1.
Symbol
Absolute Maximum Ratings
Parameter
Rating
Units
V
Power supply voltage (V -GND)
-0.5 to +5.75
-65 to +150
V
°C
V
CC
CC
T
Storage temperature
STG
PECLP, PECLN
PECL Output pins voltage
V
- 2 to V + 0.4
CC
CC
I(PECLP), I(PECLN)
|DINP - DINN|
DINP, DINN
PECL Output pins maximum continuous current (delivered to load)
Data input pins differential voltage
30
mA
V
0.80
Data input pins voltage meeting |DINP - DINN| requirement
GND to V
+ 0.4
+ 0.4
V
CC3
CC3
ST
Signal detect threshold setting pin voltage
Output enable pin voltage
GND to V
V
V
SET
JAM
ST LOS
GND to V + 0.4
CC
Status Output pins voltage
GND to V + 0.4
V
,
CC
I
Current into Reference input
Current into Status Output pins
+0 to -120
µA
µA
REF
I(LOS), I(ST)
+3000 to -100
1.2
Recommended Operating Conditions
Table 1-2.
Recommended Operating Conditions
Parameter
Rating
Units
Power supply: (V -GND) (apply no potential to V ) or
+5V 7.5% or
+3.3V 7.5%
V
CC
CC3
(V -GND) (connect V to same potential as V )
CC3
CC
CC3
Junction temperature
-40 to +110
-40 to +85
°C
°C
Operating ambient
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Product Specification
1.3
DC Characteristics
V
CC = +3.3V 7.5% or +5V 7.5%, TA = -40°C to +85°C, unless otherwise noted.
Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-3.
DC Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
I
Supply Current
PECL outputs un-loaded
Single ended; 50Ω load to V - 2V
–
26
38
mA
CC
)
(1,2
V
PECL Output High Voltage
OUTHpecl
CC
(PECLP, PECLN)
V
V
-1.06
V
-0.952
V
V
-0.88
V
CC
CC
CC
CC
)
(1,2
V
PECL Output Low Voltage
(PECLP, PECLN)
Single ended; 50Ω load to V - 2V
OUTLpecl
CC
-1.86
V
-1.71
-1.62
V
Ω
V
CC
CC
R DIFF
Differential Input Resistance
ST, LOS Output High Voltage
ST, LOS Output Low Voltage
Measured between DINP and DINN
90
2.75
0
110
130
IN
V
External 4.7-10 kΩ pull up to V
External 4.7-10 kΩ pull up to V
V
CC
–
OH_CMOS
CC
CC
V
–
–
0.4
2.0
V
OL_CMOS
OL_CMOS
I
ST, LOS Output Low Current
(into device)
V
determined by external pull up to V
–
mA
OL
CC
V
JAM Input High Voltage
JAM Input Low Voltage
2.7
–
–
–
V
V
V
IH
CC
V
0.8
IL
Notes:
1. Limits apply between 0°C to +85°C. Below 0°C the minimum decreases by up to 40 mV.
2. In most applications the PECL outputs are AC coupled to the following device, so the actual VOH and VOL levels are not meaningful for the PECL
outputs. Only the peak to peak swing is transmitted to the load device.
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Product Specification
1.4
AC Characteristics
V
CC = +3.3V 7.5% or +5V 7.5%, TA = -40°C to +85°C, input bit rate = 622 Mbps 223-1 PRBS unless
otherwise noted. Typical specifications are for VCC = 3.3V, TA = 25°C, unless otherwise noted.
Table 1-4.
AC Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
-10
V
Differential Input Sensitivity
Input Overload
622 Mbps, BER < 10
–
2.5
4.5
mV
IN(MIN)
-10
V
BER < 10 , differential input 622 Mbps
1200
600
5
–
–
–
–
–
mV
mV
mV
I(MAX)
-10
BER < 10 , single-ended input, 622 Mbps
(1)
V
LOS Programmable Range
Differential inputs
55
TH
HYS
BW
Signal Detect/LOS Hysteresis
(electrical); across LOS programmable range
2
–
3.5
25
5.5
–
dB
Small-Signal –3dB Low Frequency Excluding AC coupling capacitors
Cutoff
kHz
LF
DJ
RJ
Deterministic Jitter (includes DCD) K28.5 pattern at 622 Mbps, 10 mV input
–
–
0.02
5
0.1
–
UI
PP
Random Jitter
10 mV input
ps
RMS
PP
t / t
Data Output Rise and Fall Times
20% to 80%; outputs terminated into 50Ω;
–
150
250
ps
µs
µs
r
f
10 mV input
PP
T
Time from LOS state until LOS
output is asserted
LOS assert time after 1 V input signal is turned
2.3
2.3
–
80
LD_ON
LD_OFF
PP
off; signal detect level set to 10 mV
T
Time from non-LOS state until LOS LOS deassert time after input crosses signal detect
–
80
is deasserted
level; signal detect set to 10 mV with applied input
signal of 20 mV
PP
V
RMS Input Referred Noise
DC to 467 MHz Bessel Filter
–
200
–
µV
RMS
N
Note:
1. This compares to 20 mV maximum for the MC2044 making the M02044CG compatible with the Mindspeed M02011 622 Mbps TIA without having
to use an attenuator between the TIA output and LIA input to set the LOS threshold.
Figure 1-1. Data Input Requirements
Differential Input
DINP
2 - 600 mV
DINN
4 - 1200 mV
Single-ended Input
DINP or DINN
Unused Input
4 - 600 mV
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Product Specification
Figure 1-2. Typical Applications Circuit
12.1 kΩ
optional
Jam
I
REF
+3.3 V
V
TT
AC-Coupled
to TIA
Biasing
100nF
PECLP
DINP
6.8pF*
Clock Data
Limiting
Amplifier
Output
Buffer
Recovery
Unit
M02011
Photodiode
DINN
PECLN
100nF
MON
Offset cancel
Level
Detect
* The shunt capacitance is optional
but can improve receiver sensitivity
by ~0.5 dB
AC or DC Coupled
(as described in
Applications Information)
Comparator
Regulator
Threshold
Setting
Circuit
ST
LOS
V
CC
ST
SET
V
CC3
R
ST
NOTE:
For single-ended input connections.
When connecting to the used input with AC-coupling, the unused input should be AC-coupled through
50Ω to the supply voltage of the TIA;
When connecting to the used input with DC-coupling, the unused input should be DC-coupled through
50Ω to a voltage equal to the common mode level of the used input.
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2.0 Pin Definitions
Table 2-1.
QSOP Pin#
1
Pin Descriptions
Name
Function
ST
Loss of signal threshold setting input. Connect a 1% resistor between this pin and V
threshold.
(pin 2) to set loss of signal
CC3
SET
2
V
Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when V = 5V.
CC3
CC
Connect directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power supply if
V
= 5V.
CC
3
4
5
6
7
GND
DINP
DINN
NC
Ground.
Non-inverting data input. Internally terminated with 50Ω to V (see Figure 3-2).
TT
Inverting data input. Internally terminated with 50Ω to V (see Figure 3-2).
TT
No Connect. Leave Floating.
V
Power supply input for 3.3V applications or the output of the internally regulated 3.3V voltage when V = 5V.
CC3
CC
Connect directly to supply for 3.3V applications (internal regulator not in use). Do not connect to power supply if
V
= 5V.
CC
8
JAM
Output disable. When high, data outputs are disabled (with non-inverting output held high and inverting output
held low). Connect to LOS output to disable outputs with loss of signal. Outputs are enabled when JAM is low or
floating. Internal 150 kΩ resistor to ground.
9
LOS
ST
Loss of signal output. Goes high when input signal falls below threshold set by ST . This output is an open
SET
collector TTL with internal 80 kΩ pull-up resistor to V . Leave floating if not used.
CC
10
Signal detect output. Goes high when input signal amplitude is above threshold set by ST . In M02044, this
SET
output is an open collector TTL with internal 80 kΩ pull-up resistor to V . Leave floating if not used.
CC
11
12
13
14
GND
Ground.
PECLN
PECLP
Inverting data output (PECL).
Non-inverting data output (PECL).
Power supply. Connect to either +5V or +3.3V.
V
CC
15
16
NC
No Connect. Leave Floating.
I
Internal reference current for the LOS threshold. Must be connected to ground through a 12.1 kΩ 1% resistor.
REF
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Pin Definitions
Figure 2-1. M02044 Pinout
ST
SET
I
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
V
NC
CC3
V
GND
DINP
DINN
CC
PECLP
M02044CG-31
Date Code
PECLN
GND
NC
V
ST
CC3
JAM
LOS
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3.0 Functional Description
3.1
Overview
The M02044 is a highly integrated high-gain limiting amplifier that can be used with the same board layout and
footprint as the MC2044C. Featuring PECL outputs, the M02044 is intended for use in applications from 100 Mbps
to 622 Mbps. Full output swing is achieved even at minimum input sensitivity. The M02044 can operate with a 3.3V
or 5V supply.
Included in the M02044 is a programmable signal-level detector, allowing the user to set thresholds at which the
logic outputs are enabled. The signal detect function has typically 2 dB (optical) of hysteresis which prevents
chatter at low input levels. A squelch function, which turns off the output when no signal is present, is provided by
externally connecting the LOS Status output to the JAM input.
The M02044 has CMOS Status and LOS outputs.
Figure 3-1. Block Diagram Example
Jam
I
REF
V
TT
Biasing
DINP
DINN
PECLP
PECLN
Limiting
Amplifier
Output
Buffer
Offset cancel
Level
Detect
ST
Comparator
LOS
Threshold
Setting
Circuit
Regulator
V
ST
V
SET
CC3
CC
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Functional Description
3.2
Features
•
•
•
•
•
•
•
•
Pin compatible with the MC2044C
Operates with a 3.3V or 5V supply
2.8 mV typical input sensitivity at 622 Mbps
Programmable input-signal level detect
On-chip DC offset cancellation circuit
CMOS Signal Detect and LOS outputs
Output Jam Function
Low power (< 200 mW including PECL outputs)
3.3
General Description
The M02044 is a high-gain limiting amplifier for applications up to 622 Mbps, and incorporates a limiting amplifier,
an input signal level detection circuit and also a fully integrated DC-offset cancellation loop that does not require
any external components. The M02044 features PECL high-speed data outputs.
The M02044 provides the user with the flexibility to set the signal detect threshold and features CMOS status and
LOS outputs. Optional output buffer disable (squelch/jam) can be implemented using the JAM input.
3.3.1
Inputs
The data inputs are internally connected to V via 50Ω resistors, and generally need to be AC coupled. Referring
TT
to Figure 3-2, the nominal V voltage is 2.85V because of the internal resistor divider to V
, which means this is
TT
CC3
the DC potential on the data inputs. See the applications information section for further details on choosing the AC-
coupling capacitor.
Figure 3-2. CML Data Inputs
V
V
V
CC3
CC
CC
1.3 kΩ
8.3 kΩ
V
TT
50 Ω
50 Ω
DINN
DINP
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Functional Description
3.3.2
DC Offset Compensation
The M02044 contain an internal DC autozero circuit that can remove the effect of DC offsets without using external
components. This circuit is configured such that the feedback is effective only at frequencies well below the lowest
frequency of interest. The low frequency cut off is typically 25 kHz.
3.3.3
Data Outputs
The M02044 features PECL outputs as shown in Figure 3-3. The outputs may be terminated using any standard
AC or DC-coupling PECL termination technique. AC-coupling can be used for compatibility with non-PECL
interfaces.
Figure 3-3. PECL Data Outputs
V
CC
PECLP
PECLN
50 Ω
50 Ω
V
- 2V
CC
3.3.4
Signal Detect (ST) and Loss of Signal (LOS)
The M02044 features input signal level detection over an extended range. Using an external resistor, R , between
ST
pin ST
and V
(Figure 3-5) the user can program the input signal threshold. The signal detect status is
CC3
SET
indicated on the both the Signal Detect (ST) and LOS output pins. Figure 3-4 shows the ST and LOS output
structure.
The ST (LOS) signal is active (not asserted) when the signal is above the threshold value. The signal detection
circuitry has the equivalent of 3.5 dB (typical) electrical hysteresis.
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Functional Description
Figure 3-4. ST and LOS Output
VCC
Either
LOS or
80 kΩ
ST
R
establishes a threshold voltage at the ST
pin as shown in Figure 3-5. Internally, the input signal level is
SET
ST
monitored by the Level Detector which creates a DC voltage proportional to the input signal peak to peak value.
The voltage at ST is internally compared to the signal level from the Level Detector. When the Level Detect
SET
voltage is less than V
, LOS is asserted and will stay asserted until the input signal level increases by a
(STSET)
predefined amount of hysteresis. When the input level increases by more than this hysteresis above V
, LOS
(STSET)
is deasserted. See the applications information section for the selection of R .
ST
Note that ST
low.
can be left open if the loss of signal detector function is not required. In this case LOS would be
SET
Figure 3-5. STset Input
VCC3
VCC
RST
VSTSET
STSET
3.3.5
JAM Function
When asserted, the active high power down (JAM) pin forces the outputs to a logic “one” state. This ensures that
no data is propagated through the system. The loss of signal detection circuit can be used to automatically force
the data outputs to a high state when the input signal falls below the threshold. The function is normally used to
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Functional Description
allow data to propagate only when the signal is above the user's bit-error-rate requirement. It therefore inhibits the
data outputs toggling due to noise when there is no signal present (“squelch”).
In order to implement this function, LOS should be connected to the JAM pin shown in Figure 3-6, thus forcing the
data outputs to a logic “one” state when the signal falls below the threshold.
Figure 3-6. JAM Input
VCC
JAM
55 kΩ
100 kΩ
3.3.6
Voltage Regulation
The M02044 contain an on-chip voltage regulator to allow both 5V and 3.3V operation. When used at 5V, the on-
chip regulator is enabled and the digital inputs and outputs are compatible with TTL 5V logic levels.
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4.0 Applications Information
4.1
Applications
•
•
•
•
•
•
•
622 Mbps SDH/SONET
100 Mbps Ethernet
SDH/SONET 155 Mbps Transceivers
FTTx and Media Converters
Fast Ethernet Receivers
FDDI 125 Mbps Receivers
ESCON Receivers
4.1.1
Reference Current Generation
The M02044 contain an accurate on-chip bias circuit that requires an external 12.1 kΩ 1% resistor, R , from pin
REF
I
to ground to set the LOS threshold voltage at ST
precisely.
REF
SET
Figure 4-1. Reference Current Generation
VCC3
RST
STSET
VSET
LOS
VLVL_Det
BG_Ref
IREF
RREF
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Applications Information
4.1.2
Connecting VCC and VCC3
For 5V operation, the V pin is connected to an appropriate 5V 7.5% supply. No potential should be applied to
CC
the V
pin. The only connection to V
should be R as shown in Figure 3-5.
CC3 ST
CC3
When V = 5V all logic outputs and the data outputs are 5V compatible. For low power operation, V and V
CC3
CC
CC
should be connected to an appropriate 3.3V 7.5% supply. In this case all I/Os are 3.3V compatible.
4.1.3
Choosing an Input AC-Coupling Capacitor
When AC-coupling the input the coupling capacitor should be of sufficient value to pass the lowest frequencies of
interest, bearing in mind the number of consecutive identical bits, and the input resistance of the part. For SONET
data, a good rule of thumb is to chose a coupling capacitor that has a cut-off frequency less than 1/10,000 of the
input data rate. For example, for 622 Mbps data, the coupling capacitor should be chosen as:
6
3
f
≤ (622x10 / 10x10 ) = 62.2 kHz
CUTOFF
The -3 dB cutoff frequency of the low pass filter at the input is found as (assuming that the TIA output is also 50Ω
single-ended):
f
= 1/ (2 * π * 100Ω * C
)
3dB
AC
so solving for C where f
= f
CUTOFF
3dB
C
= 1/ (2 * π * 100Ω * f
)
EQ.1
AC
CUTOFF
and in this case the minimum capacitor is 25.6 nF.
For Ethernet or Fibre Channel, there are less consecutive bits in the data, and the recommended cut-off frequency
is 1/(1,000) of the input data rate. This results in a minimum capacitor of 16 nF (or greater) for 100 Mbps Ethernet.
In all cases, a high quality coupling capacitor should be used as to pass the high frequency content of the input
data stream. It is also important that the ROSA bandwidth is sufficiently low and high enough to also support the
required data rate, for it’s lower and upper cutoff bandwidth impact the receiver bandwidth as much as does the
limiting amp’s lower and upper cutoff bandwidth.
4.1.4
Setting the Signal Detect Level
Using Figure 4-2, the value for R is chosen to set the LOS threshold at the desired value. The resulting
ST
hysteresis is also shown in Figure 4-2.
From Figure 4-2, it is apparent that small variations in R cause significant variation in the LOS threshold level,
ST
particularly for low input signal levels. This is because of the logarithmic relationship between the internal level
detect voltage and the input signal level. It is recommended that a 1% resistor be used for R and that allowance
ST
is provided for LOS variation, particularly when the LOS threshold is near the sensitivity limit of the M02044.
Example R resistor values are given in Table 4-1.
ST
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Applications Information
Table 4-1.
Typical LOS Assert and De-assert Levels for Various 1% R Resistor Values
ST
VIN (mV pp) differential
LOS De-Assert
R
(kΩ)
ST
LOS Assert
4.9
7.50
7.8
6.81
6.19
5.49
11.7
17.0
33.4
77.3
23.2
55.0
Figure 4-2. Typical Loss of Signal Characteristic (Full Input Signal Range)
80
Conditions:
622 Mbps, 2 31 - 1
70
60
50
40
30
20
10
0
Vcc = 3.3V, Temp = 25C
De-assert
Assert
Optical Hysteresis
= 10*log10(De-assert/Assert)
5.5
5.7
5.9
6.1
6.3
6.5
6.7
6.9
7.1
7.3
7.5
RST (kΩ)
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Applications Information
Figure 4-3. Typical Loss of Signal Characteristic (Low Input Signal Range)
30
Conditions:
622 Mbps, 2 31 - 1
Vcc = 3.3V, Temp = 25C
20
10
0
De-assert
Assert
Optical Hysteresis = 10*log10(De-assert/Assert)
6.5
6.7
6.9
7.1
7.3
7.5
RST (kΩ)
Figure 4-4. Typical Loss of Signal Characteristic (High Input Signal Range)
80
Conditions:
70
60
50
40
30
20
10
0
622 Mbps, 2 31 - 1
Vcc = 3.3V, Temp = 25C
De-assert
Assert
Optical Hysteresis
= 10*log10(De-assert/Assert)
5.5
5.7
5.9
6.1
6.3
6.5
RST (kΩ)
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Applications Information
Figure 4-5. Typical Loss of Signal Hysteresis Characteristic (Full Input Signal Range)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Electrical Hysteresis
= 20*log10(De-assert/Assert)
Conditions:
622 Mbps, 2 31 - 1
Vcc = 3.3V, Temp = 25C
5.5
5.7
5.9
6.1
6.3
6.5
6.7
6.9
7.1
7.3
7.5
RST (kΩ)
4.1.5
PECLP and PECLN Termination
The data outputs of the M02044 are PECL. Figure 4-6 illustrates PECL compliant PECL termination. This is the
only termination where PECL specifications are guaranteed (this is level shifted ECL100k/300k ECL termination).
For the high speed PECLP and PECLN outputs any standard AC or DC-coupling termination technique can be
used. Figure 4-7 illustrates the most common PECL termination in use today and Table 4-2 lists the pull down
resistor values. Since this type of termination is AC coupled, the actual VOH and VOL levels are not meaningful for
the PECL outputs. Only the peak to peak swing is transmitted to the load device.
Figure 4-6. True PECL Termination
VCC
V
CC
Z
o
PECLP
PECLN
PECL
Zo
M02044
50 Ω
50 Ω
10 nF
VCC - 2V
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Applications Information
Figure 4-7. AC-Coupled PECL Termination
VCC
0.1µF
PECLP
PECLN
M02044
0.1µF
50Ω
50Ω
RPULL-DOWN
Table 4-2.
Supply
5V
PECL Termination Resistor Values
R
PULL-DOWN
270 Ω
150 Ω
3.3V
4.1.6
Using JAM
As shown in the typical applications circuit (Figure 1-2), the LOS output pin can optionally be connected to the Jam
input pin. When LOS asserts the Jam function sets the data outputs to a fixed “one” state (PECLP is held high and
PECLN is held low). This is normally used to allow data to propagate only when the signal is above the users' bit
error rate (BER) requirement. It prevents the outputs from toggling due to noise when no signal is present.
From the LOS assert and deassert figures above (Figure 4-2 - Figure 4-4), when an input signal is below the LOS
assert threshold, LOS asserts (LOS high) causing Jam to assert. When Jam asserts, the data outputs and the
internal servo loop of the M02044 are disabled. If the input signal reaches or exceeds the LOS deassert threshold,
LOS deasserts (LOS low) causing Jam to deassert, and hence enables the data outputs and the internal servo
loop. If, however, the input signal is slowly increasing to a level that does not exceed the LOS deassert threshold
(operating in the hysteresis region), the internal servo loop may not be fully established and this may cause partial
enabling of the data outputs. To avoid this the input signal needs to fully reach or exceed the LOS deassert level to
fully enable the data outputs.
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5.0 Package Specification
Figure 5-1. Package Information
Symbol
Tols/N
MAX.
±.05
QSOP16
1.60
A
A1
A2
D
0.1
±.05
1.40
±.05
4.95
E
±.10
6.00
E1
L
±.05
3.90
E
E1
±.15
0.60
ccc
ddd
e
MAX.
MAX.
BASIC
±.025
±.02
0.080
0.10
0.635
0.224
0.22
b
c
R
±.05
0.25
Bottom View
R1
Min.
0.20
Stand-Off
Seating Plane
A1 Stand-Off
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TM
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