73M1903-IGV/F [TERIDIAN]
Consumer Circuit, PQFP32, LEAD FREE, TQFP-32;型号: | 73M1903-IGV/F |
厂家: | TERIDIAN SEMICONDUCTOR CORPORATION |
描述: | Consumer Circuit, PQFP32, LEAD FREE, TQFP-32 |
文件: | 总45页 (文件大小:447K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
73M1903
Modem Analog Front End
DATA SHEET
SEPTEMBER 2006
DESCRIPTION
FEATURES
The TERIDIAN 73M1903 Analog Front End
(AFE) IC includes fully differential hybrid driver
outputs, which connect to the telephone line
interface through a transformer-based DAA. The
receive pins are also fully differential for
maximum flexibility and performance. This
arrangement allows for the design of a high
performance hybrid circuit to improve signal to
noise performance under low receive level
conditions, and compatibility with any standard
transformer intended for PSTN communications
applications.
•
•
•
•
•
•
Up to 56kbps (V.92) performance
Programmable sample rates (7.2 - 14.4kHz)
Reference clock range of 9-40MHz
Crystal frequency range of 9-27MHz
Host synchronous serial interface operation
Pin compatible with 73M2901CL/CE
modems
•
•
•
Low power modes
On board line interface drivers
Fully differential receiver and transmitter
Drivers for transformer interface
3.0V – 3.6V operation
The device incorporates
a
programmable
•
•
•
•
•
sample rate circuit to support soft modem and
DSP based implementations of all speeds up to
V.92 (56kbps). The sampling rates supported
are from 7.2kHz to 14.4kHz by programming
pre-scaler NCO and PLL NCO.
5V tolerant I/O
Industrial temperature range (-40 to +85°C)
JATE compliant transmit spectrum
Package options: 32-TQFP and 32-QFN
The TERIDIAN 73M1903 device incorporates a
digital host interface that is compatible with the
serial ports found on most commercially
available DSPs and processors and exchanges
both payload and control information with the
host.
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Set Top Boxes
Personal Video Recorders (PVR)
Multifunction Peripherals (MFP)
Fax Machines
Cost saving features of the device include an
input reference frequency circuit, which accepts
a range of crystals from 9-27MHz. It also
accepts external reference clock values between
9-40MHz generated by the host processor. In
most applications, this eliminates the need for a
dedicated crystal oscillator and reduces the bill
of material (BOM).
Internet Appliances
Game Consoles
Point of Sale Terminals
Automatic Teller Machines
Speaker Phones
RF Modems
VBG
(HYBRID)
The 73M1903 also supports two analog loop
back and one digital loop back test modes.
Transmit
Drivers/
Filters
Analog
Sigma
Delta
TXAP
TXAN
Ref.
SCLK
The 73M1903 in 32-TQFP package is footprint
compatible with 73M2901CL embedded modem
and allows for the same circuit design to
accommodate soft modem, V.22bis hard
modem, and high speed (V.32bis/V.34/V.92)
applications through population of an external
data pump device.
SDIN
Receive
Mux/
RXAP
RXAN
Control
Serial
Port
SDOUT
DAC
Registers
Filters
FSB
GPIO
DAA
Control
Logic
Clocks
Crystal
Controls
HOOK
Page: 1 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
REVISION HISTORY
Revision Level
Revision Date
Revision Description
2.4
March 13, 2003
Generated Preliminary Datasheet Release
Inconsistent Pin-out tables corrected; Entered
limitation on effective divide > = 2.0; VBG=1.19V; Fs
range increased to 14.4kHz; Gain change in ALB
mode (Txd code must be reduced by 3dB);SCLK drive
strength increased by x5.
2.5
May 22, 2003
3.0
3.3
June 2003
August 2003
Make changes to reflect B01
Make changes to reflect B02
Make changes to delete test comments and pass
3.4
3.5
3.6
August 2003
September 2003
September 9, 2003
band ripple
Revised front sheet, added block diagram, IDD current
changed.
Add active low fonts, clean up register map, match
text to figures, general cleanup
Update footer revision on pages 1,2
Removed Pin 21 CLKOUT signal from package
drawing.
3.7
September 9,2003
Update divider tables, RXG[1,0] setting, misc.
3.8
October 10, 2003
corrections
1.0
1.1
April 16, 2004
December 13, 04
Create Final Data Sheet
Minor modification for format
Company Logo change and minor modification for
1.2
July 15, 2005
format
1.3
1.4
Sept. 14,2006
Sept. 14,2006
Correct QFN pin-out drawing
Correct QFN pin-out drawing
Page: 2 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Table of Contents
DESCRIPTION..............................................................................................................................................1
FEATURES...................................................................................................................................................1
APPLICATIONS............................................................................................................................................1
REVISION HISTORY....................................................................................................................................2
SIGNAL DESCRIPTION ...............................................................................................................................5
SERIAL INTERFACE....................................................................................................................................6
MEMORY MAP .............................................................................................................................................9
GPIO ...........................................................................................................................................................11
ANALOG I/O ...............................................................................................................................................11
CLOCK GENERATION...............................................................................................................................13
Crystal Oscillator and Pre-scaler NCO..............................................................................................13
MODEM RECEIVER...................................................................................................................................19
MODEM TRANSMITTER............................................................................................................................22
TEST MODES.............................................................................................................................................26
POWER SAVING MODES..........................................................................................................................26
ELECTRICAL SPECIFICATIONS...............................................................................................................27
ABSOLUTE MAXIMUM RATINGS.........................................................................................................27
RECOMMENDED OPERATING CONDITIONS .....................................................................................27
DIGITAL SPECIFICATIONS .......................................................................................................................28
DC CHARACTERISTICS........................................................................................................................28
AC TIMING..............................................................................................................................................29
ANALOG SPECIFICATIONS ......................................................................................................................30
DC SPECIFICATIONS ............................................................................................................................30
AC SPECIFICATIONS ............................................................................................................................30
PERFORMANCE ....................................................................................................................................31
PACKAGE OPTIONS..................................................................................................................................34
MECHANICAL DRAWINGS........................................................................................................................35
MECHANICAL DRAWINGS cont................................................................................................................36
APPENDIX A...............................................................................................................................................37
73M1903 DAA Resistor Calculation Guide..........................................................................................37
APPENDIX B...............................................................................................................................................40
Crystal Oscillator...................................................................................................................................40
PLL..........................................................................................................................................................41
Examples of NCO settings ...................................................................................................................42
ORDERING INFORMATION.......................................................................................................................45
Page: 3 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
List of Figures
Figure 1 -SCLK and FS with SckMode = 0................................................................................................8
Figure 2 -Control frame position vs. SPOS ..............................................................................................8
Figure 3 -Serial Port Timing Diagram......................................................................................................10
Figure 4 -Analog block diagram ..............................................................................................................12
Figure 5 -Clock Generation......................................................................................................................18
Figure 6 -Overall Receiver Frequency Response..................................................................................20
Figure 7 -Rx Path Passband Response ..................................................................................................20
Figure 8 -RXD Spectrum of 1kHz tone ....................................................................................................21
Figure 9 -RXD Spectrum of 0.5kHz, 1kHz, 2kHz, 3kHz and 3.5kHz tones of Equal Amplitudes........21
Figure 10 -Frequency Response of TX Path for DC to 4kHz in band Signal.......................................22
Figure 11 -Serial Port Data Timing ..........................................................................................................29
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
SIGNAL DESCRIPTION
The TERIDIAN 73M1903 modem AFE IC is available in a 32 pin TQFP or QFN package with same pin
out. The following table describes the function of each pin. There are two pairs of power supply pins,
VPA(analog) and VPD(digital). They should be separately decoupled from the supply source in order to
isolate digital noise from the analog circuits internal to the chip. Failure to adequately isolate and
decouple these supplies will compromise device performance.
PIN NAME
TYPE PIN #
DESCRIPTION
VND
GND
GND
PWR
PWR
PWR
PWR
1,22
16
Negative Digital Ground
Negative Analog Ground
Positive Digital Supply
VNA
VPD
2,25
10
VPA
Positive Analog Supply
VPPLL
VNPLL
20
Positive PLL Supply, shared with VPD
Negative PLL Ground
17
Master reset. When this pin is a logic 0 all registers are reset to
their default states; Weak-pulled high- default
RST
I
9
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
OSCIN
I
19
18
OSCOUT
GPIO(0-7)
O
I/O
Crystal oscillator circuit output pin.
3, 4, 5, 6,
Software definable digital input/output pins.
23, 24,30,31
VREF
RXAP
RXAN
TXAP
TXAN
O
I
13
15
14
12
11
Reference voltage pin (Reflects Vref)
Receive analog positive input.
I
Receive analog negative input.
O
O
Transmit analog positive output
Transmit analog negative output
Serial interface clock. With SCLK continuous selected,
Frequency = 256*Fs ( =2.4576MHz for Fs=9.6kHz)
Serial data output (or input to the host).
Serial data input (or output from the host)
SCLK
O
8
SDOUT
SDIN
O
I
32
29
FS
O
I
7
Frame synchronization. (Active Low)
Type of frame sync. Open, weak-pulled high = early (mode1);
tied low = late (mode0)
TYPE
27
Controls the SCLK behavior after FS. Open, weak-pulled high
= SCLK Continuous; tied low = 32 clocks per R/W cycle.
SckMode
I
28
Table 1: -32 TQFP and QFN Pin Description
Page: 5 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
SERIAL INTERFACE
The serial data port is a bi-directional port that can be supported by most DSPs. Although the 73M1903
is a peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a
serial bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that
can be programmed by the user. The serial bit clock is always derived by dividing the system clock by 18.
The sclk rate, Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs
or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the
rate at which both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout
this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to facilitate
discussions. They are:
1. Fxtal1 = 27MHz, Fs1 = 7.2kHz
2. Fxtal2 = 18.432MHz, Fs2 = 8kHz.
3. Fxtal3 = 24.576MHz, Fs3 = 9.6kHz – chip default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz.
2. If Fxtal2 = 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz.
3. If Fxtal3 = 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz.
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs1 = 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz.
2. If Fs2 = 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz.
3. If Fs3 = 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition should be forced on or after the
second Frame Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data FS is generated by the 1903 at the rate of Fs. For every data FSB
there are 16 bits transmitted and 16 bits received. The frame synchronization (FS) signal is pin
programmable for type. FS can either be early or late determined by the state of the TYPE input pin.
When Type pin is left open, an early FS is generated in the bit clock prior to the first data bit transmitted
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
or received. When held low, a late FS operates as a chip select; the FS signal is active for all bits that are
transmitted or received. The TYPE input pin is sampled when the reset pin is active and ignored at all
other times. The final state of the TYPE pin as the reset pin is de-asserted determines the frame
synchronization mode used.
The bits transmitted on the SDOUT pin are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN
are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL
In this case TX0=0 is forced.
If the Hardware Control bit (bit 0 of register 01h) is set to one, the 16 bits that are received on the SDIN
input are defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
Bit 15 is transmitted/received first. Bits RX15:0 are the receive code word. Bits TX15:0 are the transmit
code word. If the hardware control bit is set to one, a control frame is initiated between every pair of data
frames. If the hardware control bit is set to zero, CTL is used by software to request a control frame. If
CTL is high, a control frame will be initiated before the next data frame. A control frame allows the
controller to read or write status and control to the 73M1903.
The control word received on the SDIN pin is defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
The control word transmitted on the SDOUT pin is defined as follows:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0
0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
If the R/W bit is set to a 0, the data byte transmitted on the SDOUT pin is all zeros and the data received
on the SDIN pin is written to the register pointed to by the received address bits; A6-A0. If the R/W bit is
set to a 1, there is no write to any register and the data byte transmitted on the SDOUT pin is the data
contained in the register pointed to by address bits A6-A0. Only one control frame can occur between
any two data frames.
Writes to unimplemented registers are ignored. Reading an unimplemented register returns a value of 0.
The position of a control data frame is controlled by the SPOS; bit 1 of register 01h. If SPOS is set to a 0
the control frames occur mid way between data frames, i.e., the time between data frames is equal. If
SPOS is set to a 1, the control frame is ¼ of the way between consecutive data frames, i.e., the control
frame is closer to the first data frame. This is illustrated in Figure 3.
Page: 7 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
New to TERIDIAN 73M1903 modem AFE IC is a feature that shuts off the serial clock (SCLK) after 32
cycles of SCLK following the frame synch (Figure 2). This mode is controlled by the SckMode pin. If this
pin is left open the clock will run continuously. If SckMode is low the clock will be gated on for 32 clocks
for each FS. The SDOUT and FS pins change values following a rising edge of SCLK. The SDIN pin is
sampled on the falling edge of SCLK. Figure 4 shows the timing diagrams for the serial port.
32 Cycles of sclk
SCLK
FS(mode1)
SCLK and FS in mode 1
32 Cycles of sclk
SCLK
FS(mode0)
SCLK and FS in mode 0
Figure 1 -SCLK and FS with SckMode = 0
Figure 2 -Control frame position vs. SPOS
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
MEMORY MAP
The following table shows the memory map of addressable registers in the 73M1903. Each register and
its bits are described in detail in the following sections.
ADRESS Default
BIT 7
ENFE
TMEN
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RXGAIN
HC
00
08h
00h
FFh
FFh
00h
00h
10h
00h
00h
0Ah
22h
12h
00h
C0h
00h
unused
DIGLB
DTMFBST TXBST0 TXDIS
RXG1
RXG0
01
ANALB
GPIO 5
DIR5
INTLB
reserved RXPULL SPOS
02
GPIO7 GPIO 6
GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
03
DIR7
DIR6
DIR4
DIR3
DIR2
DIR1
DIR0
reserved reserved
reserved reserved
reserved
reserved
reserved reserved reserved reserved reserved
reserved reserved reserved reserved reserved
04
05
06
Rev3
Rev2
Rev1
Rev0
unused reserved reserved reserved
reserved
reserved reserved reserved reserved reserved
07
unused reserved
08
Pseq7
Prst2
Ichp3
Pseq6
Prst1
Ichp2
Pseq5
Pseq4
Pdvsr4
Ichp0
Ndvsr4
Nseq4
Pseq3
Pdvsr3
FL
Ndvsr3
Nseq3
Pseq2
Pdvsr2
Kvco2
Ndvsr2
Nseq2
Pseq1
Pdvsr1
Kvco1
Ndvsr1
Nseq1
Nrst1
Pseq0
Pdvsr0
Kvco0
Ndvsr0
Nseq0
Nrst0
09
Prst0
0A
0B
0C
0D
0E
0E-7F
Ichp1
unused Ndvsr6
Ndvsr5
Nseq5
Nseq7
Xtal1
Nseq6
Xtal0
reserved reserved unused Nrst2
Frcvco PwdnPLL reserved unused unused unused unused unused
unused unused
unused
unused unused unused unused unused
To prevent unintended operation, do not write to reserved or unused locations. These locations are for
factory test or future use only and are not intended for customer programming.
Table 2: -Memory Map
Page: 9 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
SCLK
FS(mode1)
SDIN
TX15 TX14 TX13 TX12 TX11 TX10
RX15 RX14 RX13 RX12 RX11 RX10
TX9
RX9
TX8
RX8
TX7
RX7
TX6
RX6
TX5
RX5
TX4
RX4
TX3
RX3
TX2
RX2
TX1
RX1
CTL
RX0
SDOUT
Data Frame With Early Frame Sync
SCLK
FS(mode1)
SDIN
R/W
zero
A6
A5
A4
A3
A2
A1
A0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SDOUT
zero
zero
zero
zero
zero
zero
zero
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Control Frame With Early Frame Sync
SCLK
FS(mode0)
SDIN
R/W
zero
A6
A5
A4
A3
A2
A1
A0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
zero
zero
zero
zero
zero
zero
zero
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SDOUT
Control Frame With Late Frame Sync
7.2KHz (8KHz)
SCLK
FS
SDIN
SDOUT
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
1
R
0
A
0
A
0
DI
DI
DI
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
0
A
0
RX
DO
DO
DO
RX
Control Frame
Data Frame
Data Frame
Relation Between the Data and Control Frames
Figure 3 -Serial Port Timing Diagram
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
GPIO
The TERIDIAN 73M1903 modem AFE device provides 8 user defined I/O pins. Each pin is programmed
separately as either an input or an output by a bit in a direction register. If the bit in the direction register is
set high, the corresponding pin is an input whose value is read from the GPIO data register. If it is low,
the pin will be treated as an output whose value is set by the GPIO data register.
To avoid unwanted current contention and consumption in the system from the GPIO port before the
GPIO is configured after a reset, the GPIO port I/Os are initialized to a high impedance state. The input
structures are protected from floating inputs, and no output levels are driven by any of the GPIO pins.
The GPIO pins are configured as inputs or outputs when the host controller (or DSP) writes to the GPIO
direction register. The GPIO direction and data registers are initialized to all ones (FFh) upon reset.
GPIO Data (GPIO): Address 02h
Reset State FFh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
Bits in this register will be asserted on the GPIO(7:0) pins if the corresponding direction register bit is a 0.
Reading this address will return data reflecting the values of pins GPIO(7:0).
GPIO Direction (DIR): Address 03h
Reset State FFh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
This register is used to designate the GPIO pins as either inputs or outputs. If the register bit is low, the
corresponding GPIO pin is programmed as an output. If the register bit is a 1, the corresponding pin will
be treated as an input.
ANALOG I/O
Figure 4 on page 12 shows the block diagram of the analog front end. The analog interface circuit uses
differential transmit and receive signals to and from the external circuitry.
The hybrid driver in the TERIDIAN 73M1903 IC is capable of connecting directly, but not limited to, a
transformer-based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s
line coupling transformer, which carries an impedance on the primary side that is typically rated at 600Ω,
depending on the transformer and matching network. The hybrid drivers can also drive high impedance
loads without modification. The class AB behavior of the amplifiers provides load dependent power
consumption.
Page: 11 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
An on-chip band gap voltage is used to provide an internal voltage reference and bias currents for the
analog receive and transmit channels. The reference derived from the bandgap, nominally 1.25 Volts, is
multiplied to 1.36Volts and output at the VREF pin. Several voltage references, nominally 1.25 Volts, are
used in the analog circuits. The band gap and reference circuits are disabled after a chip reset since the
ENFE bit is reset to a default state of zero. When ENFE=0, the band gap voltage and the analog bias
currents are disabled. In this case all of the analog circuits are powered down and draw less than 5 µA of
current.
A clock generator (CKGN) is used to create all of the non-overlapping phase clocks needed for the time
sampled switched-capacitor circuits, ASDM, DAC1, and TLPF. The CKGN input is 2 times the
analog/digital interface sample rate or 3.072MHz clock for Fs=8kHz.
Figure 4 -Analog block diagram
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
CLOCK GENERATION
Crystal Oscillator and Pre-scaler NCO
The crystal oscillator operates over wide choice of crystals (from 9MHz to 27MHz) and it is first input to an
NCO based pre-scaler (divider) prior to being passed onto an on-chip PLL. The intent of the pre-scaler is
to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference
frequency, Fref, for the PLL. The NCO pre-scaler requires a set of three numbers to be entered thru the
serial port (Pseq[7:0], Prst[2:0] and Pdvsr[2:0]. The PLL also requires 3 numbers as for programming;
Ndvsr[6:0], Nseq[7:0], and Nrst[2:0]. The following is a brief description of the registers that control the
NCOs, PLLs, and sample rates for the TERIDIAN 73M1903 IC. The tables show some examples of the
register settings for different clock and sample rates. A more detailed discussion on how these values
are derived can be found in Appendix B.
Control Register (CTRL 8): Address 08h
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Pseq7
Pseq6
Pseq5
Pseq4
Pseq3
Pseq2
Pseq1
Pseq0
This corresponds to the sequence of divisor. If Prst{2:0] =0 this register is ignored.
Control Register (CTRL 9): Address 09h
Reset State 0Ah
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Prst2
Prst1
Prst0
Pdvsr4
Pdvsr3
Pdvsr2
Pdvsr1
Pdvsr0
Prst[2:0] represents the rate at which the sequence register is reset.
Pdvsr[4:0] represents the divisor.
Control Register (CTRL 10): Address 0Ah
Reset State 22h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
FL
BIT 2
BIT 1
BIT 0
Ichp3
Ichp2
Ichp1
Ichp0
Kvco2
Kvco1
Kvco0
.Kvco2:0 represents the magnitude of Kvco associated with the VCO within PLL. This indicates the center
frequency of the VCO when the control voltage is 1.6 Volts and the slope of the VCO freq vs. control
voltage (i.e., Kvco.). FL represents the PLL loop filter settings.
Kvco2
Kvco1
Kvco0
Fvco
Kvco
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
33 MHz
36 MHz
44 MHz
48 MHz
57 MHz
61 MHz
69 MHz
73 MHz
38MHz/v
38MHz/v
40MHz/v
40MHz/v
63MHz/v
63MHz/v
69MHz/v
69MHz/v
Table 3: Kvco vs. Settings at Vc=1.6V, 25°C
Page: 13 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
FL
0
PLLloop Filter settings
R1=32kΩ,C1=100pF,C2=2.5pF
R1=16kΩ, C1=100pF,C2=2.5pF
1
Table 4: PLL Loop Filter Settings
Control Register (CTRL 11): Address 0Bh
Reset State 12h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Ndvsr6
Ndvsr5
Ndvsr4
Ndvsr3
Ndvsr2
Ndvsr1
Ndvsr0
Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored.
Control Register (CTRL 12): Address 0Ch
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Nseq7
Nseq6
Nseq5
Nseq4
Nseq3
Nseq2
Nseq1
Nseq0
Nseq[7:0] represents the divisor sequence.
Control Register (CTRL 13): Address 0Dh
Reset State 48h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Xtal1
Xtal0
reserved reserved unused
Nrst2
Nrst1
Nrst0
Xtal[1:0] : 00 = Xtal osc. bias current at 120µA
01 = Xtal osc. bias current at 180µA
10 = Xtal osc. bias current at 270µA
11 = Xtal osc. bias current at 450µA
If OSCIN is used as a Clock input, “00” setting should be used to save power(=167µA at 27.648MHz).
Nrst[3:0] represents the rate at which the NCO sequence register is reset.
The address ODh must be the last register to be written to when effecting a change in PLL.
Control Register (CTRL 14): Address 0Eh
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Frcvco
PwdnPLL reserved unused
unused
unused
unused
unused
Frcvco = 1 forces VCO as system clock. This is reset upon RST, PwdnPLL = 1 or Enfe = 0. Both
PwdnPLL and Enfe are delayed coming out of digital section to keep PLL alive long enough to transition
the system clock to crystal clock when Frcvco is reset by PwdnPLL or Enfe.
PwdnPll = 1 forces Power down of PLL analog section.
ge: 14 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Addr. 00h bit 7
Addr. 0Eh bit 6
PLL
Enfe
PwdnPLL
0
1
1
X
0
1
PLL Power Off
PLL Power On
PLL Power Off
Table 5: PLL Power Down
Fs
Nnco1
Dnco1
PsSeq(7:0)
PsRst
Nnco2
PllSeq(7:0)
PllRst
Fvco
PPM
(kHz)
=Dnco1 Dnco2
-1
=Dnco2 (Mhz)
-1
7.2
8/125
8/125
8/169
15
11011010
7
5/96
3/64
3/89
19
XXX10000
4
33.177600
0
8.0
15
11011010
7
21
XXXXX100
2
36.864000
0
2.4*8/7*3
=8.22857142858
21
15
15
15
10000000
11011010
11011010
11011010
7
7
7
7
29
22
XXXXX110
XXX10100
2
4
0
4
37.917160*
38.707200
41.472000
44.236800
-3
0
8.4
8/125
8/125
8/125
8/125
5/112
1/24
5/128
7/192
9.0
24 XXXXXXXX
0
9.6
25
XXX11010
0
2.4*10/7*3
=10.2857142857
15
11011010
7
27
X1010110
6
47.396571
0
2.4*8/7*4
7/50
8/107
=10.9714285714
7
7
15
8
X1000000
X1010100
11011010
10000000
6
6
7
7
13
14
10100100
XXX10000
7
4
0
3
50.557500*
51.611538*
55.296000
58.984615*
23
38
0
11.2*
7/52
8/125
8/65
7/80
5/71
1/32
4/71
4/107
12.0
32 XXXXXXXX
12.8*
17
XXXX1110
38
2.4*10/7*4
=13.7142857143
11
15
X1010100
11011010
6
7
0
0
26
38
13
XXXX1110
XXX10100
XXXXXX10
3
4
1
0
63.196875*
66.355200
33.177600
36.864000
23
0
0
0
14.4
8/125
1/10
1/10
4/35
5/192
2/27
1/15
7.2
10 XXXXXXXX
10 XXXXXXXX
8.0
15 XXXXXXXX
2.4*8/7*3
=8.22857142858
8
XXXX1110
3
0
0
0
2/27
4/63
8/135
1/18
13
15
16
XXXXXX10
XXXX1110
11111110
1
3
7
0
37.917257…
38.707200
41.472000
44.236800
0
0
0
0
8.4
1/10
1/10
1/10
10 XXXXXXXX
10 XXXXXXXX
10 XXXXXXXX
9.0
9.6
18 XXXXXXXX
2.4*10/7*3
=10.2857142857
3/28
9
8
XXXXX100
XXXX1110
2
1/18
18 XXXXXXXX
0
47.3965714..
0
2.4*8/7*4
=10.9714285714
4/35
1/10
1/10
1/10
3
0
0
0
1/18
1/21
2/45
1/24
18 XXXXXXXX
21 XXXXXXXX
0
0
1
0
50.5563429..
51.609600
55.296000
58.982400
0
0
0
0
11.2
10 XXXXXXXX
10 XXXXXXXX
10 XXXXXXXX
12
22
XXXXXX10
12.8
24 XXXXXXXX
2.4*10/7*4
=13.7142857143
1/7
1/10
1/4
1/4
1/4
1/4
1/4
2/7
7
XXXXXXXX
0
0
0
0
0
0
0
1/18
1/27
5/72
1/16
5/84
1/18
5/96
5/96
18 XXXXXXXX
27 XXXXXXXX
0
0
4
0
4
0
4
63.19542…
66.355200
33.177600
36.864000
38.707200
41.472000
44.236800
0
0
0
0
0
0
0
14.4
10 XXXXXXXX
7.2
4
4
4
4
4
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
14
XXX10100
8.0
16 XXXXXXXX
16 XXX11110
8.4
9.0
18 XXXXXXXX
9.6
19
XXX10000
2.4*8/7*4
=10.9714285714
6
4
4
4
8
XXXXXX10
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
4
0
0
0
0
19
22
XXX10000
XXX10100
4
4
0
4
4
50.556343
51.609600
55.296000
58.982400
66.355200
0
0
0
0
0
11.2
12
12.8
14.4
1/4
1/4
1/4
1/8
5/112
1/24
5/128
5/288
24 XXXXXXXX
25
57
XXX11010
XXX11010
Table 6: -Examples of NCO Settings
Page: 15 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
7.2
8/125
2/25
15
12
11011010
7
1
5/108
5/96
21
19
XXX11010
XXX10000
4
4
33.1776
36.864
0
0
8.0
XXXXXX10
2.4*8/7*3
=8.22857142858
8.4
9.0
9.6
4/73
18
15
6
XXXX1000
11011010
XXXX1000
11011010
3
7
3
7
6/173
5/126
5/54
28
25
10
28
XX111110
XXX10000
XXX11110
XXX11110
5
4
4
4
37.91781*
38.7072
41.472
15
0
0
0
8/125
4/25
8/125
15
5/144
44.2368
2.4*10/7*3
=10.2857142857
2.4*8/7*4
=10.9714285714
11.2
8/125
15
11011010
7
7/216
30
X1111110
6
47.39657
0
6/59
9
15
6
XX111110
11011010
XXXX1000
11011010
5
7
3
7
7/145
5/168
5/72
20
33
14
38
X1110110
XXX11010
XXX10100
XXX10100
6
4
4
4
50.5569*
51.6096
55.296
12
0
0
0
8/125
4/25
12.0
12.8
8/125
15
5/192
58.9824
2.4*10/7*4
=13.7142857143
14.4
5/61
7/73
8/163
12
10
20
XXX10000
X1010100
10010010
4
6
7
8/257
6/173
3/80
32
28
26
10000000
XX111110
110
7
5
2
63.19672*
66.35616*
33.177914*
21
15
10
7.2
Table 6: -Examples of NCO Settings - continued
Reg Address
Ichp Kvco
Fs(kHz)
7.2
8h 9h Ah Bh Ch Dh* (µA) [2:0]
DA EF 20 13 10 C4
8
0
8.0
DA EF 31 15 04 C2 10
1
2.4*8/7*3
80 F5 41 1D 06 C2 12
1
=8.22857142858
8.4
9.0
9.6
DA EF 31 16 14 C4 10
DA EF 31 18 XX C0 10
DA EF 32 19 1A C4 10
1
1
2
2.4*10/7*3
DA EF 43 1B 54 C6 12
3
3
=10.2857142857
2.4*8/7*4
40 C7 23 0D A4 C7
8
=10.9714285714*
11.2*
54 C7 23 0E 10 C4
DA EF 24 20 XX C0
80 E8 15 11 0E C3
8
8
6
3
4
5
12.0
12.8*
2.4*10/7*4
54 CB 26 1A 0E C3
8
6
6
=13.7142857143
14.4
DA EF 46 26 14 C4 12
Table 7: Clock Generation Register Settings for Fxtal = 27MHz
ge: 16 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Reg Address
Ichp Kvco
Fs(KHz)
7.2
8h 9h Ah Bh Ch Dh* (µA) [2:0]
XX 0A 10 0D 02 C1
6
0
8.0
XX 0A 11 0F XX C0
6
1
2.4*8/7*3
0E 68 11 0D 02 C1
6
1
=8.22857142858
8.4
9.0
9.6
XX 0A 21 0F 0E C3
XX 0A 21 10 FE C7
XX 0A 22 12 XX C0
8
8
8
1
1
2
2.4*10/7*3
04 49 23 12 XX C0
0E 68 23 12 XX C0
8
8
3
3
=10.2857142857
2.4*8/7*4
=10.9714285714
11.2
XX 0A 23 15 XX C0
XX 0A 14 16 02 C1
XX 0A 15 18 XX C0
8
6
6
3
4
5
12
12.8
2.4*10/7*4
XX 07 16 12 XX C0
XX 0A 26 1B XX C0
6
8
6
6
=13.7142857143
14.4
Table 8:Clock Generation Register Settings for Fxtal = 24.576MHz
Reg Address
Ichp Kvco
Fs(KHz)
7.2
8h 9h Ah Bh Ch Dh* (µA) [2:0]
XX 04 20 0E 14 C4
8
0
1
1
1
2
8.0
XX 04 31 10 XX C0 10
XX 04 31 10 1E C4 10
XX 04 31 12 XX C0 10
XX 04 32 13 10 C4 10
8.4
9.0
9.6
2.4*8/7*4
02 23 33 13 10 C4 10
XX 04 33 16 14 C4 10
3
=10.9714285714
11.2
3
4
5
6
12
XX 04 24 18 XX C0
8
12.8
14.4
XX 04 35 19 1A C4 10
XX 08 66 39 1A C4 16
Table 9:Clock Generation Register Settings for Fxtal = 9.216MHz
Page: 17 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Reg Address
Ichp Kvco
Fs(KHz)
7.2
(µA) [2:0]
8h 9h Ah Bh Ch Dh*
DA EF 30 15 1A C4 10
02 2C 31 13 10 C4 10
0
1
8.0
2.4*8/7*3
08 72 41 1C 3E C5 12
1
=8.22857142858
8.4
9.0
9.6
DA EF 41 19 10 C4 12
1
1
2
08 66 11 0A 1E C4
6
DA EF 42 1C 1E C4 12
2.4*10/7*3
DA EF 43 1E 7E C6 12
3
3
=10.2857142857
2.4*8/7*4
3E A9 33 14 76 C6 10
DA EF 53 21 1A C4 14
=10.9714285714
11.2
12
12.8
3
4
5
08 66 14 0E 14 C4
6
DA EF 45 26 14 C4 12
10 8C 46 20 80 C7 12
54 CA 46 1C 3E C5 12
2.4*10/7*4
6
=13.7142857143
14.4
6
Table 10:Clock Generation Register Settings for Fxtal = 24.000MHz
Reg Address
Ichp Kvco
Fs(KHz)
8h 9h Ah Bh Ch Dh* (µA) [2:0]
7.2
0
92 F4 50 1A 06 C2 14
Table 11:Clock Generation Register Settings for Fxtal = 25.35MHz
FrcVco
0
1
System
Clock
2
Loop Filter Control
VCO Locked
Xtal Oscillator
Up
Kd
NCO
Prescaler
Fref
Fvco
R1
C1
VCO
Charge
Pump
Fxtal
C2
PFD
Kvco
Dn
Ichp Control
2
Kvco Control
2
NCO
Figure 5 -Clock Generation
ge: 18 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
MODEM RECEIVER
A differential receive signal applied at the RXAP and RXAN pins or the output signal at TXAP and TXAN
pass through a multiplexer, which selects the inputs to the ADC. In normal mode, RXAP/RXAN are
selected. In analog loopback mode, TXAP/TXAN are selected. The DC bias for the RXAP/RXAN inputs
is supplied from TXAP/TXAN thru the external DAA in normal conditions. (See Appendix) It can be
supplied internally, in the absence of the external DAA, by setting RXPULL bit in Control Register 2.
The output of the multiplexer goes into a second-order continuous time, Sallen-Key, low-pass filter (AAF)
with a 3dB point at approximately 40kHz. The filtered output signal is the input to an analog sigma-delta
modulator (ASDM), clocked at an over sampling frequency of 1.536MHz for Fs = 8kHz, which converts
the analog signal to a serial bit stream with a pulse density that is proportional to the amplitude of the
analog input signal.
There are three gain control bits for the receive path. The RXGAIN bit in control register one results in a
+20dB gain of the receive signal when set to a “1”. This 20dB of gain compensates for the loss through
the DAA while on hook. It is used for Caller ID reception. This gain is realized in the front end of ASDM.
The other gain bits in control register 1, RXG1:0, compensate for differences in loss through the receive
path.
RXG1
RXG0
Receive Gain Setting
0
0
1
1
0
1
0
1
6dB
9dB
12dB
0dB
Table 10: Receive Gain
The output of ASDM is a serial bit stream that feeds three digital sinc3 filters. Each filter has a [sin(x)/x]3
frequency response and provides a 16 bit sample every 288 clock cycles. The filters are synchronized so
that there is one sample available after every 96 analog samples or at a rate of 16kHz for Fs=8kHz. The
output of the sinc3 filter is a 17 bit, two’s compliment number representing the amplitude of the input
signal. The sinc3 filter, by virtue of holding action (for 96 sample period), introduces a droop in the
passband that is later corrected for by a 48 tap FIR filter that follows. The maximum digital word that can
be output from the filter is 0d800h. The minimum word is 12800h.
The output of the sinc3 filter is input to another 48 tap digital FIR filter that provides an amplitude
correction in the passband to the output of the sinc3 filter as well as rejecting noise above Fs/2 or 4kHz for
Fs=8kHZ. The output of the this filter is then decimated by a factor of 2; so, the final output is 16 bit, two’s
compliment samples at a rate of 8 kHz.
Figure 6 and Figure 7depict the sinc3 filter’s frequency response of ASDM along with the 48 tap digital
FIR response that compensates for it and the resulting overall response of the receiver.
Page: 19 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Figure 6 -Overall Receiver Frequency Response
Figure 7 -Rx Path Passband Response
It is important to keep in mind that the receive signal should not exceed 1.16Vpk-diff for proper
performance for Rxg=11 (0dB). In particular, if the input level exceeds a value such that one’s density of
RBS exceeds 99.5%, sinc3 filter output will exceed the maximum input range of the decimation filter and
consequently the data will be corrupted. Also for stability reasons, the receive signal should not exceed
ge: 20 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
1.16Vpk differentially. This value is set at around 65% of the full receive signal of 1.791Vpkdiff at
RXAP/RXAN pins that “would” corresponds to ASDM putting out all ones.
Figure 8 and Figure 9 show the spectrum of 1kHz tone received at RXAP/RXAN of 1.16Vpk-diff and
0.5kHz and 1.0kHz tones of 0.6Vpk-diff each, respectively for Fs=8kHz. Note the effect of FIR
suppressing the noise above 4kHz but at the same time enhancing (in order to compensate for the
passband droop of sinc3 filter) it near the passband edge of 4kHz.
Figure 8 -RXD Spectrum of 1kHz tone
Figure 9 -RXD Spectrum of 0.5kHz, 1kHz, 2kHz, 3kHz and 3.5kHz tones of Equal Amplitudes
Page: 21 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
MODEM TRANSMITTER
The modem transmitter begins with an 48 tap Transmit Interpolation Filter (TIF) that takes in the 16-bit,
two’s compliment numbers (TXD) at SDIN pin at Fs=8kHz rate. It up-samples (interpolates) the data to
16kHz rate rejecting the images at multiples of 8kHz that exist in the original TXD data stream and
outputs 16-bit, two’s compliment numbers to a digital sigma-delta modulator.
interpolation filter is 0.640625 (–3.8679dB) at dc.
The gain of the
The digital sigma-delta modulator (DSDM) takes 16-bit, two’s compliment numbers as input and
generates a 1’s bit stream which feeds into a D to A converter (DAC1). The gain through DSDM is 1.0.
DSDM takes 16-bit, two’s compliment numbers as input and generates a 1’s bit stream that feeds into a D
to A converter (DAC1).
DAC1 consists of a 5-tap FIR filter and a first order switched capacitor low pass filter both operating at
1.536MHz. It possesses nulls at multiples of 384kHz to allow decimation by the succeeding filter.
DAC1’s differential output is fed to a 3rd-order switched-capacitor low pass filter (TLPF). The output of
TLPF drives a continuous time smoothing filter. The sampling nature of the transmitter leads to an
additional filter response that affects the in-band signals. The response is in the form of sin(x)/x and can
be expressed as 20*log [(sin(PI*f/fs))/(PI*f/fs)] where f = signal frequency and fs = sample frequency = 16
kHz. Figure 10 shows the frequency response of the transmit path from TXD to TXAP/TXAN for a dc to
4kHz in-band signal including the effect of this sampling process plus those of DAC1, TLPF and SMFLT.
It is important to note that as TXD is sampled at 8kHz, it be band-limited to 4kHz.
Figure 10 -Frequency Response of TX Path for DC to 4kHz in band Signal
ge: 22 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Transmit Levels
The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF)
has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will
result in a 0.5 (-6dB) gain change in the analog output signal.
The following formula describes the relationship between the transmit code word and the output level at
the transmit pins (TXAP/TXAN):
Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * Vref * TLPFgain * SMFLTgain * FreqFctr
Vout is the differential peak voltage at the TXAP and TXAN pins.
Code is the 16-bit, two’s compliment transmit code word written out by the DSP to the DSDM (via TIF).
The code word falls within a range of ± 32,767. For a sinusoidal waveform, the peak code word should
be used in the formula to obtain the peak output voltage.
DSDMgain is the scaling factor used on the transmit code word to reduce the possibility of saturating the
modulator. This value is set to 0.640625(–3.555821dB) at dc in the 48 tap transmit interpolation filter
(TIF) that precedes DSDM.
dacGAIN is the gain of the DAC. The value dacGAIN is calculated based on capacitor values inside
DAC1 and dacGAIN=8/9=0.8889. The number 32,767 refers to the code word that generates an 82%
“1’s” pulse density at the output of the DSDM. As one can see from the formula, the D to A conversion is
dependent on the level of Vref. Also when DTMFBST bit is set, Vref is increased from 1.36V to 1.586V
to allow higher transmit level or 16.6% increase in gain. This bit is intended for enhancing the DTMF
transmit level and should not be used in data mode.
TLPFgain is the gain of TLPF and nominally equals to 0.00dB or 1.0.
SMFLTgain is the gain of SMFLT and nominally equal to 1.445 or 3.2dB.
When TXBST0 bit is set, the gain is further increased by 1.65dB (1.21) for the total of 4.85 dB. This is to
accommodate greater hybrid insertion loss encountered in some applications.
FreqFctr shows dependency of the entire transmit path on frequency. See Figure 10.
With the transmit code word of +/- 32,767, the nominal differential swing at the transmit pins at dc is:
Vout (V) = 2 * code/32,767 * DSDMgain * dacGAIN * Vref * TLPFgain * SMFLTgain * FreqFctr
= 2 * 32,767/32767 * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.0 = 2.31Vpk diff.
When DTMFBST bit is set, Vout (V) = 1.166 * 2.31= 2.693Vpk diff.
When TXBST0 bit is set, Vout (V) = 1.21 * 2.31= 2.795Vpk diff. (1)
When both DTMFBST and TXBST0 are set to 1, Vout (V) = 2.795 * 1.166 = 3.259Vpk diff.
[1] If not limited by power supply or internal reference.
Page: 23 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Transmit Power - dBm
To calculate the analog output power, the peak voltage must be calculated and the peak to rms ratio
(crest factor) must be known. The following formula can be used to calculate the output power, in dBm
referenced to 600Ω.
Pout (dBm) = 10 * log [ ( Vout (V) / cf )2 / ( 0.001 * 600 ) ]
The following example demonstrates the calculation of the analog output power given a 1.2kHz FSK tone
(sine wave) with a peak code word value of 11,878 sent out by the DSP.
The differential output voltage at TXAP-TXAN will be:
With FreqFctr = 1.02, (See Figure 10)
Vout (V) = 2 * (11,878/32,767) * 0.6640625 * 0.8889 * 1.36 * 1.0 * 1.4454 * 1.02 = 0.841Vpk.
The output signal power will be:
Pout (dBm) = 10 * log [(0.841 / 1.41)2 / (0.001 * 600) ] = - 2.29dBm.
Transmit Type crest factor Max line level
V.90
QAM
DPSK
FSK
4.0
-12dBm
-9dBm
-9dBm
-9dBm
-5.7dBm
2.31
1.81
1.41
1.99
DTMF
Table 11: -Peak to RMS ratios for various modulation types
Control Register (CTRL1): Address 00h
Reset State 08h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
RXG1
BIT 1
RXG0
BIT 0
RXGAIN
ENFE
unused
DTMFBST TXBST0 TXDIS
ENFE
1 = Enable the digital filters and analog front end.
0 = Disable the analog blocks shut off the clocks to the digital and analog receive/transmit
circuits.
DTMFBST 1 = Add a gain of 0.83dB(10%) to the transmitter; also the common mode voltage of the
transmit path is increased to 1.375V. This is intended for enhancing DTMF transmit
power only and should not be used in data mode.
0 = No gain is added
TXBST0
1 = A gain of 1.5dB(18.9%) is added to the transmitter
0 = The gain of the transmitter is nominal
ge: 24 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
TXDIS
1 = Tri-state the TXAP and TXAN pins, provides a bias of VBG into 80 kꢀ for each output
pin
RXG1:0
RXGAIN
These bits control the receive gain as indicated in Table 8.
1 = Increase the gain of the receiver by 20 dB.
Control Register (CTRL2): Address 01h
Reset State 00h
BIT 7
BIT 6
BIT 5
ANALB
BIT 4
INTLB
BIT 3
BIT 2
BIT 1
BIT 0
HC
TMEN
DIGLB
CkoutEn RXPULL SPOS
TMEN
DIGLB
1 =
1 =
Enable test modes.
Tie the serial bit stream from the digital transmit filter output to the digital receive filter
input. DIGITAL LOOPBACK
ANALB
INTLB
CkoutEn
RXPULL
SPOS
HC
1 =
1 =
1 =
1 =
Tie the analog output of the transmitter to the analog input of the receiver. ANALOG
LOOPBACK
Tie the digital serial bit stream from the analog receiver output to the analog
transmitter input. INTERNAL LOOPBACK
Enable the CLKOUT output; 0 = CLKOUT tri-stated. For test purposes only; do not
use in normal operation.
Pulls DC Bias to RXAP/RXAN pins, thru 100Kohm each, to VREF, to be used in
testing Rx path.
0 =
1 =
0 =
No DC Bias to RXAP/RXAN pins
Control frames occur after one quarter of the time between data frames has elapsed.
Control frames occur half way between data frames.
1 =
0 =
FSB is under hardware control, bit 0 of data frames on SDIN is bit 0 of the transmit
word and control frames happen automatically after every data frame.
FSB is under software control, bit 0 of data frames on SDIN is a control frame request
bit and control frames happen only on request.
Revision Register: Address 06h
Reset State 30h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Rev3
Rev2
Rev1
Rev0
Unused
reserved reserved reserved
Bits 7-4 contain the revision level of the TERIDIAN 73M1903 device. The rest of this register is for chip
development purposes only and is not intended for customer use. Do not write to shaded locations.
Page: 25 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
TEST MODES
There are two loop back test modes that affect the configuration of the analog front end. The internal
loop back mode connects the serial bit stream generated by the analog receiver to the input of the analog
transmitter. This loop back mode is similar to a remote analog loop back mode and can be used to
evaluate the operation of the analog circuits. When using this loop back mode, the TXAN/TXAP pins
should not be externally coupled to the RXAP/RXAN pins. Set bit 4 (INTLB) in register 1h (CTRL2) to
enter this loop back mode.
The second loop back test mode is the external loop back mode, or local analog loop back mode. In this
mode, the analog transmitter outputs are fed back into the input of the analog receiver. Set bit 5 (ANALB)
in register 1h (CTRL2) to enter this loop back mode. In this mode, TBS must be kept to below a value
that corresponds to less than 1.16V/2.31V x -6dB = 25% of the full scale code of +/- 32768 at TXD in
order to ensure that the receiver is not overdriven beyond the maximum of 1.16Vpkpk diff for
Rxg=11(0dB) setting. See Table 18 on page 33 for the maximum allowed transmit levels. Check the
transmitted data against received data via serial interface. This tests the functionality of essentially all
blocks, both digital and analog, of the chip.
There is a third loopback mode that bypasses the analog circuits entirely. Digital loop back forces the
transmitter digital serial bit stream (from DSDM) to be routed into the digital receiver’s sinc3 filters. Set bit
6 (DIGLB) in register 1h (CTRL2) to enter this loop back mode.
POWER SAVING MODES
The 73M1903 has only one power conservation mode. When the ENFE, bit 7 in register 0h, is zero the
clocks to the filters and the analog are turned off. The transmit pins output a nominal 80kꢀ impedance.
The clock to the serial port is running and the GPIO and other registers can be read or updated.
ge: 26 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation outside these rating limits may cause permanent damage to this device.
PARAMETER
RATING
Supply Voltage
-0.5V to +4.0V
-0.5V to 6.0V
-0.5V to VDD + 0.5V
Pin Input Voltage (except OSCIN)
Pin Input Voltage (OSCIN)
RECOMMENDED OPERATING CONDITIONS
PARAMETER
RATING
Supply Voltage (VDD) with respect to VSS
Oscillator Frequency
3.0V to 3.6V
24.576 MHz ±100ppm
-40C to +85°C
Operating Temperature
Page: 27 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
DIGITAL SPECIFICATIONS
DC CHARACTERISTICS
PARAMETER
Condition
MIN
NOM
MAX
UNIT
Input Low Voltage
Input High Voltage
(Except OSCIN)
Input High Voltage
OSCIN
VIL
-0.5
0.2 * VDD
V
VIH1
0.7 VDD
5.5
V
VIH2
0.7 VDD
VDD + 0.5
V
Output Low Voltage
(Except OSCOUT, FS, VOL
SCLK, SDOUT)
IOL = 4mA
0.45
V
Output Low Voltage
VOLOSC
IOL = 3.0mA
IOL = 1mA
0.7
V
V
OSCOUT
Output Low Voltage
FS,SCLK,SDOUT
Output High Voltage
VOL
0.45
(Except OSCOUT, FS, VOH
SCLK, SDOUT)
IOH = -4mA
VDD - 0.45
V
Output High Voltage
VOHOSC
IOH =-3.0mA
IOH = -1mA
VDD - 0.9
V
V
OSCOUT
Output High Voltage
FS,SCLK,SDOUT
Input Low Leakage
Current
VOH
IIL1
VDD - 0.45
VSS < Vin < VIL1
1
µA
(Except OSCIN)
Input High Leakage
Current (Except
OSCIN)
IIH1
IIL2
IIH2
VIH1 < Vin < 5.5
VSS < Vin < VIL2
VIH2 < Vin < VDD
1
µA
µA
µA
Input Leakage Current
OSCIN
1
1
30
30
Input High Leakage
Current
OSCIN
IDD current at 3.0V – 3.6V Nominal at 3.3V
IDD Total current
IDD Total current
IDD Total current
Fs=8hz,
IDD
IDD
IDD
IDD
9
12.0
13.4
14.5
2.5
mA
mA
mA
mA
Xtal=27Mh
Fs=11.2hz,
Xtal=27Mh
Fs=14.4hz,
Xtal=27Mh
10.3
11.8
2
IDD Total current
ENFE=0
ge: 28 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
AC TIMING
PARAMETER
MIN
NOM
MAX
-
UNIT
ns
SCLK Period (Tsclk) (Fs=8kHz)
SCLK to FSB Delay (td1) – mode1
SCLK to FSB Delay (td2) – mode1
SCLK to SDOUT Delay (td3) (With 10pf load)
Setup Time SDIN to SCLK (tsu)
Hold Time SDIN to SCLK (th)
-
-
1/2.048MHz
-
--
-
20
20
20
-
-
20
20
ns
-
-
ns
ns
15
10
-
-
ns
-
ns
SCLK to FSB Delay (td4) – mode0
SCLK to FSB Delay (td5) – mode0
-
ns
-
-
ns
Table 12: -Serial I/F Timing
td1
td2
Tsclk
SCLK
FS
(mode1)
RX15
RX14
TX14
RX1
RX0
TX0
SDOut
SDIN
td3
tsu
TX1
TX15
th
FS
(mode0)
td5
td4
Figure 11 -Serial Port Data Timing
.
Page: 29 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
ANALOG SPECIFICATIONS
DC SPECIFICATIONS
Vref should be connected to an external bypass capacitor with a minimum value of 0.1uF. This pin is not
intended for any other external use.
Parameter
Test Condition
Min
Nom
1.36
-86
Max
-80
Units
V
dBm600
dB
Vref
VDD= 3.0V - 3.6V.
Vref Noise
Vref PSRR
300Hz-3.3kHz
300Hz-30kHz
40*
Table 13: -Reference Voltage Specifications
AC SPECIFICATIONS
The table below shows the maximum transmit levels that the output drivers can deliver before distortion
through the DAA starts to become significant. The loss though the DAA transmit path is assumed to be 7
dB. The signals presented at TXAP and TXAN are symmetrical. The transmit levels can be increased by
setting either TXBST0 (+1.5dB) or/and DTMFBST (+0.83dB) for the combined total gain of 2.33dB.
These can be used where higher-level DTMF tones are required.
MAXIMUM TRANSMIT LEVELS
Maximum
differential line
level (dBm0)
Maximum single-
ended level at
Single-ended rms Single-ended
Voltage at TXA Peak Voltage at
peak to
TXA pins (dBm) rms ratio
pins (V)
TXA pins (V)
Transmit Type
VPA=2.7V to 3.6V; All rms and peak voltages are relative to Vref
-12.0
-11.0
4
0.2175
0.377
0.87
0.87
V.90
QAM
-7.3
-6.3
2.31
DPSK
-5.1
-3.0
-4.1
-2.0
1.81
0.481
0.87
FSK
1.41
0.617
0.87
DTMF (high tone)
DTMF (low tone)
-7.8
-9.8
-6.8
-8.8
1.41
1.41
0.354
0.283
0.500
0.400
Table 14: -Maximum Transmit Levels
ge: 30 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
PERFORMANCE
Receiver
Parameter
Test Conditions
Measured at RXAP/N relative to Vref
RXPULL=HI
Min
Nom
Max
Units
kꢀ
Input Impedance
230
Measured at RXAP/N relative to Vref
RXPULL=LO
1.0
Mꢀ
Receive Gain
Boost
Rxgain = 1; 1kHz; RXAP/N=0.116Vpk-diff
Gain Measured relative to Rxgain=0
Rxgain=1 for Fs=8Khz
17.0
16.2
15.7
18.5
17.4
17.2
20.0
18.7
18.7
dB
dB
dB
Rxgain=1 for Fs=12Khz
Rxgain=1 for Fs=14.4Khz
THD = 2nd and 3rd harmonic.
Rxgain=1
Total Harmonic
Distortion (THD)
RXG Gain
64
70
Gain Measured relative to RXG[1:0]=11
(0dB) @1 KHz
RXG[1:0]=00
5.8
8.8
6
9
6.2
9.2
dB
dB
dB
RXG[1:0]=01
RXG[1:0]=10
11.8
12
12.2
Passband Gain
Input 1.16Vpk-diff at RXA. Measure gain at
0.5kHz, and 2KHz. Normalized to 1khz.
Gain at 0.5kHz
-0.29
-0.067
-30
-0.042
0.000
0.183
0.21
0.43
30
dB
dB
dB
Gain at 1kHz (Normalized)
Gain at 2.0kHz
Input offset
Short RXAP to RXAN. Measure input
voltage relative to Vref
0
mV
Normalized to VBG=1.25V.
Includes the effect of AAF(-0.4dB) with
Bit1,0 of CTRL2=0,0.
Sigma-Delta ADC
Modulation gain
41
µV/bit
Vpk-diff
Maximum Analog Peak voltage measured differentially
Signal Level at
RXAP/RXAN
across RXAP/RXAN.
1.16
-80
1kHz 1.16Vpk-diff at RXA with Rxg=11
THD = 2nd and 3rd harmonic.
Total Harmonic
Distortion (THD)
80
85
dB
Transmit V.22bis low band; FFT run on
ADC samples. Noise in 0 to 4kHz band
0dBm 1000Hz sine wave at TXAP; FFT
on Rx ADC samples, 1st four harmonics
Reflected back to receiver inputs.
Noise
-85
dBm
Crosstalk
-100
dB
Note: RXG[1:0] and RXGAIN are assumed to have settings of ‘0’ unless they are specified otherwise.
Table 15: -Receiver Performance Specifications
Page: 31 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Transmitter
Parameter
Test Condition
Min
Nom
Max
Units
DAC gain
Code word of ± 32,767 @1kHz;
(Transmit Path Gain)
TXBST0=0; DTMFBST=0
70
µv/bit
mV
mV
dB
DC offset –Differential Across TXAP and TXAN for
Mode
DAC input = 0
-100
-80
100
80
DC offset -Common
Mode
Average of TXAP and TXAN for DAC
input = 0; relative to VREF
Code word of ± 32,767 @1kHz;
TXBST0 Gain
relative to TXBST0=0; TXBST1=0
1.65
Code word of ± 32,767 @1kHz;
DTMFBST Gain
relative to TXBST0=0; TXBST1=0
1.335
dB
Code word of ± 32,767 @1kHz;
relative to TXBST0=0;TXBST1=0
THD = 2nd and 3rd harmonic.
Code word of ± ( 32,767*0.8) @1kHz;
relative to TXBST0=0;TXBST1=0
THD = 2nd and 3rd harmonic.
Code word of ± ( 32,767*0.9) @1kHz;
relative to TXBST0=1;TXBST1=1
THD = 2nd and 3rd harmonic.
Code word of ± 32,767 @1kHz;
relative to TXBST0=1;DTMFBST=1
THD = 2nd and 3rd harmonic
Total Harmonic
Distortion (THD)
-75
-80
-60
-85
-85
-70
-70
dB
dB
dB
1200ꢀ Resistor
across TNAN/TXAP
At output (TXAP-TXAN): DTMF
1.0kHz, 1.2kHz sine waves, summed
2.0Vpk (-2dBm tone summed with 0dBm
tone)
dB
below
low
Intermod Distortion
70
Refer to TBR 21 specifications for
description of complete requirements.
tone
Idle Channel Noise
PSRR
200Hz - 4.0kHz
110
µV
dB
dB
-30 dBm signal at VPA
40
300Hz – 30kHz
Passband Ripple
300Hz - 3.2kHz
-0.125
0.125
Code word of ± 32,767 @1kHz.
Measure gain at 0.5kHz, and 2KHz
relative to 1kHz.
Transmit Gain
Flatness
Gain at 0.5kHz
0.17
0
dB
dB
dB
dB
Gain at 1kHz (Normalized)
Gain at 2.0kHz
0.193
-0.12
Gain at 3.3kHz
Table 16: -Transmitter Performance Specifications
ge: 32 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Parameter
Test Condition
Min
Nom
Max
Units
Txap/n output
impedance
TXDIS =1.
Measure impedance differentially
between TXAP and TXAN.
differentially
(TXDIS=1)
160
0
kꢀ
Txap/n common
output offset
(TXDIS=1)
TXDIS=1
Short Txap and Txan. Measure the
voltage respect to Vbg
-20
20
mV
Note: TXBST0 and DTMFBS are assumed have setting 0’s unless they are specified otherwise.
Table 17: -Transmitter Performance Specifications (continued)
Page: 33 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
PACKAGE OPTIONS
(Drawings not to scale)
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GPIO5
VND
VPD
VND
VPD
1
2
3
4
5
6
7
8
GPIO5
24
23
22
21
20
19
18
17
GPIO4
VND
GPIO4
VND
N/C
GPIO0
GPIO1
GPIO2
GPIO3
FS
GPIO0
GPIO1
NC
TERIDIAN
73M1903
TERIDIAN
73M1903
GPIO2
GPIO3
FS
VPPLL
VPPLL
OSCIN
OSCIN
OSCOUT
OSCOUT
VNPLL
SCLK
SCLK
VNPLL
73M1903 QFN 32
73M1903 TQFP 32
Pin
Name
Pin
Name
1
2
VND
VPD
GPIO0
GPIO1
GPIO2
GPIO3
FSB
SCLK
RST
VPA
TXAN
TXAP
VREF
RXAN
RXAP
VNA
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VNPLL
OSCOUT
OSCIN
VPPLL
CLKOUT
VND
GPIO4
GPIO5
VPD
N/C
TYPE
SckMode
SDIN
GPIO6
GPIO7
SDOUT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ge: 34 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
MECHANICAL DRAWINGS
8.7
9.3
INDEX
1
6.8
7.2
0.0
0.20
0.60 Typ.
1.0
1.2
0.34
0.46
0.80 Typ.
32 lead TQFP
Controlling dimensions in mm
Page: 35 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
MECHANICAL DRAWINGS cont.
12º MAX
0.65 NOM./ 0.7MAX.
0.85 NOM./ 0.9MAX.
0.00 / 0.005
0.20 REF.
SIDE VIEW
SEATING
PLANE
All Dimensions
in mm
5
4.75
2.95 / 3.25
0.18 / 0.3
2.5
2.375
1.475 / 1.625
1
2
3
1
2
3
0.45
0.25 MIN.
0.3 / 0.5
0.5
BOTTOM VIEW
TOP VIEW
32 lead QFN
Controlling dimensions in mm
ge: 36 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
APPENDIX A
73M1903 DAA Resistor Calculation Guide
The following procedure can be used to approximate the component values for the DAA. The optimal
values will be somewhat different due to the effects of the reactive components in the DAA (this is a DC
approximation). Simulations with the reactive components accurately modeled will yield optimal values.
The procedures for calculating the component values in the DAA are as follows. First set up R1. The
DAA should be designed to reflect 600 ꢀ when looking in at TIP/RING. If the transformer is 1 to 1, the
holding coil and ring detect circuit are high impedance, Cblock is a high value so in the frequency band of
interest it is negligible, the sum of R2 and R3 is much greater than R1, and the output impedance of the
drivers driving TXAP/TXAN are low then:
Rin 2.R1 RW Rohswitch 2.Rbead
RW is the sum of the winding resistance of both sides of the transformer. Measure each side of the
transformer with an Ohmmeter and sum them.
Rohswitch is the on resistance of the Off Hook Switch. Mechanical Relay switches can be ignored, but
Solid State Relays sometimes have an appreciable on resistance.
Rbead is the DC resistance of whatever series RF blocking devices may be in the design.
For Rin equal to 600 ꢀ:
600 RW Rohswitch 2.Rbead
R1
2
To maximize THL (Trans-Hybrid Loss), or to minimize the amount of transmit signal that shows up back
on the Receive pins. The RXAP/RXAN pins get their DC bias from the TXAP/TXAN pins. By capacitively
coupling the R3 resistors with the C1 caps, the DC offset can be minimized from the TXAP/TXAN to the
RXAP/RXAN because the DC offset will be divided by the ratio of the R1 resistors to the winding
resistance on the one side of the transformer.
Page: 37 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
Next make the sum of R2 + R3 much higher than 600 ꢀ. Make sure they are lower than the input
impedance of the RXAP/RXAN pins; otherwise they can move the frequency response of the input filter.
So let R2 + R3 = 100K.
100 K
R3
Rwtot 600
1
1200
where
Rwtot RW Rohswitch 2.Rbead
R2 100 K R3
Use 1% resistors for R1, R2, and R3
To select the value for C1, make the zero at around 10Hz.
1
10
2.
C1
π
.100 K.C1
1
2. .100 K.10
π
C1 0.15 uF
The blocking cap Cblock should also have the same frequency response, but due to the low impedance,
its value will be much higher, usually requiring a polarized cap. A blocking cap may also be needed on
the modem side of the transformer if the DC offset current of the transmit pins will exceed the current
rating of the transformer.
1
Cblock
2. .600.10
Cblock 27 uF
π
If you are using a Wet transformer design, as in the following figure:
ge: 38 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
The only difference is that the blocking capacitor, Cblock, it is removed. All other equations still hold true.
Trans-Hybrid Loss (THL)
Trans-Hybrid Loss is by definition the loss of transmit signal from Tip/Ring to the receive inputs on the
modem IC. This definition is only valid when driving a specific phone line impedance. In reality, phone
line impedances are never perfect, so this definition isn’t of much help. Instead, as an alternate definition
that helps in analysis for this modem design, THL is the loss from the transmit pins to the receive pins. In
this definition the worst-case THL from the transmit pins to the Receive pins is 10.8dB. An insertion loss
of 7dB is assumed accounting for losses due to switch, bridge and transformer.
Page: 39 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
APPENDIX B
Crystal Oscillator
The crystal oscillator is designed to operate over wide choice of crystals (from 9MHz to 27MHz). The
crystal oscillator output is input to an NCO based pre-scaler (divider) prior to being passed onto an on-
chip PLL. The intent of the pre-scaler is to convert the crystal oscillator frequency, Fxtal, to a convenient
frequency to be used as a reference frequency, Fref, for the PLL. A set of three numbers– Pdvsr (5 bit),
Prst (3 bit) and Pseq (8 bit) must be entered thru the serial port as follows:
Pdvsr = Integer [Fref/Fxtal];
Prst = Denominator of the ratio (Fref/Fxtal) minus 1 when it is expressed as a ratio of two smallest
integers = Nnco1/Dnco1;
Pseq = Divide Sequence
overflow
Fxtal
Fref
Counter
count ctrl
Pdvsr
Pdvsr +1
mux
Sequence
Register
Sequence
Counter
Rst
Prst[2:0]
Figure B-1 NCO block diagram
Pseq[7:0]
Please note that in all cases, pre-scaler should be designed such that pre-scaler output frequency, Fref,
is in the range of 2 ~ 4MHz.
In the first example below, the exact divide ratio required is Fxtal/Fref = 15.625 =125/8. If a divide
sequence of {÷16,÷16,÷15,÷16,÷16,÷15,÷16,÷15} is repeated, the effective divide ratio would be exactly
15.625. Consequently, Pdvsr of 15, the length of the repeating pattern, Prst = 8 –1 =7, and the pattern,
{1,1,0,1,1,0,1,0}, where 0 means Pdvsr, or ÷15, and 1 means Pdvsr +1, or ÷16 must be entered as below.
Example 1: Fxtal = 27MHz, Fref = 1.728MHz.
Pdvsr = Integer [Fxtal/Fref] = 15 =0Fh
Prst[2:0] = 8 – 1 = 7 from Fxtal/Fref = 15.625 =125/8;
Pseq = ÷16,÷16,÷15,÷16,÷16,÷15,÷16,÷15 => {1,1,0,1,1,0,1,0} =DAh.
In the second example, Fxtal/Fref =4.0. This is a constant divide by 4. Thus Pdvsr is 4, Prst = 1 –1 =0
and Pseq = {x,x,x,x,x,x,x,x).
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Example 2: Fxtal = 18.432MHz, Fref = 2.304 MHz.
Pdvsr = Integer [Fxtal/Fref] = 8 = 8h;
Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 18.432/2.304 = 8/1;
Pseq = {x,x,x,x,x,x,x,x} = xxh
Example 3: Fxtal = 24.576MHz, Fref = 2.4576MHz.
Pdvsr = Integer [ Fxtal/Fref] = 10 = Ah;
Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/2.4576 = 10/1;
Pseq = {x,x,x,x,x,x,x,x} = xxh
It is also important to note that when Fxtal/Fref is an integer the output of the pre-scaler is a straight
frequency divider (example 2). As such there will be no jitter generated at Fref. However if Fxtal/Fref is
a fractional number, Fref, at the output of the pre-scaler NCO would be exact only in an average sense
(example 1) and there will be a certain amount of fixed pattern (repeating) jitter associated with Fref which
can be filtered out by the PLL that follows by appropriately programming the PLL. It is important to note,
however, that the fixed pattern jitter does not degrade the performance of the sigma delta modulators so
long as its frequency is >> 4kHz.
PLL
NCO
Up
Kd
Prescaler
Fref
Divide
by 2/1
R1
C1
VCO
Charge
Pump
C2
PFD
Kvco
Dn
Ichp Control
3
Kvco Control
3
NCO
Figure B-2 PLL Block Diagram
1903B has a built in PLL circuit to allow an operation over wide range of Fs. It is of a conventional design
with the exception of an NCO based feedback divider. (See Figure B-2: PLL Block Diagram).
The architecture of the 73M1903 dictates that the PLL output frequency, Fvco, be related to the sampling
rate, Fs, by Fvco = 2 x 2304 x Fs. The NCO must function as a divider whose divide ratio equals
Fref/Fvco.
Just as in the NCO pre-scaler, a set of three numbers– Ndvsr ( 7 bits ), Nrst ( 3 bits ) and Nseq ( 8 bits )
must be entered thru a serial port to effect this divide:
Ndvsr = Integer [ Fref/Fxtal ] ;
Nrst = Denominator of the ratio (Fvco/Fref), Dnco1, minus 1, when it is expressed as a ratio of two
smallest integers = Nnco1/Dnco1;
Nseq = Divide Sequence
Example 1: Fs = 7.2kHz or Fvco = 2 x 2304 x 7.2kHz =33.1776MHz, Fref = 1.728MHz.
Ndvsr = Integer [ Fvco/Fref ] = 19
Nrst = 5 – 1 = 4 from Fvco/Fref = 19.2 = 96/5;
Nseq = ÷19, ÷19, ÷19, ÷19, ÷20 => {0,0,0,0,1} =xxx00001 = 01h.
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Example 2: Fs = 8.0kHz or Fvco = 2 x 2304 x 8kHz =36.864MHz, Fref = 2.304MHz.
Ndvsr = Integer [Fvco/Fref] = 16 = 10h;
Nrst= 1-1 = 0 from Fvco/Fref = 16/1;
Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example 3: Fs = 9.6kHz or Fvco = 2 x 2304 x 9.6kHz =44.2368MHz, Fref = 2.4576MHz.
Ndvsr = Integer [Fvco/Fref] = 18 = 16h;
Nrst= 1-1 = 0 from Fvco/Fref = 18/1;
Nseq = {x,x,x,x,x,x,x,x} = xxh.
It is important to note that in general the NCO based feedback divider will generate a fixed jitter pattern
whose frequency components are at Fref/Accreset2 and its integer multiples. The overall jitter frequency
will be a nonlinear combination of jitters from both pre-scaler and PLL NCO. The fundamental frequency
component of this jitter is at Fref/Prst/Nrst. The PLL parameters should be selected to remove this jitter.
Three separate controls are provided to fine tune the PLL as shown in the following sections.
To ensure quick settling of PLL, a feature was designed into the 73M1903 where Ichp is kept at a higher
value until Lokdet becomes active or Frcvco bit is set to 1, whichever occurs first. Thus PLL is
guaranteed to have the settling time of less than one Frame Synch period after a new set of NCO
parameters had been written to the appropriate registers. The serial port register writes for a particular
sample rate should be done in sequence starting from register 08h ending in register 0Dh. 0Dh register
should be the last one to be written to. This will be followed by a write to the next register in sequence
(0Eh) to force the transition of Sysclk from Xtal to Pllclk.
Upon the system reset, the system clock is reset to Fxtal/9. The system clock will remain at Fxtal/9 until
the Host forces the transition, but no sooner the second Frame Synch period after the write to 0Dh.
When this happens, the system clock will transition to PLLclk without any glitches thru a specially
designed deglitch MUX.
Examples of NCO settings
Example 1:
Crystal Frequency = 24.576MHz; Desired Sampling Rate, Fs = 13.714kHz(=2.4kHz x 10/7 x 4)
Step 1. First compute the required VCO frequency, Fvco, corresponding to
Fs = 2.4kHz x 10/7 x 4 = 13.714kHz, or
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 10/7 x 4 = 63.19543MHz.
Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers.
This is initially given by :
2• 2304• 2.4kHz•10/7• 4
.
Fvco/ Fxtal =
24.576MHz
After a few rounds of simplification this ratio reduces to:
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DATA SHEET
18
7
Nnco1
1
7
18
1
Fvco / Fxtal
=
= (
) • (
)
1
Dnco1
7
=
=
Nnco2
1
Dnco2
18
, where Nnco1 and Nnco2 must be < or equal to 8.
The ratio, Nnco1/Dnco1 = 1/7, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 =
1/18 for the NCO in the PLL.
Prescaler NCO: From Nnco1/Dnco1 = 1/7,
Pdvsr = Integer [ Dnco1/Nnco1 ] = 7;
Prst[2:0] = Nnco1 – 1 = 0; this means NO fractional divide. It always does ÷7. Thus Pseq becomes
“don’t care” and is ignored.
Pseq = {x,x,x,x,x,x,x,x} = xxh.
PLL NCO: From Nnco2/Dnco2 = 1/18,
Ndvsr = Integer [ Dnco2/Nnco2 ] = 18;
Nrst[2:0] = Nnco2 – 1 = 0; this means NO fractional divide. It always does ÷18. Thus Pseq becomes
“don’t care” and is ignored.
Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example 2:
Crystal Frequency = 24.576MHz; Desired Sampling Rate, Fs = 10.971kHz=2.4kHz x 8/7 x4
Step 1. First compute the required VCO frequency, Fvco, corresponding to
Fs = 2.4kHz x 8/7 x 4 =10.971kHz.
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 8/7 x 4 = 50.55634MHz.
Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers.
This is initially given by :
2• 2304• 2.4kHz•8/7• 4
.
Fvco/ Fxtal
=
24.576MHz
After a few rounds of simplification this ratio reduces to:
4
35
18
1
Fvco / Fxtal = (
) • (
)
Nnco1
4
Dnco1
35
=
=
Nnco2
1
Dnco2
18
, where Nnco1 and Nnco2 must be < or equal to 8.
The ratio, Nnco1/Dnco1 = 4/35, is used to form a divide ratio for the NCO in pre-scaler and Nnco2/Dnco2
=1/18 for the NCO in the PLL.
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Modem Analog Front End
DATA SHEET
Pre-scaler NCO: From Nnco1/Dnco1 = 4/35,
Pdvsr = Integer [ Dnco1/Nnco1 ] = 8;
Prst[2:0] = Nnco1 – 1 = 3;
Dnco1/Nnco1 = 35/4 = 8.75 suggests a divide sequence of {÷9,÷9,÷9,÷8}, or
Pseq = {x,x,x,x,1,1,1,0} = xDh.
PLL NCO: From Nnco2/Dnco2 = 1/18,
Ndvsr = Integer [ Dnco2/Nnco2 ] = 18;
Nrst[2:0] = Nnco2 – 1 = 0; this means NO fractional divide. It always does ÷18. Thus Pseq becomes
“don’t care”.
Nseq = {x,x,x,x,x,x,x,x} = xxh.
Example3:
Crystal Frequency = 27MHz; Desired Sampling Rate, Fs = 7.2kHz
Step 1. First compute the required VCO frequency, Fvco, corresponding to
Fs = 2.4kHz x 3 = 7.2kHz.
Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4kHz x 3 = 33.1776MHz.
Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers.
This is initially given by :
2• 2304• 2.4kHz•3
.
Fvco/ Fxtal =
27MHz
After a few rounds of simplification this reduces to:
8
125
96
5
Fvco / Fxtal = (
) • (
)
.
Nnco1
8
Dnco1
125
=
=
Nnco2
5
Dnco2
96
The two ratios are not unique and many other possibilities exist. But for this particular application, they
are found to be the best set of choices within the constraints of Prst and Nrst allowed. (Nnco1, Nnco2
must be less than or equal to 8.)
The ratio, Nnco1/Dnco1 = 8/125, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2
=5/96 for the NCO in the PLL.
Pre-scaler NCO: From Nnco1/Dnco1 = 8/125,
Pdvsr = Integer [ Dnco1/Nnco1 ] = 15;
Prst[2:0] = Nnco1 – 1 = 7;
Dnco1/Nnco1 = 125/8 = 15.625 suggests a divide sequence of {÷16,÷16,÷15,÷16,÷16,÷15,÷16,÷15}, or
Pseq = {1,1,0,1,1,0,1,0} = DAh.
PLL NCO: From Nnco2/Dnco2 = 5/96,
Ndvsr = Integer [ Dnco2/Nnco2 ] = 19;
Nrst[2:0] = Nnco2 – 1 = 4;
Dnco2/Nnco2 = 19.2 suggests a divide sequence of {÷19, ÷19, ÷19, ÷19, ÷20}, or
Nseq = {x,x,x,0,0,0,0,1} = x1h.
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© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
73M1903
Modem Analog Front End
DATA SHEET
ORDERING INFORMATION
PART DESCRIPTION
73M1903 32-Lead QFN Lead Free
73M1903 32-Lead QFN Standard
ORDER NUMBER
73M1903-IM/F
73M1903-IM
73M1903 32-Lead Thin Quad Flat Pack Lead Free
73M1903-IGV/F
73M1903 32-Lead Thin Quad Flat Pack Standard
73M1903-IGV
Data Sheet: This Data Sheet is proprietary to TERIDIAN Semiconductor Corporation (TSC) and sets forth design goals for the described
product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and
when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,
including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves
the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is
current before placing orders. TSC assumes no liability for applications assistance.
TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
Revision 1.4 09/14/06
© 2006 TERIDIAN Semiconductor Corporation
Page: 45 of 45
© 2005 TERIDIAN Semiconductor Corporation
Rev 1.4
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