U3280M-MFB [TEMIC]
Telecom Circuit, 1-Func, PDSO16, SSO-16;
| 型号： | U3280M-MFB |
| 厂家： | 
TEMIC SEMICONDUCTORS |
| 描述： | Telecom Circuit, 1-Func, PDSO16, SSO-16 电信 光电二极管 电信集成电路 |
| 文件： | 总17页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Contactless power supply and communication interface
• Up to 10 kbaud data rate (R/O)
• Power management for contactless- and battery power supply
• Frequency range 100 to 150 kHz
• 32 x 16-bit EEPROM
• Two wire serial interface
• Shift register supported Biphase and Manchester modulator stage
• Reset I/O line
• Field clock extractor
• Field and gap detection output for wake up and data reception
• Field modulator with energy-saving damping stage
Transponder
Interface for
Microcontroller
Applications
• Overview
- Access control
- Telemetry
- Wireless sensors
Par example:
U3280M
• Wireless passive access and active alarm control for protection of valuables
• Contactless position sensors for alignments of machines
• Contactless status verification and/ or data readout from sensors
Description
The U3280M IC is a transponder interface which enables contactless ID systems,
remote control systems, tag and sensor applications. It is able to supply a microcon-
troller with power from an RF field via a LC-resonant circuit and it enables the
controller for contactless bidirectional data communication via this RF field. It includes
a power management which handles switching between magnetic field and battery
power supply. To store permanent data like identifiercode and configuration data the
U3280M includes a 512-bit EEPROM with an serial interface .
Block Diagram
Figure 1.
VBatt
U3280M Transponder interface
Sensors, keys, displays, actuators
Energy
VField
regulator
Power
management
NRST
VDD
Damping
stage
Coil 1
Coil 2
512-bit
EEPROM
memory
Rectifier
Low power
microcontroller
SDA
SCL
Serial
interface
Field/gap
detect
Biphase
modulator
Clock
extractor
Data
>_1
VSS
MOD
NGAP
FC
Transmit data
Receive data/ field detected
Field clock
Rev. A4, 11-Dec-01
1 (17)
Ordering Information
Extended Type Number
Package
Remarks
U3280M–MFB
SSO16
SSO16
Tube
U3280M–MFBG3
Taped and reeled
Pin Configuration
Figure 2.
VBatt
1
16
15
14
13
12
11
10
9
Coil 2
VDD
SCL
NRST
SDA
VSS
n.c.
2
3
4
5
6
7
8
Coil 1
n.c.
n.c.
n.c.
n.c.
NGAP
MOD
FC
Pin Description
Pin
Symbol
Function
1
V
Power supply voltage input to connect a battery
Batt
2
V
Power supply voltage for the µC and EEPROM. At this pin a buffer capacitor (0.5... 10 µF) must be
connected to buffer the voltage during field supply and to block the VDD of the mC.
DD
3
4
SCL
NRST
SDA
Serial clock line
Reset line bidirectional
5
Serial data line
6
V
Circuit ground
SS
7
n.c.
FC
Not connected
8
Field clock output of the front end clock extractor
9
MOD
NGAP
n.c.
Modulation input
10
11
12
13
14
15
16
Gap and field detect output
Not connected
n.c.
Not connected
n.c.
Not connected
n.c.
Not connected
Coil 1
Coil 2
Coil input 1. Pin to connect a resonant circuitry for communication and field supply
Coil input 2, see above
2 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
Functional Description
The Transponder
Interface
The U3280M is a transponder interface IC which is able to operate microcontrollers
wireless and battery-independent. Wireless data communication and power supply are
handled via an electromagnetic field and the coil antenna of the transponder interface.
The U3280M consists of a rectifier stage for the antenna, a power management to han-
dle field and battery power supply, a damping modulator and a field-gap detection stage
for contactless data communication, further a field clock extraction and an EEPROM are
on the chip.
The internal rectifier stage rectifies the AC from the LC-resonant circuit at the coil inputs
and supplies the U3280M device and an additional microcontroller device with power. It
is also possible to supply the device via the VBatt input with DC from a battery. The
power management handles switching between battery supply (VBatt pin) and field sup-
ply automatically. It switches to field supply if a field is applied at the coil and it switches
back to battery if the field is removed. The voltage from the coil or the VBatt pin is output
at the VDD pin to supply the microcontroller or any other suited device. At the VDD pin a
capacitor must be connected to smooth and buffer the supply voltage. This capacitor is
also necessary to buffer the supply voltage during the communication (damping and
gaps in the field).
For communication, the chip contains a damping stage and a gap-detect circuitry. By
means of the damping stage the coil voltage can be modulated to transmit data via the
field. It can be controlled with the modulator input (MOD pin) via the microcontroller. The
gap-detection circuitry detects gaps in the field and outputs the gap/field signal at the
gap-detect output (Pin NGAP).
For the storage of data like keycodes, identifiers and configuration bits a 512-bit
EEPROM is available on the chip. It can be read and written by the microcontroller via
an I2C compatible two-wire serial interface.
The serial interface, the EEPROM and the microcontroller are supplied with the voltage
at the VDD pin. That means the microcontroller can read and write the EEPROM if the
supply voltage at VDD is in the operating range of the IC.
The U3280M has build in operating modes to support a wide range of applications.
These modes can be activated via the serial interface with special mode control bytes.
To support applications with battery supply only, the power management can be
switched off by software to disable the automatic switching to field supply.
An on-chip Biphase and Manchester modulator can be activated and controlled by the
serial interface. If this modulator is used it modulates the serial data stream at the serial
inputs SDA and SCL into a Biphase or Manchester coded signal for the damping stage.
Modulation
The transponder interface can modulate the magnetic field by its damping stage to
transmit data to a base station. It modulates the coil voltage by varying the coil’s load.
The modulator can be controlled via the MOD pin. A high level (”1” ) increases the cur-
rent into the coil and damps the coil voltage. A low level (”0”) decreases the current and
increases the coil voltage. The modulator generates a voltage stroke of about 2 V at
pp
the coil. A high level at the MOD pin makes the maximum of the field energy available at
VDD. During a reset a high level at the MOD pin causes the optimum conditions for
starting the device and charging the capacitor at VDD after the field is applied at the coil.
Digital input to control the damping stage (MOD)
MOD = 0: coil not damped
3 (17)
Rev. A4, 11-Dec-01
V
= VDD x √2 + V
= V
CU
coil-peak
CMS
MOD = 1: coil damped
V
= VDD x √2 = V
coil-peak
CD
V
= V
: modulation voltage stroke @ coil inputs
CID
CMS
Note:
If the automatic power management is disabled, the internal front end V is limited at
DD
V
. In this case the value V must be used in the above formula.
DDC DDC
Field Clock
Gap Detect
The field clock extractor of the interface makes the field clock available for the microcon-
troller. It can be used to supply timer inputs to synchronize modulation and
demodulation with the field clock.
The transponder interface can also receive data. The base station modulates the data
with short gaps in the field. The gap-detection circuit detects these gaps in the magnetic
field and outputs the NGAP/field signal at the NGAP pin. A high level indicates that a
field is applied at the coil and a low level indicates a gap or that the field is off. The
microcontroller must demodulate the incoming data stream at one of its inputs.
U3280M Signals and Timing
Figure 3. Modulation
MOD
V
CU
V
V
CMS
CD
Coil inputs
Figure 4. GAP and Modulation Timing
t
t
FGAP0
FGAP1
Gap detection and battery to field switching
V
FDON
V
FDOFF
Coil inputs
1. edge used as wakeup signal
NGAP
Field clock FC
Power management
Battery
supply
Battery supply
Coil supply if automatically power management is enabled
t
BFS
t
FBS
4 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
Digital output of the gap–detection stage (NGAP)
NGAP = 0: gap detected / no field
V
= V
COIL_peak
COIL-peak
FDoff
NGAP = 1: field detected
V
= V
FDon
Note:
No amplifier is used in the gap-detection stage. A digital Schmitt trigger evaluates the
rectified and smoothed coil voltage.
Wake-up Signal
If a field is applied at the coil of the transponder interface the microcontroller can be
woken up with the wake signal at the NGAP pin. For that purpose the NGAP pin must be
connected to an interrupt input of the microcontroller. A high level at the NGAP output
indicates an applied field and can be used as wake signal for the microcontroller via an
interrupt. The wake signal is generated if the power management switches to field sup-
ply. The field-detection stage of the power management has lowpass characteristics to
avoid generating of wake signals and unnecessary switching between battery and field
supply in case of interferences at the coil inputs.
Power Supply
The U3280M has a power management that handles two power supply sources. Nor-
mally the IC is supplied by a battery at the VBatt pin. If a magnetic field is applied at the
LC-resonant circuit of the device the field detection circuit switches automatically from
VBatt to field supply.
The VDD pin is used to connect a capacitor to smooth the voltage from the rectifier and
to buffer the power while the field is modulated by gaps and damping. The EEPROM
and the connected controller always operate with the voltage at the VDD pin.
Note:
During field supply the maximum energy from the field is used if a high level is applied at
the MOD input!
Automatic Power
Management
There are different conditions to switch from the battery to field and back from field to
the battery.
The power management switches from battery to field if the rectified voltage (Vcoil) from
the coil inputs becomes higher than the field-on-detection voltage (V
), even if no
FDon
battery voltage is available (0 < VBatt < 1.8 V). It switches back to battery if the coil volt-
age becomes lower than the field-off-detection voltage (V ).
FDoff
The field detection stage of the power management has lowpass characteristics to sup-
press noise. An applied field needs a time delay t (battery-to-field switch delay) to
BFS
change the power supply. If the field is removed from the coil, the power management
will generate a reset that can be connected to the microcontroller.
Figure 5. Switch conditions for the power management
VCoil > VFDon for t > tBFS
Battery
Field
supply
supply
(VBatt
)
VCoil < VFDon for t > tBFS
Note:
The rectified supply voltage from the coil is limited to V
DDC
(2.9 V). During field supply
the battery is switched off and V
changes to V .
DD
DDC
5 (17)
Rev. A4, 11-Dec-01
Controlling the Power
Management via the Serial
Interface
The automatic mode of the power management can be switched off and on by a com-
mand from the microcontroller. If the automatic mode is switched off the IC is always
supplied by the battery up to the next power-on reset or to a switch on command. The
power management-on and -off command must be transferred via the serial interface.
If the power managment is switched off and the device is supplied from the battery it can
communicate via the field without load the field. This mode can be used to realize appli-
cations with battery supply if the field is to weak to supply the IC with power.
Buffer Capacitor C
The buffer capacitor connected at VDD is used to buffer the supply voltage for the
microcontroller and the EEPROM during field supply. It smoothes the rectified AC from
the coil and buffers the supply voltage during modulation and gaps in the field. The size
of this capacitor depends on the application. It must be of a dimension so that during
modulation and gaps the ripple on the supply voltage is in the range of 100 mV to
300 mV. During gaps and damping the capacitor is used to supply the device, that
means the size of the capacitor depends on the length of the gaps and damping cycles.
B
Example: for a supply current 350 µA, 200 mV ripple @ V
DD
Necessary C
No Field Supply During
B
250 µs
500 µs
470 nF
1000 nF
Serial Interface
The transponder interface has an I2C like serial interface to the microcontroller for read
and write accesses to the EEPROM. In a special mode the serial interface can also be
used to control the Biphase/ Manchester modulator or the ower management of the
U3280M.
The serial interface of the U3280M device must be controlled by a master device (nor-
mally the microcontroller) which generates the serial clock and controls the access via
the SCL and SDA line. SCL is used to clock the data in and out of the device. SDA is a
bidirectional line and used to transfer data into and out of the device. The following pro-
tocol is used for the data transfers.
Serial Protocol
•
•
Data states on the SDA line changing only during SCL is low.
Changes in the SDA line while SCL is high will be interpreted as START or STOP
condition.
•
•
A STOP condition is defined as high-to-low transition on the SDA line while the SCL
line is high.
Each data transfer must be initialized with a START condition and terminated with a
STOP condition. The START condition wakes the device from standby mode and the
STOP condition returns the device to standby mode.
•
A receiving device generates an acknowledge (A) after the reception of each byte.
For that the master device must generate an extra clock pulse. If the reception was
successfull the receiving master or slave device pulls down the SDA line during that
clock cycle. If in transmit mode an acknowledge is not detected (N) by the interface,
it will terminate further data transmissions and will go into receive mode. A master
device must finish its read operation by a not acknowledge and then issue a stop
condition to place the device into a known state.
6 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
Figure 6. Serial protocol
SCL
SDA
Stand Start
by condition
Data
valid
Data
Data/
Stop Stand-
condition by
changeacknowledge
valid
13884
Control Byte Format
Mode control
bits
Read/
NWrite
EEPROM address
A3 A2 A1
Start
A4
A0
C1
C0
R/NW
Ackn
The control byte follows the start condition and consists of the 5-bit row address, 2 mode
control bits and the read/not-write bit.
Data Transfer Sequence
Start
Control byte
Ackn
Data byte
Ackn
Data byte
Ackn
Stop
•
•
Before the start condition and after the stop condition the device is in standby mode
and the SDA line is switched as input with pull-up resistor.
The start condition follows a control byte that determines the following operation. Bit
0 of the control byte is used to control the following transfer direction. A ”0” defines a
write access and a ”1” a read access.
EEPROM
The EEPROM has a size of 512 bit and is organized as 32 × 16 bit matrix. To read and
write data to and from the EEPROM serial interface must be used. The interface sup-
ports one and two byte write accesses and one to n-byte read accesses to the
EEPROM.
EEPROM - Operation
Modes
The operating modes of the EEPROM are defined via the control byte. The control byte
contains the row address, the mode control bits and the read/not-write bit, that is used to
control the direction of the following transfer. A ”0” defines a write access and a ”1” a
read access. The five address bits select one of the 32 rows of EEPROM memory to be
accessed. For all accesses the complete16-bit word of the selected row is loaded into a
buffer. The buffer must be read or overwritten via the serial interface. The two mode
control bits C1 and C2 define in which order the accesses to the buffer are performed:
High byte – low byte or low byte – high byte. The EEPROM supports also autoincrement
and autodecrement read operations. After sending the start address with the corre-
sponding mode consecutive memory cells can be read row by row without transmission
of the row addresses.
Two special control bytes allow to initialize the complete EEPROM with ”0” or with ”1”.
7 (17)
Rev. A4, 11-Dec-01
Write Operations
The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the
START condition followed by writing a write control byte and one or two data bytes from
the master. It is complete with the STOP condition from the master after the acknowl-
edge cycle.
If the EEPROM receives the control byte it loads the addressed memory cell into a 16-
bit read/write buffer. The following data bytes overwrites the buffer. The internal
EEPROM programming cycle is started by a stop condition after the first or second data
byte. During the programming cycle the addressed EEPROM cells are cleared and the
contents of the buffer is written back to the into the EEPROM cells. The complete erase-
write cycle takes about 10 ms.
Acknowledge polling
If the EEPROM is busy with an internal write cycle all inputs are disabled and the
EEPROM will not acknowledge until the write cycle is finished. This can be used to
determine when the write cycle is complete. The master must perform acknowledge
polling by sending a start condition followed by the control byte. If the device is still busy
with the write cycle, it will not return an acknowledge and the master has to generate a
stop condition or perform further acknowlege polling sequencies.
If the cycle is complete, it returns an acknowledge and the master can then proceed with
the next read or write cycle.
Write One Data Byte
Start
Control byte
Control byte
A
A
Data byte 1
Data byte 1
A
A
Stop
Write Two Data Bytes
Start
Data byte 2
A
Stop
Write Control Byte Only
Start
Control byte
A
Stop
A -> acknowledge
Write Control Bytes
Write low byte first
MSB
A4
LSB
R/NW
0
A3
A2
A1
A0
C1
0
C0
1
Row address
Byte order
LB(R)
HB(R)
MSB
A4
LSB
R/NW
0
Write high byte first
Byte order
A3
A2
A1
A0
C1
1
C0
0
Row address
HB(R)
LB(R)
HB: high byte; LB: low byte; R: row address
8 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
Read Operations
The EEPROM allows byte-, word- and current address read operations. The read oper-
ations are initiated in the same way as write operations. Every read access is initiated by
sending the start condition followed by the control byte which contains the address and
the read mode. After the device receives a read command it returns an acknowledge,
loads the addressed word into the read\write buffer and sends the selected data byte to
the master. The master has to acknowledge the received byte if it wants to proceed the
read operation. If two bytes are read out from the buffer the device increments respec-
tively decrements the word address automatically and loads the buffer with the next
word. The read mode bits determines if the low or high byte is read first from the buffer
and if the word address is incremented or decremented for the next read access. If the
memory address limit is reached, the data word address will ”roll over” and the sequen-
tial read will continue. The master can terminate the read operation after every byte by
not responding with an acknowledge (N) and by issuing a stop condition.
Read One Data Byte
Start
Control byte
Control byte
Data byte 1
A
Data byte 1
Data byte 1
N
Stop
Read Two Data Bytes
Start
A
A
Data byte 2
N
Stop
Read n Data Bytes
Start
Control byte
A
A
Data byte 2
A
- - - - - -
Data byte n
N
Stop
A -> acknowledge, N -> no acknowledge
Read Control Bytes
MSB
LSB
R/NW
1
Read low byte first,
address increment
A4
A3
A2
A1
A0
C1
0
C0
1
Row address
Byte order
LB(R)
HB(R)
LB(R+1)
HB(R+1)
- - - -
LB(R+n)
HB(R+n)
MSB
A4
LSB
R/NW
1
Read high byte first
address decrement
A3
A2
A1
A0
C1
1
C0
0
Row address
Byte order
HB(R)
LB(R)
HB(R-1)
LB(R-1)
- - - -
HB(R-n)
LB(R-n)
HB: high byte; LB: low byte; R: row address
Initilization after a Reset
Condition
The EEPROM with the serial interface has ist own reset circuitry. In systems with micro-
controllers that have their own reset circuitry for power-on reset , watchdog reset or
9 (17)
Rev. A4, 11-Dec-01
brown-out reset, it may be necessary to bring the U3280M into a known state indepen-
dent on the internal reset. This is performed by reading one byte without acknowledging
and then generating a stop condition.
Special Modes
Control Byte
1100x111b
1101x111b
Description
Biphase modulation
Manchester modulation
Switch power managment off -> disables switching from battery to field
supply
11xx0111b
Switch power managment on -> enables automatical switching
between battery and field supply
11xx1111b
xxxxx110b
Reserved
Data Transfer Sequence for Biphase and Manchester Modulation:
Start Control byte Ackn Bit 1 Bit 2 Bit 3 - - - - - - - - - - -
Bit n
Stop
With special control bytes the serial interface can be used to control the modulator stage
or the power management. The EEPROM access and the serial interface are disabled
in these modes until to the next stop condition. If no start or stop condition is generated
the SCL and SDA line can be used for the modulator stage. SCL is used for the modula-
tor clock and SDA is used for the data. In that mode the same conditions for clock and
data changing like in the normal are valid. The SCL and SDA line can be used for con-
tinuous bit transfers, an acknowledge cycle after 8 bits must not be generated.
Note:
After a reset of the microcontroller it is not sure that the transponder interface has been
reset too. It could still be in a receive or transmit cycle. To place the serial interface of the
device into a known state the miocrocontroller should read one byte from the device with-
out acknowledge and then generate a stop condition.
Power-On Reset, NRST
The U3280M transponder front end starts working with the applied field. For the digital
circuits like EEPROM serial interface and registers there is a reset circuitry. A reset is
generated by a power-on condition at VDD, by switching back from field to battery sup-
ply and if a low signal is applied at the NRST-pin.
The NRST-pin is a bidirectional pin and can also be used as reset output to generate a
reset for the microcontroller if the circuit switches over from field to battery supply. This
sets the microcontroller in a well defined state after the uncertain power supply condition
during switching.
Antenna
For the transponder interface a coil must be used as antenna. Air and ferrite cored coils
can be used. For battery-less operation the working distance resp. the minimum cou-
pling factor of an application depends on the power consumption and on the size of the
antennas of the IC and the base station. With a power consumption of 150 µA a mini-
mum magnetic coupling factor below 0.5% is within reach. For applications with a higher
power consumption the coupling factor must be increased.
The Q-factor of the antenna coil should be in the range between 30 to 80 for read only
application and below 40 for bidirectional read-write applications.
10 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
The antenna coil must be connected together with a capacitor as a parallel LC resonant
circuit to the Coil 1 and Coil 2 pins of the IC. The resonance frequency f0 of the antenna
circuit should be in the range of 100 to 150 kHz.
The right LC combination can be calculated with the following formula:
Coil 1
Coil 2
1
LA = --------------------------------------------
CA × (2 × π × f0)2
LA
CA
Example: Antenna frequency: f = 125 kHz, capacitor: C = 2.2 nF
0
A
1
LA = ----------------------------------------------------------------------- = 737 µH
2.2 nF × (2 × π × 125 kHz)2
Absolute Maximum Ratings
Voltages are given relative to V
Parameter
.
SS
Symbol
Value
Unit
V
Supply voltage
V
, V
0 V to +7.0 V with reverse protection
DD Batt
Max. current out of V
SS
pin
pin
I
15
15
mA
mA
V
SS
Max. current into V
I
Batt
Batt
Input voltage (on any pin)
V
V
-0.6 ≤ V ≤ V
+0.6
IN
/ I
SS
IN
DD
Input/output clamp current (V > Vi/Vo > V
SS
)
I
+/- 15
+/-2
mA
kV
°C
°C
°C
DD
IK OK
Min. ESD protection (100pF through 1.5kΩ)
Operating-temperature range
T
- 40 to + 85
- 40 to + 125
260
AMB
Storage-emperature range
T
STG
Soldering temperature (t ≤ 10 sec)
T
SD
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at any condition above those indicated in the operational section of
these specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device
reliability. All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to
minimize built-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused
inputs are connected to an appropriate logic voltage level (e.g. V ).
DD
Thermal Resistance
Parameter
Symbol
Value
Unit
Junction ambient
R
180
K/W
thJA
11 (17)
Rev. A4, 11-Dec-01
DC Characteristics
Supply voltage V
= 1.8 to 6.5 V, V = 0 V, T = -40°C to 85°C unless otherwise specified
SS amb
DD
Parameters
Power supply
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Operating voltage at VBatt
V
2.0
6.5
V
V
Batt
Operatíng voltage at VDD
V
V
–
DDB
Batt
during battery supply
V
SD
VDD-limiter voltage during coil
supply
V
2.6
2.9
3.2
80
V
DDC
Operating current during field
supply
V
> 2.0 V
I
40
µA
µA
DD
Fi
Sleep current
I
0.4
Sl
EEPROM
Operating current during
erase/write cycle
V
V
= 2.0 V
= 6.5 V
I
I
400
500
1200
µA
µA
DD
DD
WR
WR
Operating current during read
cycle
V
V
= 2.0 V
= 6.5 V
I
I
300
350
µA
µA
DD
DD
Rdp
Rdp
Peak current during 1/4 of read
cycle
Power management
Field-on detection voltage
Field-off detection voltage
V
V
> 1.8 V
> 1.8 V
VFDon
VFDoff
VSD
2.3
2.5
0.8
2.9
V
V
DD
DD
Voltage drop at
IS = 0.5 mA,
150
mV
power-supply switch
V
= 2 V
Batt
Coil inputs Coil 1 and Coil 2
Coil input current
I
20
mA
pF
V
CI
Input capacitance
C
30
IN
Coil voltage stroke during
modulation
V
> 5V
= 3 to 20 mA
V
1.8
2.3
4.0
CU
CMS
I
coil
Pin MOD
Input LOW voltage
V
V
0.2 ×
V
V
IL
IH
V
DD
DD
Input LOW voltage
V
0.8 ×
V
IH
V
DD
Input leakage current
Pin NGAP/ FC
I
10
nA
Ileakage
Output LOW current
V
= 2.0 V
= 0.2 × V
I
0 . 0 8
0 . 2
0 . 3
m A
m A
DD
OL
V
OL
DD
Output HIGH current
V
= 2.0 V
I
-0.06
-0.15
-0.25
DD
OH
V
= 0.8 × V
OH
DD
12 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
DC Characteristics
Supply voltage V
= 1.8 to 6.5 V, V = 0 V, T
= -40°C to 85°C unless otherwise specified
Test Conditions Pin Symbol Min.
DD
Parameters
SS amb
Typ.
Max.
Unit
Serial interface I/O pins SCL and SDA
Input LOW voltage
V
V
0.3 ×
V
V
IL
IH
V
DD
DD
Input HIGH voltage
V
0.7 ×
V
IH
V
DD
Input leakage current
I
10
nA
Ileakage
Output LOW current
V
= 2.0 V
I
0.7
0 . 9
1 . 1
m A
DD
OL
V
= 0.2 V
DD
OL
V
= 6.0 V
2.8
3.5
4.2
mA
m A
DD
Output HIGH current
V
= 2.0 V
= 0.8 V
= 6.0 V
I
-0.5
- 0 . 6
-0.7
DD
OH
V
OH
DD
V
-1.8
-2.2
-2.6
mA
DD
AC Characteristics
Supply voltage V
= 1.8 to 6.5 V, V = 0 V, T
= -40°C to 85°C unless otherwise specified
DD
SS
amb
Test Conditions
Parameters
Serial interface timing
SCL clock frequency
Clock low time
Pin
Symbol
Min.
Typ.
Max.
Unit
f
0
100
kHz
µs
µs
ns
ns
µs
µs
ns
ns
µs
µs
ns
ns
SCL
t
4.7
4.0
LOW
Clock high time
t
HIGH
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
Bus free time
t
1000
300
R
t
F
t
4.7
4.0
250
0
SUSTA
HDSTA
SUDAT
HDDAT
SUSTO
t
t
t
t
4.7
4.7
t
BUF
Input filter time
t
100
I
Data output hold time
Coil inputs
t
300
100
1000
DH
Coil frequency
f
125
150
kHz
COIL
Gap detection
Delay field off to GAP = 0
Delay field on to GAP = 1
Power management
Battery to field switch delay
Field to battery switch delay
V
V
< 0.7 V
DC
T
T
10
1
50
50
µs
µs
coilGap
FGAP0
FGAP1
> 3 V
coilGap
DC
t
t
1000
30
µs
BFS
VBatt = 6.5 V
5
10
ms
FBS
13 (17)
Rev. A4, 11-Dec-01
AC Characteristics
Supply voltage V
= 1.8 to 6.5 V, V = 0 V, T = -40°C to 85°C unless otherwise specified
SS amb
DD
Parameters
Test Conditions
Pin
Symbol
Min.
500000
10
Typ.
Max.
Unit
EEPROM
Endurance
Erase/ write-cycles
For 16 bits access
Tamb = 25_C
E
Cycles
ms
D
Data erase/ write cycle time
Data retention time
Power up to read operation
Power up to write operation
Reset
t
9
12
DEW
t
years
ms
DR
t
0.2
0.2
PUR
PUw
t
ms
Power-on reset
V
= 0 to 2 V
t
10
ms
DDrise
VIl < 0.2 V
rise
NRST
t
1
µs
DD
res
Figure 7. Typical reset delay after switching V
on
DD
600
500
V
DD
NRST
400
300
200
100
0
t
RESDEL
1.0
2.0
3.0
VDD ( V )
4.0
5.0
6.0
Figure 8. Typical reset delay after switching V
on
DD
5.5
5.0
5 ms
VDD
NRST
4.5
4.0
3.5
3.0
2.5
tRESDEL
1.0
2.0
3.0
VDD ( V )
4.0
5.0
6.0
14 (17)
U3280M
Rev. A4, 11-Dec-01
U3280M
Figure 9. V
rise time to ensure power-on reset
DD
6
5
4
3
2
1
0
Not allowed
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
trise ( ms )
Package Information
Package SSO16
Dimensions in mm
5.00 max
5.00
4.80
6.2
5.8
1.40
0.2
0.25
3.95 max
0.25
0.10
0.635
4.45
5.2
4.8
16
9
technical drawings
according to DIN
specifications
1
8
15 (17)
Rev. A4, 11-Dec-01
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and
do not contain such substances.
16 (17)
U3280M
Rev. A4, 11-Dec-01
Atmel Sales Offices
France
Sweden
Hong Kong
3, Avenue du Centre
78054 St.-Quentin-en-Yvelines
Cedex
Kavallerivaegen 24, Rissne
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Tel: +46 8 587 48 800
Fax: +46 8 587 48 850
Room #1219,
Chinachem Golden Plaza
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East Kowloon, Hong Kong
Tel: +852 23 789 789
Fax: +852 23 755 733
Tel: +33 1 30 60 70 00
Fax: +33 1 30 60 71 11
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Berkshire RG12 1LX
Tel: +44 1344 707 300
Fax: +44 1344 427 371
Germany
Erfurter Strasse 31
85386 Eching
Tel: +49 89 319 70 0
Fax: +49 89 319 46 21
Korea
25-4, Yoido-Dong, Suite 605,
Singsong Bldg.
Youngdeungpo-Ku
150-010 Seoul
Tel: +822 785 1136
Fax: +822 785 1137
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Kruppstrasse 6
45128 Essen
Tel: +49 201 247 30 0
Fax: +49 201 247 30 47
2325 Orchard Parkway
San Jose, California 95131
Tel: +1 408 441 0311
Fax: +1 408 436 4200
Rep. of Singapore
Keppel Building #03-00
25 Tampines Street 92,
Singapore 528877
Theresienstrasse 2
74072 Heilbronn
Tel: +49 7131 67 36 36
Fax: +49 7131 67 31 63
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1465 Route 31, Fifth floor
Annandale
New Jersey 08801
Tel: +1 908 848 5208
Fax: +1 908 848 5232
Tel: +65 260 8223
Fax: +65 787 9819
Taiwan, R.O.C.
8F-2, 266 Sec.1 Wen Hwa 2 Rd.
Lin Kou Hsiang,
244 Taipei Hsien
Tel: +886 2 2609 5581
Fax: +886 2 2600 2735
Italy
Via Grosio, 10/8
20151 Milano
Tel: +39 02 38 03 71
Fax: +39 02 38 03 72 34
Spain
Japan
Principe de Vergara, 112
28002 Madrid
Tonetsushinkawa Bldg.
1-24-8 Shinkawa Chuo Ku
Tokyo 104-0033
Tel: +34 91 564 51 81
Fax: +34 91 562 75 14
Tel: +81 3 3523 3551
Fax: +81 3 3523 7581
Web Site
http://www.atmel-wm.com
© Atmel Germany GmbH 2001.
Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel Germany GmbH’s Terms and Conditions. The Company assumes no responsibility for any errors which may appear in
this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commit-
ment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by
the Company in connection with the sale of Atmel Germany GmbH products, expressly or by implication. Atmel Germany GmbH’s products are
not authorized for use as critical components in life support devices or systems.
Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com
Rev. A4, 11-Dec-01
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