IS29C82_技术文档

MATRA MHS

29C82^*

JPEG Decoder

Description

The 29C82 performs decompression of still pictures in The 29C82 is a peripheral circuit which communicates

accordance with the ISO JPEG 8 R6 standard for basic with the microprocessor over the DATA [0..7] and

systems (pixels coded in 8 bits, sequential display, ADDRESS [0..3] busses. The microprocessor performs

HUFFMAN coding, etc). The 29C82 independently decoding of the JPEG image frame header in order to

executes most following of the adaptive discrete cosine extract the markers, the image parameters, the

transform (ADCT) algorithm :

quantization, and the VLC tables. These tables and

parameters are then used to program the 29C82. After

decoding, the pixels are available on pixels bus

PIXEL[0..7] of the 29C82 or on the DATA [0..7] system

bus. The 29C82 is able to provide pixels at a speed of

1.25 MPixels/s on PIXEL[0..7], with the system clock

(CLK) at 20 MHz.

–

VLC (HUFFMAN) decoding using tables created by

the user or contained in the JPEG image frame. Two

AC tables and two DC tables can be loaded into the

29C82.

–

de-quantization using tables contained in the JPEG

image frame. Two DC tables and two AC tables can

be loaded into the 29C82.

inverse COSINE transform.

Features

D Decoding of still images to the ISO JPEG-8 Rev6 standard.

D Performs VLC decoding, de-quantization and inverse

discrete cosine transform (IDCT).

D Maximum system clock frequency : CLK = 20 MHz.

D Maximum output bit rate : 1.25 mega-pixels/s on the private

bus.

D 8-bit microprocessor interface.

D Dedicated 8-bit pixel bus

D 5 V DC power supply.

D Package : PLCC68

Figure 1. Application Block Diagram using 29C82

* CCETT License

This data sheet includes information obtained from CCETT

Rev. B (20/05/94)

1

29C82

MATRA MHS

Architecture

Figure 2.

2982 Block Diagram

The 29C82 is a peripheral circuit, the system bus of which

is compatible with a demultiplexed address/data bus of

the INTEL type. It contains 4 blocks which are

interconnected over the internal bus (BUSDIF). The

internal “VLC decoder”, “de-quantization operator” and

“DCT operator” blocks are also interconnected over a

data path which enables the passage of coefficients

between the various blocks to be optimized, and the

traffic on the internal BUSDIF bus to be reduced. After

decompression over the various stages mentioned

previously, the pixels can then be read by the system bus

(over BUSDIF) or on the PIXEL[7..0] private bus.

–

the de-quantization block

D the de-quantization operator (see appendix 1).

D 4 de-quantization tables, each containing 64

levels.

D 1 programming register (PROGRAMQ)

the IDCT block :

D 1

inverse

Duhamel-Guillemot type

DCT

operator

of

the

D 1 output FIFO with two 64-byte pages working

alternately - each page can be accessed by the

DATA[7..0] system bus or by the PIXEL[7..0] bus

(like a single 64-bit FIFO).

The 29C82 includes the following blocks :

–

the microprocessor interface

–

the VLC block :

D 1 interrupt monitor with status and control

D VLC decoder (see appendix 3).

registers.

D 2 VLC DC tables, each containing 32 × 5 bits.

D 2 VLC AC tables, each containing 512 × 9 bits.

D 2 sets of registers (Nblock and Mux)

D 1 interface block to allow connection to a

microprocessor over the DATA[7..0] bus, the

ADDR[3..0] bus, WR, RD, CS and READY.

2

Rev. B (20/05/94)

MATRA MHS

29C82

Pin Configuration

Figure 3. 29C82 68 pin PLCC Package. Top View

NAME

TYPE

FUNCTION

Vdd (A1/A4)

supply

core positive supply (+ 5V)

buffer positive supply (+ 5V)

Vdd (A3)

Vdd (A2)

Vdd (B2)

Vdd (B1)

Vss (A1)

Vss (A2)

Vss (A3/A4)

Vss (B1)

Vss (B2)

supply

core negative supply (0V)

buffer negative supply (0V)

CLK

I

reference clock

RESET

hardware reset (active high)

table contents are not changed by reset

DATA[7..0]

ADDR[3..0]

CS

I/O

8 bit system DATA bus

I

4 bit system ADDRESS bus

chip select active low

RD

I

READ active low

WR

I

WRITE active low

READY

O

READY output signal active low

Rev. B (20/05/94)

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29C82

MATRA MHS

NAME

TYPE

FUNCTION

INT

O

I

interrupt signal active high

PRQ

pixel request used to request from 29C82 a block of pixels on pixel bus

(active high)

PIXEL[0..7]

CTYPE[1..0]

BLKRDY

PIXOUT

TEST1

O

I

8 bit tristate pixel bus (at CLK frequency)

component type (tree state) user defined code (ex : cyan, green, Y)

block ready, indicates that a new 64 pixel block is available (active high)

pixel out flag, indicates that pixels are present on pixel bus (active high)

TEST pin, should be left floating in normal mode

TEST2

I

TEST pin, should be left floating in normal mode

Description of Inputs And Outputs

Initialization of the 29C82, loading of the blocks to be A PIXEL[7..0] bus, dedicated to an image memory

decoded into the input FIFO (FIFE), and pixel read after interface, is used to read the pixels after decompression.

decoding, are all accomplished over the microprocessor This bus is able to carry 8 × 8 pixel blocks (line by line)

interface connected to an ADDR[3..0]/ DATA[7..0] at a system clock frequency of 20 MHz. When the bus is

demultiplexed bus. The 29C82 is a peripheral circuit of not used (pixel output on the system bus), PIXEL (7..0]

the microprocessor, it is accessed the 29C82 through a and CTYPE[1..0] are in the high-impedance mode in

16-address window which corresponds to registers, tables order to allow the connection of several 29C82’s in

or FIFOs. A STATUS register, combined with an parallel.

INTerrupt register, informs the µP on any detected change

in status or errors.

Figure 4. 29C82 Read/Write Bus Cycles

4

Rev. B (20/05/94)

MATRA MHS

29C82

Figure 5. Pixel Block Output Timing

Description of the Registers

The microprocessor communicates with the 29C82 over

an 8-bit data bus and a 4 bits address bus, (16 possible

addresses). When one of these 16 addresses corresponds

to a FIFO or a table or a multiple register, read or write

access to the various parts of the FIFO, table or register

set is accomplished sequentially, keeping the address on

ADDR[3..0] constant.

D depth : 512 × 9-bit words, with the 9th bit (LSB)

obtained by address decoding. This is forced to 1

for a leaf of the HUFFMAN tree, and to 0 for a

node of the tree.

D access : write in sequential mode.

The Quantization Tables

The 29C82 contains 4 quantization tables :

D address Q0 : 09H

The VLC Tables

Q1 : 0AH

Q2 : 0BH

Q3 : 0CH

depth : 64 × 8-bit words

access : write in sequential mode.

The 29C82 contains 4 VLC tables. Two are for DC

coefficients and two for AC coefficients. Each VLC table

contains the HUFFMAN tree associated with decoding of

the various AC and DC coefficients.

D

The threshold levels in the quantization tables are written

into Q0 to Q3 in the following order :

D the DC tables

D address : T0_DC : 00H.

01³02³06³07³15³16³28³29

¼

T1_DC : 03H.

03 05 08 14 17 27 30 43

± ½ ½ ±

04 09 13 18 26 31 42 44

depth : 32 × 5-bit words centered on the 5 LSB’s

of the byte written over the microprocessor bus.

Access : write in sequential mode.

T0_DC/T1_DC selection is performed in the

NTAB register of the GENMUX register set.

¼

½

¼

½

¼

½

¼

½

¼

½

¼

10 12 19 25 32 41 45 54

± ½ ½ ±

11 20 24 33 40 46 53 55

½

¼

½

¼

½

¼

½

¼

21 23 34 39 47 52 56 61

± ½ ½ ±

22 35 38 48 51 57 60 62

¼

½

¼

½

¼

D the AC tables

¼

½

¼

½

¼

½

¼

D address : T0_AC : 01H (Nodes)

36³37 49³50 58³59 63³64

and

02H (leaves).

T1_AC : 04H (Nodes)

05H (leaves).

Q0 to Q3 selection is accomplished using the

PROGRAMQ register.

Rev. B (20/05/94)

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29C82

MATRA MHS

Registers

6

Rev. B (20/05/94)

MATRA MHS

29C82

The FIFO’s

Writing to the output Pixel FIFO (MEMPIX) is achieved

using the DCT operator. Read is accomplished :

The input FIFO - FIFE

–

over the PIXEL[7..0] bus if PIX_BUS

(CONTROL register)

= 1

D

address

:

06H

D depth

64 bytes

–

over the DATA[7..0] bus if PIX_BUS = 0

D access type

sequential write

The PIXELS FIFO is splitted into two pages of 64 bytes,

accessed alternately by the DCT operator. While the

operator is calculating the inverse DCT for a block of 8x8

coefficients, the second page of 64 bytes can be accessed

over the PIXEL[7..0] bus or via the DATA[7..0] bus to

output the results of the DCT calculation on the preceding

8x8 block. When the output FIFO is full up, the

BLK_RDY bit of the STATUS register goes to 1, and an

interrupt (INT) is activated if this has been enabled by the

INT3_EN bit in the CONTROL register.

D pointer reset by hardware or software RESET

Write access to FIFE is made through the mP bus.

Reading from FIFE is done via the VLC decoder. The

FIFE_MT bit of the status register is used to indicate that

FIFE is three-quarters empty (3 16 bytes available in

FIFE). The microprocessor is responsible for limiting the

number of write into the FIFO so that its capacity is not

exceeded. When the FIFO is 100% empty, the VLC

decoder does not hold up 29C82 operation.

The output FIFO - MEMPIX

D address : 0F

D depth : 64 bytes 2 y 64

D access type : sequential read

D pointer reset by RESET

The registers

CONTROL

address : 0EH

Access type : write

RESET Hardware

RESET

START

PIX_BUS

CL_FIFE

RSC_ACK

INT3_EN

BLK_RDY

INT2_EN

FIFE_MT

INT1_EN

VLC_ERR

SOFT

7

6

5

4

3

2

1

0

START : DECODING START.

Note : The JPEG standard specifies the use of

re-synchronisation markers in order to segment the

image. These markers are alined on the byte borders.

They can be used for partial re-transmission of images

after detection of errors.

START=1 enables the start of image decoding. This

bit is reset to 0 one clock period (CLK) after it has

been written to 1 in the control register.

PIX_BUS : BUS PIXEL

D PIX_BUS=0. Read access to the output

FIFO, MEMPIX, occurs over the

microprocessor bus. The PIXEL[7..0] and

CTYPE[1..0] outputs are in the

The Interrupts

When the INTx_EN enable bit is at 1, the interrupt request

(INT) can be activated :

high-impedance

state,

PIXOUT=0,

BLKRDY is active and PRQ is inactive.

D PIX_BUS=1, read access to the output

FIFO is performed over the PIXEL[7..0]

private bus.

–

INT3_EN : if the output FIFO, MEMPIX, contains a

full block of 8x8pixels (bit BLK_RDY=1 in the

STATUS register). Reading a single pixel from

MEMPIX causes a reset of the interrupt request.

INT2_EN : if the input FIFO, FIFE, is three-quarters

empty (bit FIFE_MT=1 in the STATUS register).

INT1_EN : when a VLC decoding error is detected

(bit VLC_ERR=1 in the STATUS register).

CL_FIFE : Input FIFO reset

–

CL_FIFE=1 causes a zero reset of the input

FIFO, FIFE. This bit is automatically reset

to 0 one CLK period after it has been

written to 1 in the CONTROL register.

The microprocessor must read the STATUS register to

identify the cause of the interrupt. One interrupt process

cycle allows the output INT to be forced to 0 (at least

RSC_ACK : DECODING OF THE RESYNCHRO-

NISATION MARKERS.

RSC_ACK=1 enables decoding of the

RSC0(FFD0) to RSC7(FFD7) markers.

Rev. B (20/05/94)

7

29C82

MATRA MHS

during the cycle period) and the associated interrupt

request to be de-activated in the following way :

have been written to FIFE after an INT-2 interrupt

request does not necessarily cause the FIFO pointer to

go to a value over 16 (the 3/4 empty level). In such a

case, a new INT-2 interrupt occurs.

INT-3 (block ready in the output FIFO) : reading (one

pixel only) from MEMPIX resets BLK_RDY (the

status register) and the BLKROY/INT outputs to “0”.

If INT-1 or INT-2 are active, INT goes back to 1 after

the first read cycle from MEMPIX.

–

INT-1 (VLC error) : read NBLOCK register. If INT-2

or INT-3 are active, INT goes back to 1 after fully

reading NBLOCK (3 bytes).

–

INT-2 (FIFE three-quarters empty) : a write to FIFE

is used to reset the FIFE_MT bit of the STATUS

register to 0, and to force the INT output to 0. If INT-1

or INT-3 are active, INT goes back to 1 after the write

cycle to FIFE. Caution : the fact that one or more bytes

Figure 6.

INT3_EN : “OUTPUT

BLOCK

READY”

(VLC ERROR) interrupt request to the

microprocessor.

INTERRUPT ENABLE.

INT3_EN=1 enables transmission of INT-3

(BLOCK READY) interrupt request to

the microprocessor.

RESET :

SOFTWARE RESET RESET=1 is used to

re-initialise the internal STATUS register

and also the FIFO pointers without

affecting the contents of the tables and the

CONTROL, PROGRAMQ, NBLOCK,

and MUXGEN registers. This bit is

automatically reset to 0 one CLK period

after it has been written to “1”.

INT2_EN : “FIFE 3/4 EMPTY” INTERRUPT

ENABLE.

INT2_EN=1

enables

transmission of INT-2 (FIFE 3/4 EMPTY)

interrupt request to the microprocessor.

INT1_EN : “VLC ERROR” INTERRUPT ENABLE.

INT1_EN=1 enables transmission of INT-2

STATUS

CTYP [1]

address 0EH

CTYP [0]

Access Type : read

RESET SOFTWARE or HARDWARE

BLK_RDY

DCT_BSY

RSC [2]

QZT_BSY

RSC [1]

VLC_BSY

RSC [0]

VLC_ERR

FIFE_MT

7

6

5

4

3

2

1

0

8

Rev. B (20/05/94)

MATRA MHS

29C82

CTYP[1..0] : COMPONENT TYPE.

VLC_ERR : VLC ERROR. VLC_ERR=1 indicates that

a VLC decoding error has been detected.

This type of error can be caused by :

– detection of an EOI or RSC marker with

the content of the NBLOCK register

different from 0.

These two bits are used to indicate the

image component to which the pixel block

available in MEMPIX belongs. The

CTYP[1..0] bits are in the same state as the

CTYPE[1..0] outputs.

– detection of a VLC code with a length of

more than 16 bits.

– a coefficient pointer over 63.

BLK_RDY : PIXEL BLOCK READY. The BLK_RDY

bit goes to 1 when a new 8 × 8 pixel block

is available in MEMPIX. BLK_RDY bit is

in the same state as the BLKRDY output.

In this case, the RSC[2..0] of the status

register represent the three LSB’s of the last

re-synchronisation marker detected before

the error. Output INT goes to 1 if bit

INT1_EN of the CONTROL register is at

1. The microprossor reads from NBLOCK

the number of blocks remaining to be

DCT_BSY : DCT OPERATOR ACTIVE (FOR

INFORMATION ONLY).

DCT_BSY=1 indicates that the reverse

DCT operator is active. If bit

VLC_ERR=1, this bit is re-defined as

RSC[2] (see description of the VLC_ERR

bit).

decoded

(NBLOCK

acts

as

a

down-counter) in order to reset the

interrupt and the VLC_ERR bit to 0. In the

case where there is no re-synchronisation,

the µP (APPLICATION) selects the

strategy to be used (re-transmission of

BLOCK, SCAN, FRAME, IMAGE, etc.)

When one or more re-synchronisation

markers exist, the 29C82 waits for the next

resynchronisation marker so that it can

continue decoding of the current image.

QZT_BSY : DE-QUANTIZATION

ACTIVE (FOR INFORMATION ONLY).

QZT_BSY=1 indicates that the

OPERATOR

de-quantization operator is active. If bit

VLC_ERR=1, this bit is re-defined as

RSC[1] (see description of the VLC_ERR

bit).

VLC_BSY : VLC DECODING OPERATOR ACTIVE

(FOR INFORMATION ONLY).

VLC_BSY=1 indicates that the VLC

operator is active. If bit VLC_ERR=1, this

bit is re-defined as RSC[0] (see description

of the VLC_ERR bit). The VLC operator is

always active, even if FIFE is completely

empty. VLC_BSY is reset to 0 only after a

RESET and before the START bit has been

set to 1.

FIFE_MT : FIFE 3/4 EMPTY.

FIFE_MT=1 when the input FIFO, FIFE, is

three-quarters empty (16 bytes left ≤).

When the INT2_EN bit of the CONTROL

register is at 1, the INT output goes to 1. In

this case, the microprossor can write 48

new bytes into FIFE.

PROGRAMQ

QCT3 [1]

address 0DH

QCT2 [1]

Access type : write

QCT2 [0] QCT1 [1]

Reset : HARDWARE

QCT3 [1]

QCT1 [0]

QCT0 [1]

QCT0 [0]

7

6

5

4

3

2

1

0

QCT3[1..0] : “QUANTIZATION

TABLE” QCT1[1..0] : “QUANTIZATION

TABLE”

REFERENCE FOR COMPONENT 3.

These two bits code the reference of the

quantization table for a block which

belongs to a type-3 image component.

REFERENCE FOR COMPONENT 1.

These two bits code the reference of the

quantization table for a block which

belongs to a type-1 image component.

QCT2[1..0] : “QUANTIZATION

TABLE” QCT0[1..0] : “QUANTIZATION

TABLE”

REFERENCE FOR COMPONENT 2.

These two bits code the reference of the

quantization table for a block which

belongs to a type-2 image component.

REFERENCE FOR COMPONENT 0.

These two bits code the reference of the

quantization table for a block which

belongs to a type-0 image component.

Rev. B (20/05/94)

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29C82

MATRA MHS

The Multiple Registers

NBLOCK address 07H

depth : 3 bytes

Access type : sequential read/write

RESET HARDWARE

NBLK[23]

NBLK[15]

NBLK[07]

NBLK[22]

NBLK[14]

NBLK[06]

NBLK[21]

NBLK[20]

NBLK[12]

NBLK[04]

NBLK[19]

NBLK[18]

NBLK[10]

NBLK[02]

NBLK[17]

NBLK[09]

NBLK[01]

NBLK[16]

7

6

5

4

3

2

1

0

NBLK[13]

NBLK[05]

NBLK[11]

NBLK[03]

NBLK[08]

NBLK[00]

NBLK[23..0] : NUMBER OF BLOCKS

The ADCT algorithm allows two interlacing modes :

NBLK[23..0] contains the number of

blocks to be decoded between the two

markers (RSC_ACK=1) or for a full image

–

the frame interlace mode, where each component is

coded separately and transmitted sequentially for a

complete image (e.g. press images, “yellow”, “blue”,

“red”, “black” transmission).

(RSC_ACK=0).

The

29C82

uses

NBLOCK as a down-counter.

The block interlacing mode, where the 8x8 blocks are

interlaced in accordance with a repeating pattern (MDU)

(e.g. Videotext transmission of two 8x8 luminance

blocks, one 8 × 8 “red” chrominance block, 1 “blue”

chrominance block, ...)

MUXGEN address 08H Access type : sequential write

depth : 7 bytes RESET HARDWARE

MUXGEN contains 7 registers :

NTAB

X

VLCT3

VLCT2

VLCT1

VLCT0

7

6

5

4

3

2

1

0

VLCT3 :

VLC TABLE FOR TYPE-3 IMAGE VLCT1 :

COMPONENT.

VLC TABLE FOR TYPE-1 IMAGE

COMPONENT.

This bit indicates which VCL table will be

used for a block belonging to the type-3

component. (“0” for T0_DC/ T0_AC and

”1” for T1_DC/T1_AC).

This bit indicates which VCL table will be

used for a block belonging to the type-1

component. (“0” for T0_DC/T0_AC and

“1” for T1_DC/T1_AC).

VLCT2 :

VLC TABLE FOR TYPE-2 IMAGE VLCT0 :

COMPONENT.

VLC TABLE FOR TYPE-0 IMAGE

COMPONENT.

This bit indicates which VCL table will be

used for a block belonging to the type-2

component. (“0” for T0_DC/ T0_AC and

“1” for T1_DC/T1_AC).

This bit indicates which VCL table will be

used for a block belonging to the type-0

component. (“0” for T0_DC/T0_AC and

“1” for T1_DC/ T1_AC).

NCOMP

X

COMP[1]

COMP[0]

7

6

5

4

3

2

1

0

COMP[1..0] : NUMBER OF IMAGE COMPONENTS

COMP[1..0] contains the number of

image components to be decoded :

11 → 4 components

10 → 3 components

01 → 2 components

00 → 1 components

10

Rev. B (20/05/94)

MATRA MHS

29C82

ORDER

1_CT[1]

7

1_CT[0]

2_CT[1]

2_CT[0]

3_CT[1]

3_CT[0]

4_CT[1]

4_CT[0]

1 0

6

5

4

3

2

The “quantization table”, “VLC table”..., data associated 2_CT[1..0] : TYPE OF FIRST COMPONENT. These

with each image component are clearly specified in the

JPEG header (see appendix 2). The ORDER register is

used to associate indirectly a component type with a

component of the JPEG frame. The PROGRAMQ and

NTAB registers are used to associate the VLC and

quantization tables with each component type.

two bits code the type of the second

component to be processed.

3_CT[1..0] : TYPE OF FIRST COMPONENT. These

two bits code the type of the third

component to be processed.

4_CT[1..0] : TYPE OF FIRST COMPONENT. These

two bits code the type of the fourth

component to be processed.

1_CT[1..0] : TYPE OF FIRST COMPONENT. These

two bits code the type of the first

component to be processed.

BLOCK-0

BCT0[7]

BCT0[6]

BCT0[5]

BCT0[4]

BCT0[3]

BCT1[3]

BCT2[3]

BCT3[3]

BCT0[2]

BCT0[1]

BCT0[0]

7

6

5

4

3

2

1

0

BCT0[7..0] : NUMBER OF SUCCESSIVE BLOCKS

FOR TYPE-0 COMPONENT.

The BLOCK-0 register indicates (in 8 bits)

the number of successive 8 × 8 blocks

contained in 1 MDU.

BLOCK-1

BCT1[7]

BCT1[6]

BCT1[5]

BCT1[4]

BCT1[2]

BCT1[1]

BCT1[0]

7

6

5

4

2

1

0

BCT1[7..0] : NUMBER OF SUCCESSIVE BLOCKS

FOR TYPE-1 COMPONENT.

The BLOCK-1 register indicates (in 8 bits)

the number of successive 8 × 8 blocks

contained in 1 MDU.

BLOCK-2

BCT2[7]

BCT2[6]

BCT2[5]

BCT2[4]

BCT2[2]

BCT2[1]

BCT2[0]

7

6

5

4

2

1

0

BCT2[7..0] : NUMBER OF SUCCESSIVE BLOCKS

FOR TYPE-2 COMPONENT.

The BLOCK-2 register indicates (in 8 bits)

the number of successive 8 × 8 blocks

contained in 1 MDU.

BLOCK-3

BCT3[7]

BCT3[6]

BCT3[5]

BCT3[4]

BCT3[2]

BCT3[1]

BCT3[0]

7

6

5

4

2

1

0

BCT3[7..0] : NUMBER OF SUCCESSIVE BLOCKS

FOR TYPE-3 COMPONENT.

The BLOCK-3 register indicates (in 8 bits)

the number of successive 8 × 8 blocks

contained in 1 MDU.

Rev. B (20/05/94)

11

29C82

MATRA MHS

Initialisation

Before it can be used, the 29C82 has to be programmed

by the microprocessor as follows :

D write to register PROGRAMQ

D write to the CONTROL register (START=0).

1 - the RESET bit of the CONTROL register is put to 1

for a partial reset, or a complete reset is achieved by

forcing the RESET pin to 1.

3 - Put the START bit of the CONTROL register to 1.

4 - Load the input FIFO (FIFE). This step can be

programmed after setting CL_FIFE and before setting

the START bits.

2 - in any order :

D load the NBLOCK register

D load the MUXGEN register

D load the VLC table (example in appendix 4)

D load the quantization tables (example in

appendix 5)

After the 29C82 has started decoding, the microprocessor

is able to poll the STATUS register or the state of the

output INT to discover the state of progress of the current

decoded block.

Electrical Characteristics

Absolute Maximum Ratings

Operating Characteristics

VCC to earth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to +7V

Input/output voltage . . . . . . . . . . . . . . . . . . . . . . –0.3V to VCC + 0.3V

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to +150°C

VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to +5.5V

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70°C

Load capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50pF on each output

Electrical DC Characteristics

PARAMETER

CONDITIONS

MIN

MAX

Input voltage VIL

Input voltage VIH

I=5µA

0.8V

2.2V

All inputs except Test 1 and Test 2

Input current leakage

Test 1 and Test 2

– 5µA

+ 5µA

+ 100µA

0.4V

Output voltage, level 0

Output voltage, level 1

Dynamic consumption

I = 6.4mA

6.4mA

2.4 V

VCC=5V, 20MHz

120mA

12

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29C82

AC Timings

VCC = 5V ± 10%. Temperature = 0 to 70°C

50 pF load on all outputs

MIN

ns

MAX

ns

NAME

DESCRIPTION

tphch

tchpl

tchqv

tchqx

tchqz

tdvwh

twhdx

twhyh

twlyl

tchcl

tclch

trlyl

PRQ to CLK setup time

20

5

PRQ to CLK hold time

CLK to PIXEL_BUS data delay

CLK to PIXEL_BUS not floating

CLK to PIXEL_BUS floating

DATA[0..7] to WR setup time

DATA[0..7] to WR hold time

CS/WR high to READY low delay

CS/WR low to READY low delay

minimum high CLK pulse width

minimum low CLK pulse width

CS/RD low to READY low

CS/RD high to READY high

RD/CS to DATA_BUS data delay

RD/CS to DATA_BUS not floating

RD/CS high to DATA_BUS floating

CLK period

40

35

5

20

25

5tclk+30

25

trhyh

trldv

trldx

trhdz

tclk

5tclk+35

5tclk+5

20

50

twlwh

twhax

tavw

trlrh

write pulse width

1tclk

2tclk

3tclk

6tclk

1tclk

7tclk

ADDR[3..0] / WR hold time

address hold time (write)

RD pulse width

trhax

tavr

ADDR[3..0] / RD hold time

address hold time (read)

Rev. B (20/05/94)

13

29C82

MATRA MHS

AC Timings

14

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29C82

Appendix 1

The various stages of ADCT

The successive stages of image de-compression for a decoding, the dequantization and the Inverse cosine

basic JPEG system are the VLC coding (Huffman) transform.

The two-dimensional Cosine Transform

The image is divided into 8 × 8 pixel blocks and then divided into 90 × 72 blocks for Y luminance and 45 × 72

polled in the order shown in figure 1. In the case of a 720 blocks for Cr and Cb chrominance.

× 576 pixel image in 4:2:2 for example, the image will be

Figure 7.

Rev. B (20/05/94)

15

29C82

MATRA MHS

Level transposition

Before applying the Cosine Transform to the unsigned data (Y,Cr,Cb) a level transposition is performed by subtracting

128 (for 8-bit data).

The Cosine Transform

For each block, the Cosine Transform is used to convert from the space domain (the pixels) to the frequency domain

(the coefficients), by applying the direct Cosine Transform (FDCT).

7

_{F u, v + 1ń4C u @}_C(v)ȍȍ_{F i, j cos 2i ) 1 u @ pń16 @ cos 2j ) 1 v @ piń16}

)

(

)

( )

(

)

(

)

i+0 j+0

or from the frequency domain to the space domain using the inverse Cosine Transform (IDCT).

7

_{F i, j + 1ń4}ȍȍ_{C u @ C v F u, v cos 2i ) 1 u @ pń16 @ cos 2j ) 1 vpiń16}

)

(

)

( )

( ) (

)

(

)

u+0 v+0

Figure 8.

Quantization

An essential property of the Cosine Transform is the each 8x8 block into the DC component and some

concentration of the energy in the coefficients between ’low-frequency” AC components.

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29C82

Since the human eye is not very sensitive to Example :

high-frequency AC components, these can be quantized

in a coarser manner.

signal value

probability

0

1

2

3

4

.11

.52

.25

.01

.11

Each coefficient is quantized as follows :

F(u,v)0 : C(u,v) =

full division (F(u,v)+(Q(u,v)/2))/Q(u,v)

F(u,v) : C(u,v) =

full division (F(u,v) – (Q(u,v)/2))/Q(u,v)

a - classification of probabilities in decreasing order, and

grouping of the lowest probability values.

F(u,v) is the coefficient before quantization

C(u,v) is the coefficient after quantization

Q(u,v) indicates no quantization

.52, .25, .11, .11, .01

.52, .25, .12, .11,

.52, .25, .23

De-quantization is performed in a similar fashion :

F’(u,v) = C(u,v) * Q(u,v)

.52, .48

b - construction of the HUFFMAN tree

root

HUFFMAN coding

ń

Ņ

The average number of bits necessary to code a signal

without loss of information can be measured by entropy

of the signal. A procedure used commonly to construct

the associated variable-length code words is known as

HUFFMAN coding.

0

1

(.52) .48

0ń

Ņ1

(.25) .23

0ń

Ņ1

.12 (.11)

One intuitively associates short code words to frequent

signal values and longer code words to the less frequent

values.

0ń

Ņ1

(.11) (.01)

c - association of Code

SIGNAL VALUE

PROBABILITY

HUFFMAN CODE

CODE LENGTH

1

2

0

4

3

.52

.25

.11

.01

0

10

111

1100

1101

1

2

3

4

This technique is used in the JPEG frame for coding the block of coefficients is transmitted in the following

DC and AC components after quantization. Each 8 × 8 order :

0

2

3

1

4

8

11

19

22

36

5

7

6

13

17

24

32

38

49

14

16

25

31

39

46

57

15

26

30

40

45

51

58

27

29

41

44

52

55

62

28

42

43

53

54

61

63

0 =DC coefficient

12

18

23

33

48

9

10

20

35

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MATRA MHS

Appendix 2

Structure of a JPEG frame

A JPEG image is divided into signalling or data segments. the segment. The last data item of a segment is ended with

Each segment starts with an FFxx marker in hex notation. a “1” so that FFxx is aligned on a byte border.

The last xx byte of the marker identifies the function of

Figure 9.

S0I

FFD8

FFFE

FFD8

FFC4

FFC0

IMAGE START

S0C

DQT

DHT

S0F0

COMMENTS

QUANTIZATION TABLES

VLC TABLES

FRAME

Parameter definition :

sample precisio,n number of line,s number of samples per lin,e num-

ber of components in fram,e vertical sampling factor horizontal

sampling facto,r selection of quantization table.

S0S

E0I

FFDA

FFD9

SCAN 1 Parameter definition : number of scan components, choice

of HUFFMAN matrix (AC, DC), choice of mode (sequential, pro-

gressive). Coded data

IMAGE END

Comments

Example

fffe

: COM marker

0020

: Comment length (30 usable bytes)

: MATRA MHS Electronic – APPLICATION LAB

: 1992

432d 4355 4245 204d

6963 726f 7379 7374

656d 7320 496e 632e

2031 2e30 3000

: JPEG image example

Quantization tables

The quantization tables are always included in the header of the frame (1 per component type).

Example

ffdb

: DQT marker

007F

00

: Table length (2 tables × 8 bits)

: Table 0 : luminance

10 0b 0c 0e 0a 10 0e

0d 0e 12 11 10 13 18 28

1a 18 16 16 18 31 23 25

1d 28 3a 33 3c 3c 39 33

38 37 40 48 5c 4e 40 44

57 45 37 38 50 6d 51 57

5f 70 64 78 5c 65 67 63

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29C82

01

: table 1 : Chrominance (Cr/Cb)

11 12 12 18 15 18 2f 1a

1a 2f 63 42 38 42 63 63

63 63 63 63 63 63 63 63

The HUFFMAN Tables

HUF(ssss) = the HUFFMAN code associated with ssss

Coding the DC coefficients

The HUFFMAN table (HUFCODE) associated with ssss

is not transmitted directly in the JPEG image header. In

fact two tables, [BITS] and [HUFVAL], are used for this :

Only the DC coefficient of the first block is transmitted

in the form of an absolute value. The following

coefficients are transmitted differentially in relation to

this first block. The value of the DC coefficient to be

transmitted is divided into 16 categories coded in 4 bits,

ssss, and corresponds to the length of the DC delta code

to be sent :

[BITS] is 16 bytes long and contains the number of ssss

values (categories) coded in 1 bit, 2 bits, 3 bits ... 16 bits

in the HUFFMAN table.

[HUFVAL] contains the list of ssss values (categories)

sorted into ascending order of length of the HUFFMAN

code (1 bit to 16 bits).

ssss

0

DC delta

0

1

2

3

–1,+1

–3,–2,2,3

–7..–4,4..7

In a basic system, there can be a maximum of two [BITS]

- [HUFVAL] pairs, transmitted by the DC coefficients.

4

–15..–8,8..15

5

6

7

8

–31..–16,16..31

–63..–32,32..63

Example :

ffc4

01a2

00

0001 0501 0101 0101

00100 0000 0000 0000

0001 0203 0405 0607

0809 0a0b

: DHT marker

: Table length

: DC table 1

–127..–64,64..127

–255..–128,128..255

–511..–256,256..511

–1023..–512,512..1023

–2047..–1024,1024..2047

–4095..–2048,2048..4095

–8191..–4096,4096..8191

–16383..–8192,8192..16383

–32767..–16384,16384..32767

9

: BITS matrix

10

11

12

13

14

15

: HUFVAL matrix

(12 elements)

: DC table 2

01

0003 0101 0101 0101

0101 0100 0000 0000

0001 0203 0405 0607

0809 0a0b

: BITS matrix

The DC coefficients are coded in the following manner :

: HUFVAL matrix

(12 elements)

HUF(ssss)

DC coefficient

Rev. B (20/05/94)

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29C82

MATRA MHS

Creation of matrices [EHUFCO] and [EHUFSI] from [BITS] and [HUFVAL]

(JPEG standard) :

The following algorithm is used to create the [HUFSIZE] associated with ssss as a function of decreasing priority

table containing the length of the HUFFMAN codes values :

The following algorithm is used to create the associated with ssss as a function of decreasing priority

[HUFCODE] table containing the HUFFMAN codes values :

20

Rev. B (20/05/94)

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29C82

The following algorithm is used to reorganise HUFSIZE and HUFCODE as a function of decreasing ssss (HUFVAL)

values :

Example

ssss

0

1

EHUHSI

EHUFCO

010

3

011

2

3

100

3

2

00

4

3

101

...

11

...

9

...

111111110

The reconstitution of the HUFFMAN decoding tree (see appendix 1) can be accomplished using EHUFCO and

EHUFSI :

Coding the AC coefficients

The AC coefficients to be transmitted are divided into 256 nnnn gives the number of coefficients equal to 0 between

categories, coded in 8 bits, nnnnssss.

two non-zero coefficients, and ssss gives the amplitude

category for the AC coefficients.

Rev. B (20/05/94)

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29C82

MATRA MHS

00000000 represents E0B which is the end-of-block

indicator.

Example

10

: AC table 1

0002 0103 0302 0403

0605 0404 0000 017d

0102 0300 0411 0612

2131 4106 1351 6107

2271 1432 8191 a108

2342 b1c1 1552 d1f0

2433 6272 8209 0a16

1718 191a 2526 2728

292a 3435 3637 3839

3a43 4445 4647 4849

4a53 5455 5657 5859

5a63 6465 6667 6869

6a73 7475 7677 7879

7a83 8485 8687 8889

8a92 9394 9596 9798

999a a2a3 a4a5 a6a7

a8a9 aab2 b3b4 b5b6

b7b8 b9ba c2c3 c4c5

c6c7 c8c9 cad2 d3d4

d5d6 d7d8 d9da e1e2

e3e4 e5e6 e7e8 e9ea

f1f2 f3f4 f5f6 f7f8

f9fa

: BITS matrix

ssss

0

1

2

3

4

5

6

7

AC coefficient

0

–1,+1

–3,–2,2,3

–7..–4,4..7

: HUFVAL matrix

(162 elements)

–15..–8,8..15

–31..–16,16..31

–63..–32,32..63

–127..–64,64..127

–255..–128,128..255

–511..–256,256..511

–1023..–512,512..1023

8

9

10

11 –2047..–1024,1024..2047

12 –4095..–2048,2048..4095

13 –8191..–4096,4096..8191

14 –16383..–8192,8192..16383

15 –32767..–16384,16384..32767

The AC coefficients are coded in the following manner :

11

: AC table 2

0002 0102 0404 0304

0705 0404 0000 0277

0001 0203 1104 0521

3106 1241 5107 6171

1322 3281 0814 4291

a1b1 c109 2333 52f0

1562 72d1 0a16 2434

e125 f117 1819 1a26

2728 292a 3536 3738

393a 4344 4546 4748

494a 5354 5556 5758

595a 6364 6566 6768

696a 7374 7576 7778

797a 8283 8485 8687

8889 8a92 9394 9596

9798 999a a2a3 a4a5

a6a7 a8a9 aab2 b3b4

b5b6 b7b8 b9ba c2c3

c4c5 c6c7 c8c9 cad2

d3d4 d5d6 d7d8 d9da

e2e3 e4e5 e6e7 e8e9

eaf2 f3f4 f5f6 f7f8

f9fa

: BITS matrix

HUF(nnnssss)

AC coefficient

: HUFVAL matrix

(289 elements)

HUF(nnnnssss) = the HUFFMAN code associated with

nnnnssss

The HUFFMAN table (HUFCODE) associated with

nnnnssss is not transmitted directly in the JPEG image

header (ss DC coefficients). In fact two tables, [BITS] and

[HUFVAL], are used for this.

In 16 bytes, [BITS] contains the number of nnnnssss

values (categories) coded in 1 bit, 2 bits, 3 bits ... 16 bits

in the HUFFMAN table.

[HUFVAL] contains the list of nnnnssss values

(categories) sorted into ascending order of length of the

HUFFMAN code (1 bit to 16 bits).

In a basic system, and for the AC coefificients, there can

be a maximum of two [BITS] - [HUFVAL] pairs.

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29C82

The algorithms given in the paragraph dealing with

coding of the DCcoefficients are used to create the

[EHUFSI] table containing the length of the HUFFMAN

codes associated with nnnnssss and the [EHUFCO] table

containing the HUFFMAN codes associated with

nnnnssss.

single image component,

the interleavce mode, where a single scan contains the

data for all components in the frame.

–

Within the frame, data is transmitted in MDU form. In the

non-interlace mode, an MDU is a block of 8 × 8

coefficients which correspond, for example, to Y

(luminance) or Cr/Cb (chrominance). In the interlace

mode, and MDU is an interlacing of blocks defined by the

sampling factor Hi,Vi and by NS, the number of

components in the scan. In the following example, the

scan is described by three components, Y, Cr and Cb, with

respective sampling factors of 2h :1v, 1h :1v, and 1h :1v.

Start of frame (DCT basic mode)

The number of components in a frame is limited to 4

(quadrichromy - black, blue, yellow and red). Each frame

can contain several successive scans, each corresponding

to one component of the image.

The MDU is described by the following :

There are two scan modes :

–

the non-interleave mode, where each scan contains a Y ,Y ,C ,C ;Y ,Y ,C ,C ...Y ,Y

,C ,C ...

2n 2n+1 rn bn

1

2

r1 b1

3

4

r2 b2

Data

The data are sent with the most significant byte leading and most significant bit leading.

Example :

93fd 1639 9954 7c9e

5fda 653e 667e fe57

3cee 1cee 2df8 ff00

.....................................

d476 96d1 cd74 e2df

7e0b 7ef3 f7ca bb63

c705 7e99 1c00 f418

ffds

when FF is created during coding, byte 00 is added to the data

: marker EOI, end of image

Example :

1

01

: V3 vertical sampling factor = 1

: selection of quantization table 1

FFC0

0011

08

0100

03

: SOF0 marker

: fields length = 17

Scanning

ffda

000C

03

01

0

02

1

: S0S = start scan marker

: sample precision = 8 bits

: number of Y lines = 256

: number of × samples per line = 256

: number of image components

in the frame = 3

: length of field (10 usable bytes)

: Ns = number of components in scan = 3

: selection of scan component = 1

: selection of HUFFMAN table, DC = 0

: selection of HUFFMAN table, AC = 0

: selection of scan component = 2

: selection of HUFFMAN table, DC = 1

: selection of HUFFMAN table, AC = 1

: selection of scan component = 3

: selection of HUFFMAN table, DC = 1

: selection of HUFFMAN table, AC = 1

: DCT/Sequential mode, Ss = 0,

Se = 63,

01

2

1

00

02

1

: component 1

: H1 horizontal sampling factor = 2

: V1 vertical sampling factor = 1

: selection of quantization table 0

: component 2

: H2 horizontal sampling factor = 1

: V2 vertical sampling factor = 1

: selection of quantization table 1

: component 3

03

1

003F00

01

03

1

Ah = 0, Al = 0

: H3 horizontal sampling factor = 1

Rev. B (20/05/94)

23

29C82

MATRA MHS

Appendix 3

Operation of the VLC Decoder (29C82)

The VLC RAM contains the HUFFMAN decoding tree (see appendix 2). The following example illustrates the

(see appendix 1). This tree is obtained from the [BITS] extraction of DC and AC parameters from the data of the

and [HUFVAL] matrices contained in the frame header JPEG frame.

a - LOADING THE TABLES

Tables T0-DC and T0-AC are respectively programmed with :

T0-DC :

02 01 09 07 03 01 01 01 01 01 01 01 01 01 01 01

04 05 06 08 01 01 01 01 01 01 01 01 01 01 01 01

T0-AC

002 001 00E 008 00A 005 023 0E3 043 019 143 083 0A3 001 001 001

.........

(16 lines)

004 003 006 012 00c 007 025 010 063 014 016 001 0c3 001 001 001

.........

(16 lines)

Each VLC table is divided into 2 zones (2 × 16 bytes for it contains the address of the next node (or leaf) of the

the DC tables and 2 × 256 bytes for the AC tables). The HUFFMAN tree, shifted 1 bit left, the LSB being forced

last bit extracted from the data stream indicated the zone to 0.

to be addressed.

Each word of the VLC table containing a leaf of the tree

will be forced to an odd number. In this case it contains

ssss (or nnnnssss) shifted 1 bit left, the LSB being forced

Conventions

Each word in the VLC table containing a node of the

to 1.

HUFFMAN table is forced to an even value. In this case

24

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29C82

Figure 10.

Rev. B (20/05/94)

25

29C82

MATRA MHS

b - DECODING THE DATA

b1 - extraction of the DC parameters

–

extraction of the DC coefficient from the data stream :

data stream →

Each DC VLC table is composed of 32 5-bit words, with

the LSB forced to 0 or 1 depending on whether the word

corresponds to a node or a leaf of the VLC tree.

0110011101100101000010000010...

delta DC_bloc_0 = 10

Extraction of DC delta from block 0 :

–

reading the first data bit

b2 - extraction of AC parameters

initial data stream (after header) →

Extraction of AC delta from block 0 :

0110011101100101000010000010...

first bit

–

reading the fifth data bit

initial data stream (after header) →

–

calculation of the address of the node (or leaf) of the

HUFFMAN tree :

0110011101100101000010000010...

fifth bit

The address is formed by concatenating :

D a 4-bit register containing the 4 MSB’s of the VLC

word corresponding to the preceding node of the

HUFFMAN tree (after shifting one bit right). For each

new coefficient, the register is reset to 0.

–

calculation of the address of the node (or leaf) of the

HUFFMAN tree :

The address is formed by concatenating :

D an 8-bit register containing the 8 MSB’s of the VLC

word corresponding to the preceding node of the

HUFFMAN tree (after shifting one bit right. The LSB

(bit 9) is obtained by address decoding). For each new

coefficient, the 8-bit register is reset to 0.

D the last bit extracted from the data stream

0

0 0 0 0

ADDRESS = 1st data bit (MSB) + contents of 4-bit

register = 00H

D the last bit extracted from the data stream

–

reading address 00H of the VLC DC table :

0

0 0 0 0 0 0 0 0

[@(00)] = 02H. This memory point corresponds to a node

(in line with the conventions)

ADDRESS = 1st data bit (MSB) + contents of 8-bit

register = 00H

–

right shift and load into 4-bit register :

–

reading address 00H of the VLC AC table :

= 1st data bit + contents of

the 4-bit register = 01H

0

0 0 0 0

[@(00)] = 02H. This memory point corresponds to a node

(in line with the conventions)

–

reading the 2nd data bit :

data stream →

–

right shift and load into 8-bit register :

0110011101100101000010000010..

2nd bit

0

0 0 0 0 0 0 0 1

= 1st data bit + contents

of the 8-bit register =

01H

–

concatenation with the 4-bit register :

–

reading the 6th data bit :

data stream →

1

0 0 0 1 = 11H

reading address 11H

0110011101100101000010000010...

6th bit

concatenation with the 8-bit register :

[@(11H)] = 05H. This memory point corresponds to a

leaf (in line with the conventions)

–

right shift :

1

0 0 0 0 0 0 0 1

= 101H

ssss = 2 and the DC coefficient of block 0 is 2 bits long.

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Rev. B (20/05/94)

MATRA MHS

29C82

–

reading address 101H

Note : nnnnssss = 00H corresponds to detection of an

end-of-block (EOB) character. nnnnssss = 0FH

corresponds to detection of an escape character

(15 zero coefficients). In this case one has to set

the following 15 coefficients to 0, and then

resume the decoding sequence by re-initialising

the 8-bit register to 0.

[@(101H)] = 03H. This memory point corresponds to a

leaf (in line with the conventions)

–

right shift :

nnnnssss = 00000001

D nnnn = 0. The number of zero coefficients = 0.

D ssss = 1. The first AC coefficient of block 0 is 1 bit

long.

–

extraction of the AC coefficient from the data stream :

data stream →

0110011101100101000010000010..

AC_1_bloc_0 = 1

Appendix 4

Example of Program for Creation of VLC Table

/* CONSTRUCTION OF VLC TABLES */

/*

DC TABLES

*/

void vlctable_dc (BITS, VALUE, HUFCODE, SIZE)

int

{

BITS[17] ;

VALUES[16] ;

HUFCODE[16] ;

int

PNTR ;

I,J ;

SIZO[16] ;

SI ;

WORD ;

unsigned int CODE ;

for (I=0 < 16 ; I++)

{SIZO[I] = 0 ;}

PNTR = 0 ;

for (I=1 ; I < 17 ; I++)

for (J=1 ; J<=BITS[I] ; J++)

Rev. B (20/05/94)

27

29C82

MATRA MHS

{SIZO[PNTR] = I ; PNTR ++ ;}

for (I=0 ; I < 16 ; I++)

{HUFCODE[I] = 0 ; SIZE[I] = 0 ; }

WORD = 0 ;

CODE = 0 ;

SI = SIZO[0] ;

HUFCODE[VALUES[WORD]] = CODE ;

SIZE[VALUES[WORD]] = SI ;

do

{

do

{

HUFCODE[VALUES[WORD]] = CODE ;

SIZE[VALUES[WORD]] = SI ;

CODE++ ;

WORD++ ;

}

while (SIZO[WORD] == SI) ;

if (SIZO[WORD] ! = 0)

do

{CODE = (CODE << 1) ; SI ++ ;}while (SIZO[WORD] ! = SI) ; else

{break ;}

}

while (SIZO[WORD] == SI) ;

return ;

}

/*

DC TABLES */

void vlctables_ac (BITS, VALUES, HUFCODE, SIZE)

int

{

BITS[17] ;

VALUES[256] ;

HUFCODE[256] ;

SIZE[256] ;

int

PNTR ;

I,J ;

SIZO[256] ;

SI ;

WORD ;

unsigned int CODE ;

for (I=0 ; I < 256 ; I++)

{SIZO[I] = 0 ;}

PNTR = 0 ;

for (I=1 ; I<17 ; I++)

for (J=1 ; J<=BITS[I] ; J++)

{SIZO[PNTR] = I ; PNTR ++ ;}

for (I=0 ; I < 256 ; I++)

{HUFCODE[I] = SIZE[I] = 0 ;}

WORD = 0 ;

CODE = 0 ;

SI = SIZO[0] ;

HUFCODE[VALUES[WORD]] = CODE ;

SIZE[VALUES[WORD]] = SI ;

do

{

28

Rev. B (20/05/94)

MATRA MHS

29C82

do

{

HUFCODE[VALUES[WORD]] = CODE ;

SIZE[VALUES[WORD]] = SI ;

CODE++ ;

WORD++ ;

}

while (SIZO[WORD] == SI) ;

if

}

(SIZO[WORD] ! = 0)

do

{CODE = (CODE << 1) ; SI ++ ; }while (SIZO[WORD] ! = SI) ; else

{break ;}

while (SIZO[WORD] == SI) ;

return ;

}

/*

CONSTRUCTION OF DECODING TREE

CONSTRUCTION OF DC TREE

*/

void makecodar_dc (HUFCODE, SIZE, PARR)

int

{

HUFCODE[16] ;

SIZE[16] ;

PARR[32] ;

int

INDEX ;

I ;

NEXT ;

CODENO ;

CODESIZE ;

CODELO ;

for (I=0 ;I < 32 ; I++)

{PARR[I] = 0 ;}

NEXT = 0 ;

for (CODENO = 0 ; CODENO < 16 ; CODENO++)

{

if (SIZE[CODENO] ! = 0)

{

INDEX = 0 ;

CODESIZE = SIZE[CODENO] ;

CODELO = HUFCODE[CODENO] ;

CODELO = (CODELO << (16 - CODESIZE)) ;

for (I=1; I < CODESIZE ; I++)

{

if (CODELO < 0) INDEX += 16 ;

if (PARR[INDEX] != 0) INDEX = PARR[INDEX] ; else

{

NEXT ++ ;

PARR[INDEX] = NEXT ;

INDEX = NEXT ;

}

CODELO = (CODELO << 1) ;

}

if (CODELO < 0) INDEX += 16 ;

PARR[INDEX] |= (CODENO << 8) ;

}

Rev. B (20/05/94)

29

29C82

MATRA MHS

return ;

}

/*

CONSTRUCTION OF AC TREE

*/

void makecodar_ac (HUFCODE, SIZE, PARR)

int

{

HUFCODE[256] ;

SIZE[256] ;

PARR[512] ;

int

INDEX ;

I ;

NEXT ;

CODENO ;

CODESIZE ;

CODELO ;

for (I=0 ; I < 512 ; I++)

{PARR[I] = 0 ;}

NEXT = 0 ;

for (CODENO = 0 ; CODENO < 256 ; CODENO++)

{

if (SIZE[CODENO] != 0)

{

INDEX = 0 ;

CODESIZE = SIZE[CODENO] ;

CODELO = HUFCODE[CODENO] ;

CODELO = (CODELO << (16 - CODESIZE)) ;

for (I=1 ; I < CODESIZE ; I++)

{

if (CODELO < 0) INDEX += 256 ;

if (PARR[INDEX] != 0) INDEX = PARR[INDEX] ; else

{

NEXT ++ ;

PARR[INDEX] = NEXT ;

INDEX = NEXT ;

}

CODELO = (CODELO << 1) ;

}

if (CODELO < 0) INDEX += 256 ;

PARR[INDEX] |= (CODENO << 8) ;

}

return ;

}

30

Rev. B (20/05/94)

MATRA MHS

29C82

Appendix 5

Decoupling and Layout Precautions

It is recommended that ceramic capacitors of the CMS

type should be used.

Layout precautions

In order to reduce noise, it is recommended that a card

with 4 levels of metalling be used, one level of which is

reserved as the earth plane and a second for Vcc.

In order to improve decoupling, and to compensate for

voltage peaks of inductive origin, a second 10 nF

capacitor can be placed in parallel with each 100 nF

capacitor. This additional capacitor should be placed as

close as possible to the package.

Rev. B (20/05/94)

31

29C82

Appendix 6

Application

MATRA MHS

The use of an MHS HM67202 1k × 9 FIFO enables the rising edge of WR or RD (CS active). The HFO flag must

frequency of accesses to the DATA bus to be reduced, be re-synchronised by the OSC signal (20 MHz clock)

thereby improving system flexibility.

before it is injected into the PRQ input.

The latch placed on the ADD[3..0] bus is sampled on the

32

Rev. B (20/05/94)

MATRA MHS

29C82

Appendix 7

29C82 PC Evaluation Board (8-bit)

–

Schematic

EPLD equation

Rev. B (20/05/94)

33

29C82

MATRA MHS

C22V10

{29C82 Evaluation PC-Board}

{82EPC.CYP}

{On Board Logic & IO DECODING}

{Appli.Lab – J.T – 13.11.92}

CONFIGURE

ICLK

A9

(node = 1), A11 (node = 2), A10 (node = 3),

(node = 4), A8 (node = 5), A7 (node = 6),

A3

(node = 10), /WR (node = 11), /RD (node = 13),

(node = 14, NOREG),

/RDF

/EFF

/HFF

D0

ALE

/C82

PRQ

/WRF

POUT

OCLK

(node = 15, NOREG), {Input}

(node = 16, NOREG), {Input}

(node = 17, NOREG, NINV),

(node = 18, NOREG, NINV),

(node = 19, NOREG),

(node = 20, NINV),

(node = 21, NOREG),

(node = 22, NOREG), {Input}

(node = 23, NOREG, NINV),

EQUATIONS

RDF =

{Read Control for FIFO Device. @IO = 310h to 317h.}

<oe>

<som> RD*/A11*/A10*A9*A8*/A7*/A6*/A5*A4*/A3 ;

{reading Empty Flag from FIFO. @IO = 318h to 31Fh.}

<oe> RD*/A11*/A10*A9*A8*/A7*/A6*/A5*A4*A3

<sum> /EFF ;

D0 =

C82 =

ALE =

{Chip Select Control for 29C82 Device. @IO = 300h to 30Fh.}

<oe>

<sum> /A11*/A10*A9*A8*/A7*/A6*/A5*/A4 ;

{Address Latch Enable for Latch Device type 74LS373.}

<oe>

<sum> /A11*/A10*A9*A8*/A7*/A6*/A5*RD

<sum> /A11*/A10*A9*A8*/A7*/A6*/A5*WR ;

{Write Control for FIFO Device.}

<oe>

WRF =

PRQ =

<sum> /ICLK*POUT ;

{Pixel request to 29C82 synchronized by Clock.}

{Available only if Half Full Flag from FIFO is not Present.}

<oe>

<sum> /HFF ;

OCLK =

{Clock for 29C82 synchronous with /WRF.}

<oe>

<sum> ICLK ;

34

Rev. B (20/05/94)

MATRA MHS

29C82

Rev. B (20/05/94)

35

29C82

MATRA MHS

Ordering Information

Ø

S

29C82

TEMPERATURE RANGE

Ø COMMERCIAL 0 TO 70 °C

I INDUSTRIAL -40 TO 85 °C

PACKAGE : S = PLCC

Part number

29C82

The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication

and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.

36

Rev. B (20/05/94)


型号：	IS29C82
厂家：	TEMIC SEMICONDUCTORS
描述：	Consumer Circuit, PQCC68, PLASTIC, LCC-68 商用集成电路
文件：	总36页 (文件大小：348K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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