IS29C84A [TEMIC]

Telecom Circuit, 1-Func, CMOS, PQCC68, PLASTIC, LCC-68;


型号：	IS29C84A
厂家：	TEMIC SEMICONDUCTORS
描述：	Telecom Circuit, 1-Func, CMOS, PQCC68, PLASTIC, LCC-68 电信电信集成电路
文件：	总11页 (文件大小：133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MATRA MHS

29C84A^*

Digital to Analog Video Decoder

Description

New video transmission systems like D2-MAC/packet elimination of the duplicated spectra introduced by

and ISDN are being introduced today. These new services digitization, a dematrixing stage and three D to A

are using digital coding and decoding of video signals. converters delivering the R, G, B signals.

The 29C84A is a digital to analog video processor

High frequency operation (27 MHz) is possible because

intended for conversion of composite input signals into

of parallel architecture and the 29C84A can be used for

analog red, green and blue signals. It fully complies with

a wide range of applications including still picture

the new MAC video specifications and CCIR 601

transmission at n × 64kbps (ISDN), video conference and

recommendation. The digital inputs are coded on 8 bits,

D2-MAC satellite receivers.

the luminance (Y) is sampled at 13.5 MHz and the

The digital RGB bus can be used as direct inputs to the

Triple DAC’s.

multiplexed chrominance (CR, CB) is sampled at 6.75

MHz. This sampling frequency is equivalent to 702 points

per active line in 625-line television systems.

Conversely, the outputs from the filter can be monitored

on the RGB bus, under a different mode of operation.

The 29C84A is processed in an advanced 1 µm analog

CMOS technology, it is composed of a filtering stage for

Features

D Y, CR, CB, to R, G, B decoder

D Blanking level drive capability (16)

D Programmable . 75 compensation factor for D2-MAC

standard

D Digital to analog converters for R, G, B

D Elimination of duplicated spectra by oversampling

D 7th Order chrominance filter with programmable cutoff (1,

1.3, 1.6 and 2MHz)

D Frame interleave capability

D Maximum operating frequency = 27MHz

D 75 Ohms/20pF load capability for DAC’s

D Single 5V supply

D 19th order luminance filter

D Compatibility with CCIR 601 recommendation and MAC

standard

D 1 µm analog CMOS technology

D Package : PLCC68

D External R, G, B digital to analog conversion capability (TV

picture and alphanumeric characters mixing capability)

* 29C84 is under CNET licence.

Rev. B (07/06/94)

29C84A

MATRA MHS

Interface

Block Diagram

R 0..7

0..7

COM0

COM1

TRIM

REXT

VREF2

X 1.3

BUFFER

Bi-Dir.

REXT

VREF.

VREF1

CK/2

CK/4

SYNC

Log.

TIMING

GENERATOR

SYNC

CK/2

CORREC

TION

DAC

MUX

RED

LIMINANCE

FILTER

0..7

SATURATION

CORREC

TION

MUX

DAC

CK/4

CK/2

GREEN

BLUE

INTERPOLATION

FILTER

Y, CR, CB

R, G, B

CORREC

TION

CR, C8

0..7

CHOMINANCE

FILTER

INTERPOLATION

FILTER

O/EF

Pin Configuration

Rev. B (07/06/94)

MATRA MHS

29C84A

Pin Description

Pin No

Name

Function

Direction

SYNC

C K

CR, CB VALIDATION CLOCK

SYSTEM CLOCK (27MHz)

LUMINANCE

3..10

Y[7..0]

CR[7...0]

DGND

DVCC

14..21

MULTIPLEXED CHROMINANCE CR, CB

DIGITAL GROUND

12, 25, 56, 68

SUPPLY

11, 45, 59

DIGITAL POSITIVE SUPPLY (5 V)

COM1

COM0

A0, A1

X1.3

DAC’S INPUT SELECT

23, 24

CHROMINANCE FILTER CUTOFF SELECT

D2–MAC COMPENSATION SELECT

1/2 CK DELAY PROGRAMMATION (ODD/EVEN FRAME)

BLUE DIGITAL PROGRAMMABLE BUS

GREEN DIGITAL PROGRAMMABLE BUS

RED DIGITAL PROGRAMMABLE BUS

O/E F

28..35

37..44

60..67

B[7..0]

G[7..0]

R[0..7]

I/O

BAGND

BLUE

GAGND

GREEN

AVCC

RAGND

RED

BLUE ANALOG GROUND

SUPPLY

BLUE ANALOG OUTPUT

GREEN ANALOG GROUND

GREEN ANALOG OUTPUT

SUPPLY

ANALOG POSITIVE SUPPLY (5V)

RED ANALOG GROUND

SUPPLY

RED ANALOG OUTPUT

SUPPLY

REXT

VREF2

VREF1

TRIM

DAC CURRENT REGULATION

MAIN REFERENCE VOLTAGE (VREF2 – VREF1 = 815 mV)

LOWER REFERENCE VOLTAGE

VREF1 TRIMMING POINT

Rev. B (07/06/94)

29C84A

MATRA MHS

Functional Description

Digital Part

The digital part includes two stages : the first one is a filter over-sampled Y, CR, CB into R, G, B components

increasing the sampling rates of the luminance and the according to CCIR 601 recommendation. Two external

chrominance, and the second one is a video matrix clocks are used : CK (27 MHz) for system clock and

operator which performs the conversion of the SYNC for input signals synchronization.

All internal registers are clocked on the falling edge of The filter block performs an interpolation by two for

CK clock. Internal data paths have been scaled to allow luminance signal (Y) and by a factor 4 for each

output data in the range [0,255/256] for R, G, B and input chrominance signal CR and CB.

data in the range [00, FF] for Y, CR, CB. Saturation

circuits are used for out of range data, rounding functions

are performed before truncation.

This operation is equivalent to computing of one

intermediate point between each incoming luminance

sample and three for the two chrominance samples.

1/Fy

1/FY*

* CK clock frequency = 2 Fy

ANALOG

DIGITAL

INPUTS

OVERSAMPLING

FILTERS

DEMATRIXING

OPERATOR

DIGITAL TO ANALOG

CONVERTERS

OUTPUTS

CR, CB

R, G, B

2Fy

Fy/2

3Fy/2

2Fy

In order to be compatible with CCIR 601 all filters must CB). FIR (non recursive) filters with linear phase have

have a linear phase and a flat response within the been used and no phase correction is required.

frequency band (5.5 MHz for Y and 2 MHz for CR and

Rev. B (07/06/94)

MATRA MHS

29C84A

Luminance Filter

The luminance filter is a 19th order transversal linear

filter :

a7 = –.0234375

a9 = .0078125

–1

–3

H (Z) = a0 + a1 (z + z ) + a3 (z + z )

The selection of the coefficients takes into account the sin

(x)/x attenuation introduced by the DAC’s

sample-and-hold function.

–5)

–7

–9

+ a5 (z + z + a7 (z + z ) + a9 (z + z )

with : a0 = .5

a1 = .328125

a3 = –.117875

a5 = .054687

The incoming and outgoing data flows are 8 bit wide with

values in the [00, FF] range.

Luminance Filter Block Diagram

INPUT Y

8b (Fy)

MUX

_{Yn +}ȍ_{ai @ X n–i}

(

)

i+–9

OUTPUT Y

8b (2Fy)

(CK = 2Fy)

Luminance and Chrominance Filter Measurements (CK = 27 MHz)

–10

–20

–30

–40

3.375 MHz

6.75 MHz

10.125 MHz

13.5 MHz

Rev. B (07/06/94)

29C84A

MATRA MHS

Chrominance Filters

CUTOFF

1 MHz

The chrominance filter is made with one 7 th order

symetrical filter for multiplexed CR/CB and two separate

2nd order filters for CR and CB.

1.3 MHz

1.6 MHz

2 MHz

The 7 th order filter transfer fonction is :

–1

–2

H (Z) = ho + h1 (Z + Z ) + h2 (Z + Z )

+ h3 (Z + Z )

–3

The corresponding coefficients are :

In a MAC decoder the chrominance filter passband is a

compromise between the colour resolution and noise.

h01 = .011110 h02 = .10010 h03 = .10110 h04 = .11010

h11 = .011000 h12 = .01110 h13 = .01111 h14 = .10010

h21 = .010001 h22 = .00111 h23 = .00101 h24 = .00011

h31 = .001000 h32 = .00010 h33 = .00001 h34 = -.00010

For this reason each subfilter is composed of 4 different

Bessel filters with a cutoff frequency of 1, 1.3, 1.6 and 2

MHz. The real time noise measurement on a MAC test

line can be used to select one of the four colour filters

through A0, A1 pins.

The second order filter transfer function is :

–1

H(Z) = .5(Z + 2 + Z )

Chrominance Filter Block Diagram

Matrix Operator

The matrix operator is in charge of Y, CR, CB → R, G, B B = 1.000 × Y + .000 × (CR–.5) + 1.730 × (CB–.5)

conversion according to CCIR 601 recommendation.

A ROM architecture has been used to achieve fast

R = 1.000 × Y + 1.370 × (CR–.5) + .000 × (CB–.5)

G = 1.000 × Y –.698 × (CR–.5) –.336 × (CB–.5)

multiplications (27 MHz). In order to improve speed this

256-word ROM has been split into 8 × 16-word ROM’s.

Rev. B (07/06/94)

MATRA MHS

29C84A

Dematrixing Operator Architecture and 1.333... Division

8b/2Fy

ROM1

1.37 (CR – 0.5)

8b/2Fy

–0.698 (CR – 0.5)

Y + 1.37 (CR – 0.5)

MUX

1.37 (CR)

–0.698 (CR)

–0.336 (CB – 0.5)

1.73 (CB – 0.5)

8b/2Fy

Y – 0.698 (CR – 0.5)

–0.336 (CB – 0.5)

MUX

–0.336 (CB)

1.73 (CB)

MAC (x .75)

8 x 16 Words ROMs

Y + 1.73 (CB – 0.5)

The R, G, B signal can be delayed by 1 Clock Period at as a voltage divider. The internal reference voltage for the

the output of the matrix operator using the O/E F external 3 converters is V –V = 815 mV. This voltage

REF2

REF1

command in order to allow frame interleaving in corresponds to the standard 700 mV range of a video

staggered rows.

signal from black to white (levels 16 and 235 in CCIR

601). In order to reduce the diaphony between the DAC’s,

these shared reference voltages are filtered by on chip

capacitors. However, additional 1 µF capacitors are

required on VREF1, VREF2 and TRIM for better

decoupling, and stability.

O/EF

DELAY

no delay

1 Clock delay (37 nS at 27 MHz)

In order to improve signal/noise ratio and according to the

D2-MAC standard the chrominance signals are

multiplied by 1.333 before transmission.

Each of the three DAC outputs is connected to an

operational amplifier used as a unity-gain buffer to drive

75 ohms/20 pF loads.

A compensation (multiplication by .75 of R, G, B) can be

programmed on the reception side through × 1.3 pin.

The REXT pin must be tied to a 10 k resistor under normal

conditions. Changing the value of REXT modifies output

amplifier characteristics (slew rate, passband ...).

X 1.3

MULT. FACTOR

3 optional intermediate input/output ports have been

implemented between the matrix operator and the DAC’s.

The converters inputs can be connected to external digital

R, G, B sources. This connection is programmed through

C0, C1 pins. A typical application in this mode is

videotext where TV picture and alphanumeric characters

defined by their R, G, B components have to be mixed.

multiplication by .75

no multiplication

Analog Part

Three 8bit D to A converters deliver analog R, G, B

signals. Each converter is based on a resistor string used The input/output ports can be programmed as follows :

COM1

COM0

DAC Programmation

FILTER + DEMATRIXING + DAC mode. Internal filters are connected to DAC inputs.R[0..7],

G[0..7], B[0..7] bus are floating.

TRIPLE/DAC MODE. Filters are not connected to DAC’s. R[0..7], G[0..7], B[0..7] are con-

nected to DAC inputs

FILTER + DEMATRIXING + DAC + MONITORING MODE. Filters are connected to DAC

inputs and to R[0..7], G[0..7], B[0..7] bus

BLANKING MODE DACs inputs are forced to 16 (blanking level) and R[0..7], G[0..7], B[0..7]

are floating.

Rev. B (07/06/94)

29C84A

MATRA MHS

Application Information

Rev. B (07/06/94)

MATRA MHS

29C84A

Electrical Characteristics

Absolute Maximum Ratings

Operating Conditions

VCC to GND : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V

input/output voltage : . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150 °C

Voltage range : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5 V

Temperature range : . . . . . . . . . . . . . . . . . . . . . . . . . . . . T = 0 to 70°C

DC Electrical Characteristics

VCC = 5 V, T = 25°C

Typical Load for DAC’s = 75 Ω, 20 pF

Parameter

Min

Typ

Max

Unit

Conditions

LOW LEVEL INPUT VOLTAGE VIL

HIGH LEVEL INPUT VOLTAGE VIH

LOW LEVEL OUTPUT VOLTAGE VOL

HIGH LEVEL OUTPUT VOLTAGE VOH

LOW LEVEL OUTPUT CURRENT IOL

HIGH LEVEL OUTPUT CURRENT IOH

INPUT LEAKAGE CURRENT IIL/IIH

OPERATING CURRENT ICCD

3.5

IOL = –4.8MA

IOH = 5MA

4.8

VOL = 0.4V

VOL = 2.4V

VIN = VCC OR 0V

LOAD = 75 0HMS OUTPUT

CODE = 80 H

OUTPUT OPAMP SLEW RATE

OUTPUT AMP UNITY GBW

DAC’S ABSOLUTE LINEARITY

100

140

V/US

MHz

LSB

IO – 90 % OF THE 00H TO FFH

DIFFERENTIAL AND

INTEGRAL

DIAPHONY BETWEEN DACS

–75 –45

DB DB

LOW FREQ 10 KHz HIGH FREQ

1 MHz

GLITCH ENERGY

NS.LSB

TRANSITION 80 → 7F

HARMONIC DISTORSION

PSRR (All Analog Pins)

200 KHz

LOW FREQ 10 KHZ

HIGH FREQ 1 MHZ

VREF1

0.345

1.16

775

0.405

1.22

815

0.465

1.28

855

VREF2

VREF2–VREF1

TEMP COEFF OF (VREF2–VREF1)

200

ppm/_C

0-70_C

Rev. B (07/06/94)

29C84A

MATRA MHS

Timings

AC Electrical Characteristics

VCC = 5 V ± 10 %, T = 0 to 70°C, CL = 20 pF on R, G, B

Symbol

Parameter

input/CK low data setup time

input/CK low data hold time

minimum CK cycle time

CK low to SYNC low

Condition

Min

10 ns

0 ns

Typ

Max

thmin

ts0min

ts1min

ts2min

ts3min

tr max

37 ns

5 ns

SYNC low to CK low

8 ns

CK low to SYNC high

4 ns

SYNC high to CK low

7 ns

CK low to R, G, B outputs propagation

delay

.5 vref

20 ns

ted max

tem max

tcp

DAC settling time full scale to 0

DAC settling time 0 to full scale

COM [0..1] to CK low setup time

COM [0..0] from CK low hold time

to 1/2 lsb

30 ns

20 ns

22 ns

0 ns

tcm

Application recommendation

The DAC O/P loads should have minimal capacitance load (20 pF typ, 50 pF maximum).

The resistor content can be either 75 Ω or 50 Ω.

Rev. B (07/06/94)

MATRA MHS

29C84A

Ordering Information

29C84A

TEMPERATURE RANGE

Ø COMMERCIAL 0 TO 70 °C

I INDUSTRIAL -40 TO 85 °C

PACKAGE : S = PLCC

Part number

29C84A

The information contained herein is subject to change without notice. No responsibility is assumed by MATRA MHS SA for using this publication

and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.

Rev. B (07/06/94)

IS29C84A [TEMIC]

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