ITG-3701 [TDK]
陀螺仪;
| 型号： | ITG-3701 |
| 厂家： | 
TDK ELECTRONICS |
| 描述： | 陀螺仪 |
| 文件： | 总34页 (文件大小：3995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
InvenSense Inc.
Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
1745 Technology Drive, San Jose, CA 95110 U.S.A.
Tel: +1 (408) 988-7339 Fax: +1 (408) 988-8104
Website: www.invensense.com
ITG-3701
Product Specification
Revision 1.0
Confidential & Proprietary
1 of 34
Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
CONTENTS
1ꢀ DOCUMENT INFORMATION ....................................................................................................................4ꢀ
1.1ꢀ
1.2ꢀ
1.3ꢀ
1.4ꢀ
REVISION HISTORY ................................................................................................................................................. 4ꢀ
PURPOSE AND SCOPE ............................................................................................................................................. 4ꢀ
PRODUCT OVERVIEW .............................................................................................................................................. 4ꢀ
APPLICATIONS ........................................................................................................................................................ 4ꢀ
2ꢀ POWER MANAGEMENT FEATURES ......................................................................................................5ꢀ
2.1ꢀ
2.2ꢀ
2.3ꢀ
2.4ꢀ
2.5ꢀ
2.6ꢀ
SENSORS ............................................................................................................................................................... 5ꢀ
DIGITAL OUTPUT..................................................................................................................................................... 5ꢀ
DATA PROCESSING ................................................................................................................................................. 5ꢀ
CLOCKING .............................................................................................................................................................. 5ꢀ
POWER .................................................................................................................................................................. 5ꢀ
PACKAGE ............................................................................................................................................................... 5ꢀ
3ꢀ ELECTRICAL CHARACTERISTICS .........................................................................................................6ꢀ
3.1ꢀ
3.2ꢀ
3.3ꢀ
3.4ꢀ
3.5ꢀ
3.6ꢀ
SENSOR SPECIFICATIONS ........................................................................................................................................ 6ꢀ
ELECTRICAL SPECIFICATIONS................................................................................................................................... 7ꢀ
ELECTRICAL SPECIFICATIONS, CONTINUED ................................................................................................................ 8ꢀ
I2C TIMING CHARACTERIZATION ............................................................................................................................... 9ꢀ
SPI TIMING CHARACTERIZATION............................................................................................................................. 10ꢀ
ABSOLUTE MAXIMUM RATINGS............................................................................................................................... 11ꢀ
4ꢀ APPLICATIONS INFORMATION ............................................................................................................12ꢀ
4.1ꢀ
4.2ꢀ
4.3ꢀ
PIN OUT AND SIGNAL DESCRIPTION........................................................................................................................ 12ꢀ
TYPICAL OPERATING CIRCUIT ................................................................................................................................ 13ꢀ
BILL OF MATERIALS FOR EXTERNAL COMPONENTS................................................................................................... 13ꢀ
5ꢀ FUNCTIONAL OVERVIEW......................................................................................................................14ꢀ
5.1ꢀ
5.2ꢀ
5.3ꢀ
5.4ꢀ
5.5ꢀ
5.6ꢀ
5.7ꢀ
5.8ꢀ
5.9ꢀ
BLOCK DIAGRAM................................................................................................................................................... 14ꢀ
OVERVIEW ........................................................................................................................................................... 14ꢀ
THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING ..................................................... 14ꢀ
I2C AND SPI SERIAL COMMUNICATIONS INTERFACE ................................................................................................. 14ꢀ
INTERNAL CLOCK GENERATION .............................................................................................................................. 15ꢀ
SENSOR DATA REGISTERS .................................................................................................................................... 15ꢀ
FIFO................................................................................................................................................................... 15ꢀ
INTERRUPTS ......................................................................................................................................................... 15ꢀ
DIGITAL-OUTPUT TEMPERATURE SENSOR............................................................................................................... 15ꢀ
5.10ꢀ BIAS AND LDO ..................................................................................................................................................... 15ꢀ
6ꢀ DIGITAL INTERFACE .............................................................................................................................16ꢀ
6.1ꢀ
7ꢀ SERIAL INTERFACE CONSIDERATIONS.............................................................................................21ꢀ
I2C SERIAL INTERFACE .......................................................................................................................................... 16ꢀ
7.1ꢀ
7.2ꢀ
SUPPORTED INTERFACES....................................................................................................................................... 21ꢀ
LOGIC LEVELS ...................................................................................................................................................... 21ꢀ
8ꢀ ASSEMBLY .............................................................................................................................................22ꢀ
8.1ꢀ
8.2ꢀ
8.3ꢀ
8.4ꢀ
8.5ꢀ
8.6ꢀ
8.7ꢀ
8.8ꢀ
8.9ꢀ
ORIENTATION OF AXES .......................................................................................................................................... 22ꢀ
PACKAGE DIMENSIONS .......................................................................................................................................... 23ꢀ
PCB DESIGN GUIDELINES ..................................................................................................................................... 23ꢀ
PRODUCT MARKING SPECIFICATION........................................................................................................................ 25ꢀ
TAPE & REAL SPECIFICATION................................................................................................................................. 25ꢀ
ASSEMBLY PRECAUTIONS ...................................................................................................................................... 27ꢀ
STORAGE SPECIFICATIONS .................................................................................................................................... 30ꢀ
LABEL .................................................................................................................................................................. 30ꢀ
PACKAGING .......................................................................................................................................................... 31ꢀ
8.10ꢀ REPRESENTATIVE SHIPPING CARTON LABEL............................................................................................................ 32ꢀ
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
9ꢀ RELIABILITY ...........................................................................................................................................33ꢀ
9.1ꢀ
9.2ꢀ
QUALIFICATION TEST POLICY ................................................................................................................................. 33ꢀ
QUALIFICATION TEST PLAN .................................................................................................................................... 33ꢀ
10ꢀ
ENVIRONMENTAL COMPLIANCE .....................................................................................................34ꢀ
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
1
Document Information
1.1 Revision History
Date
Revision
Description
12/13/2013
1.0
Initial Release
1.2 Purpose and Scope
This document is a preliminary product specification, providing a description, specifications, and design
related information for the three axis ITG-3701™ gyroscopes. The device is housed in a small 3x3x0.75mm
QFN package.
Specifications are subject to change without notice. Final specifications will be updated based upon
characterization of production silicon. For references to register map and descriptions of individual registers,
please refer to the ITG-3701 Register Map and Register Descriptions document.
1.3 Product Overview
The ITG-3701 is a single-chip, digital output, 3 Axis MEMS gyroscope IC which features a 512-byte FIFO.
The FIFO can lower the traffic on the serial bus interface, and reduce power consumption by allowing the
system processor to burst read sensor data and then go into a low-power mode.
The gyroscope includes a programmable full-scale range of ±500, ±1000, ±2000, and ±4000 degrees/sec,
very low Rate noise at 0.02 dps/√Hz and extremely low power consumption at 3.3mA. Factory-calibrated
initial sensitivity reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, a precision clock
with 1% drift from -40°C to 85°C, an embedded temperature sensor, and programmable interrupts. The
device features I2C and SPI serial interfaces, a VDD operating range of 1.71 to 3.6V, and a separate digital
IO supply, VDDIO from 1.71V to 3.6V.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS
wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the gyro
package size down to a footprint and thickness of 3x3x0.75mm (16-pin QFN), to provide a very small yet
high performance low cost package. The device provides high robustness by supporting 10,000g shock
reliability.
1.4 Applications
•
•
•
Health and sports monitoring
Motion UI
Handset gaming
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
2
Power management Features
The ITG-3701 MEMS gyroscope includes a wide range of features:
2.1 Sensors
•
•
•
Monolithic angular rate sensor (gyros) integrated circuit
Digital-output temperature sensor
External sync signal connected to the FSYNC pin supports image, video and GPS
synchronization
•
•
•
Factory calibrated scale factor
High cross-axis isolation via proprietary MEMS design
10,000g shock tolerant
2.2 Digital Output
•
•
•
•
•
Fast Mode (400kHz) I2C serial interface
1 MHz SPI serial interface for full read/write capability
20 MHz SPI to read gyro sensor & temp sensor data.
16-bit ADCs for digitizing sensor outputs
User-programmable full-scale-range of ±500°/sec, ±1000°/sec, ±2000°/sec and ±4000°/sec
2.3 Data Processing
•
The total data set obtained by the device includes gyroscope data, temperature data, and the one
bit external sync signal connected to the FSYNC pin.
FIFO allows burst read, reduces serial bus traffic and saves power on the system processor.
FIFO can be accessed through both I2C and SPI interfaces.
Programmable interrupt
•
•
•
•
Programmable low-pass filters
2.4 Clocking
•
On-chip timing generator clock frequency ±1% drift over full temperature range
2.5 Power
•
•
VDD supply voltage range of 1.71V to 3.6V
Flexible VDDIO reference voltage allows for multiple I2C and SPI interface voltage levels
Power consumption for three axes active: 3.3mA
Sleep mode: 8µA
•
•
•
Each axis can be individually powered down
2.6 Package
•
•
•
3x3x0.75mm footprint and maximum thickness 16-pin QFN plastic package
MEMS structure hermetically sealed at wafer level
RoHS and Green compliant
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
3
Electrical Characteristics
3.1 Sensor Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA=25°C.
Parameter
Conditions
Min
Typical
Max
Unit
Notes
GYRO SENSITIVITY
Full-Scale Range
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
±500
±1000
±2000
±4000
º/s
º/s
º/s
º/s
Sensitivity Scale Factor
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
65.5
32.8
16.4
8.2
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
LSB/(º/s)
Gyro ADC Word Length
16
±3
±4
bits
%
Sensitivity Scale Factor Tolerance
25°C
Sensitivity Scale Factor Variation Over
Temperature
-10°C to +75°
%
Nonlinearity
Best fit straight line; 25°C
±0.3
±5
%
%
Cross-Axis Sensitivity
GYRO ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C
±15
±15
º/s
º/s
ZRO Variation Over Temperature
-10°C to +75°C
GYRO NOISE PERFORMANCE
Total RMS Noise
FS_SEL=0
DLPFCFG=2 (1-100Hz)
At 10Hz
0.2
º/s-rms
Rate Noise Spectral Density
0.02
º/s/√Hz
GYRO MECHANICAL
Mechanical Frequency
25
27
29
kHz
GYRO START-UP TIME
DLPFCFG=0, to ±1º/s of Final
ZRO Settling
From Sleep Mode to ready
From Power On to ready
35
50
ms
ms
TEMPERATURE SENSOR
Range
Sensitivity
Untrimmed
21°C
-10 to +75
321.4
ºC
LSB/ºC
Room-Temperature Offset
Linearity
0
LSB
°C
±0.2
TEMPERATURE RANGE
Specification Temperature Range
-10
+75
ºC
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
3.2 Electrical Specifications
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA = 25°C.
Parameters
Conditions
Min
Typical
Max
Units
Notes
VDD POWER SUPPLY
Operating Voltage Range
1.71
1
3.6
V
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
Power-Supply Ramp Rate
100
ms
Normal Operating Current
Sleep Mode Current
Three Axes Active
3.3
8
mA
µA
VDDIO REFERENCE VOLTAGE
(must be regulated)
Voltage Range
1.71
0.1
3.6
V
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value
Power-Supply Ramp Rate
Normal Operating Current
100
ms
10pF load, 5MHz data rate.
Does not include pull up
resistor current draw as
that is system dependent
300
12
µA
START-UP TIME FOR REGISTER
READ/WRITE
Ready to access registers
ms
AD0 = 0
AD0 = 1
1101000
1101001
I2C ADDRESS
DIGITAL INPUTS (FSYNC, AD0,
SCLK, SDI, /CS)
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
0.7*VDDIO
0.9*VDDIO
V
V
0.3*VDDIO
< 5
pF
DIGITAL OUTPUT (INT, SDO)
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT1, INT Low-Level Output Voltage
RLOAD=1MΩ
V
V
V
RLOAD=1MΩ
OPEN=1, 0.3mA sink
current
0.1*VDDIO
0.1
Output Leakage Current
tINT, INT Pulse Width
OPEN=1
100
50
nA
LATCH_INT_EN=0
µs
.
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
3.3 Electrical Specifications, continued
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA=25°C.
Parameters
Conditions
Min
Typical
Max
Units Notes
I2C I/O (SCL, SDA)
-0.5V to 0.3*VDDIO
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
V
V
0.7*VDDIO to VDDIO +
0.5V
Vhys, Hysteresis
0.1*VDDIO
0 to 0.4
V
V
VOL1, LOW-Level Output Voltage
IOL, LOW-Level Output Current
3mA sink current
VOL = 0.4V
VOL = 0.6V
3
6
mA
mA
Output Leakage Current
100
20+0.1Cb to 250
< 10
nA
ns
pF
tof, Output Fall Time from VIHmax to VILmax
CI, Capacitance for Each I/O pin
INTERNAL CLOCK SOURCE
Cb bus capacitance in pf
Fchoice=0,1,2
SMPLRT_DIV=0
32
8
kHz
kHz
Fchoice=3;
DLPFCFG=0 or 7
SMPLRT_DIV=0
Sample Rate
Fchoice=3;
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
1
kHz
Clock Frequency Initial Tolerance
Frequency Variation over Temperature
PLL Settling Time
CLK_SEL=0, 6; 25°C
CLK_SEL=1,2,3,4,5; 25°C
CLK_SEL=0,6
-2
-1
+2
+1
%
%
-10 to +10
%
CLK_SEL=1,2,3,4,5
CLK_SEL=1,2,3,4,5
±1
4
%
ms
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
3.4 I2C Timing Characterization
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA=25°C.
Parameters
I2C TIMING
Conditions
I2C FAST-MODE
Min
Typical
Max
Units
Notes
2
fSCL, SCL Clock Frequency
0
400
kHz
tHD.STA, (Repeated) START Condition
Hold Time
0.6
µs
tLOW, SCL Low Period
tHIGH, SCL High Period
1.3
0.6
0.6
µs
µs
µs
tSU.STA, Repeated START Condition
Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
0
µs
ns
ns
100
Cb bus cap. from 10 to
400pF
Cb bus cap. from 10 to
400pF
20+0.1
Cb
20+0.1
Cb
300
300
tf, SDA and SCL Fall Time
ns
tSU.STO, STOP Condition Setup Time
0.6
µs
µs
tBUF, Bus Free Time Between STOP and
START Condition
1.3
Cb, Capacitive Load for each Bus Line
< 400
pF
µs
µs
tVD.DAT, Data Valid Time
0.9
0.9
tVD.ACK, Data Valid Acknowledge Time
I2C Bus Timing Diagram
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
3.5 SPI Timing Characterization
Typical Operating Circuit of Section 4.2, VDD = 2.5V, VDDIO = 1.8V, TA = 25°C.
Notes
Parametersꢀ
Conditionsꢀ
Minꢀ
Typicalꢀ
Maxꢀ
Unitsꢀ
ꢀ
SPIꢀTIMINGꢀ(fSCLKꢀ=ꢀ1ꢀMHz)ꢀR/Wꢀ
fSCLK,ꢀSCLKꢀClockꢀFrequencyꢀꢀ
tLOW,ꢀSCLKꢀLowꢀPeriodꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1ꢀ
MHzꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
400ꢀ
400ꢀ
8ꢀ
ꢀ
ꢀ
tHIGH,ꢀSCLKꢀHighꢀPeriodꢀ
tSU.CS,ꢀCSꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tHD.CS,ꢀCSꢀHoldꢀTimeꢀ
ꢀ
500ꢀ
11ꢀ
7ꢀ
ꢀ
ꢀ
tSU.SDI,ꢀSDIꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tHD.SDI,ꢀSDIꢀHoldꢀTimeꢀ
ꢀ
ꢀ
tVD.SDO,ꢀSDOꢀValidꢀTimeꢀ
tHD.SDO,ꢀSDOꢀHoldꢀTimeꢀ
tDIS.SDO,ꢀSDOꢀOutputꢀDisableꢀTimeꢀ
tBUF,ꢀCSꢀhighꢀtimeꢀbetweenꢀtransactionsꢀꢀ
Cloadꢀ=ꢀ20pFꢀ
ꢀ
ꢀ
100ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
50ꢀ
600ꢀ
nsꢀ
nsꢀ
ꢀ
ꢀ
Notes
Parametersꢀ
Conditionsꢀ
Minꢀ
Typicalꢀ
Maxꢀ
Unitsꢀ
ꢀ
SPIꢀTIMINGꢀ(fSCLKꢀ=ꢀ20ꢀMHz)ꢀRead3ꢀ
fSCLK,ꢀSCLKꢀClockꢀFrequencyꢀ
tLOW,ꢀSCLKꢀLowꢀPeriodꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
MHzꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
nsꢀ
ꢀ
ꢀ
-ꢀ
-ꢀ
25ꢀ
-ꢀ
tHIGH,ꢀSCLKꢀHighꢀPeriodꢀ
ꢀ
25ꢀ
-ꢀ
tSU.CS,ꢀCSꢀSetupꢀTimeꢀ
ꢀ
25ꢀ
25ꢀ
5ꢀ
6ꢀ
ꢀ
ꢀ
ꢀ
tHD.CS,ꢀCSꢀHoldꢀTimeꢀ
ꢀ
ꢀ
ꢀ
tSU.SDI,ꢀSDIꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tHD.SDI,ꢀSDIꢀHoldꢀTimeꢀ
ꢀ
ꢀ
tVD.SDO,ꢀSDOꢀValidꢀTimeꢀ
Cloadꢀ=ꢀ20pFꢀ
ꢀ
30ꢀ
ꢀ
tHD.SDO,ꢀSDOꢀHoldꢀTimeꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
ꢀ
ꢀ
tDIS.SDO,ꢀSDOꢀOutputꢀDisableꢀTimeꢀ
tBUF,ꢀCSꢀhighꢀtimeꢀbetweenꢀtransactionsꢀꢀ
ꢀ
25ꢀ
600ꢀ
nsꢀ
nsꢀ
ꢀ
ꢀ
ꢀ
/CS
SCLK
SDI
SDO
SPI Bus Timing Diagram
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
3.6 Absolute Maximum Ratings
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these conditions is not implied.
Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
Parameter
Rating
Supply Voltage, VDD
-0.5V to 4.0V
-0.5V to 4.0V
VDDIO Input Voltage Level
REGOUT
-0.5V to 2V
Input Voltage Level (AD0, FSYNC)
SCL, SDA, INT (SPI enable)
SCL, SDA, INT (SPI disable)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Protection
Latch-up
-0.5V to VDDIO
-0.5V to VDDIO
-0.5V to VDDIO
10,000g for 0.2ms
-40°C to +85°C
-40°C to +125°C
2kV (HBM); 250V (MM)
JEDEC Class II (2),125°C, ±100mA
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
4
Applications Information
4.1 Pin Out and Signal Description
Pin Number
Pin Name
Pin Description
I2C serial data (SDA); SPI serial data input (SDI)
3x3x0.75mm
1
SDA/SDI
VDDIO
/CS
3
I/O supply voltage.
SPI chip select (0=SPI mode, 1= I2C mode)
4
5
RESV
Reserved. Do not connect.
6
AD0 / SDO
REGOUT
FSYNC
VDD
I2C Slave Address LSB (AD0); SPI serial data output (SDO)
Regulator filter capacitor connection
7
8
Frame synchronization digital input. Connect to GND if not used.
Power supply voltage
9
10
INT
Interrupt digital output (totem pole or open-drain)
Power supply ground
12
GND
14
16
RESV-G
SCL/SCLK
NC
Reserved. Connect to Ground.
I2C serial clock (SCL); SPI serial clock (SCLK)
2, 11, 13, 15
Not internally connected. May be used for PCB trace routing.
16 15 14 13
GND
SDA/SDI
1
2
3
4
12
+Z
ITG-3701
(16-pin QFN)
NC
VDDIO
/CS
11 NC
10 INT
I
T
G
-
3
7
0
1
9
VDD
+Y
+X
5
6
7
8
QFN Package (Top View)
16-pin, 3mm x 3mm x 0.75mm
Footprint and maximum thickness
Orientation of Axes of Sensitivity and Polarity of Rotation
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
4.2 Typical Operating Circuit
16 15 14 13
SDA/SDI
1
2
3
4
12
11
10
9
ITG-3701
(16-pin QFN)
GND
INT
VDDIO
VDD
C3
10nF
C2
0.1µF
GND
5
6
7
8
/CS
GND
C1
0.1µF
GND
Typical Operating Circuit
4.3 Bill of Materials for External Components
Component
Label
C1
Specification
Quantity
Regulator Filter Capacitor
VDD Bypass Capacitor
VDDIO Bypass Capacitor
Ceramic, X7R, 0.1µF ±10%, 2V
Ceramic, X7R, 0.1µF ±10%, 4V
Ceramic, X7R, 10nF ±10%, 4V
1
1
1
C2
C3
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5
Functional Overview
5.1 Block Diagram
VDD
CLOCK
Gen
Factory
Test Modes
OTP Factory
Calibration
POR
VDDIO
REGOUT
CSN
IIC SLAVE
AD0 / SDO
Drive block
GND
Sensing Block
SCL / SCLK
SDA / SDI
SPI SLAVE
Digital Low Pass Filter OIS
ADC
ADC
ADC
ADC
CV
CV
CV
Single
XYZ
GYRO
Drive
FIFO
INTC
SENSOR
Digital Low Pass Filter OIS
OUTPUT
REGS
DRDY
Digital Low Pass Filter OIS
Digital Low Pass Filter
INT
FSYNC
Temp
Sensor
Status
Registers
Automatic Gain
Control
Charge
Pump
Reference
Gen
Voltage
Regulator
Control
Registers
Self test
Trims and config ckts
5.2 Overview
The ITG-3701 is comprised of the following key blocks / functions:
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
I2C and SPI serial communications interfaces
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDO
5.3 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning
The ITG-3701 consists of a single structure vibratory MEMS rate gyroscope, which detects rotation about the
XY&Z axes, respectively. When the gyro is rotated about any of the sense axes, the Coriolis Effect causes a
vibration that is detected by a capacitive pick off. The resulting signal is amplified, demodulated, and filtered
to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip
16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The chip features a programmable full-
scale range of the gyro sensors of ±500, ±1000, ±2000, and ±4000 dps. User-selectable low-pass filters
enable a wide range of cut-off frequencies. The ADC sample rate can be programmed to 32 kHz, 8 kHz, 1
kHz, 500 Hz, 333.3 Hz, 250 Hz, 200 Hz, 166.7 Hz, 142.9 Hz, or 125 Hz.
5.4 I2C and SPI Serial Communications Interface
The ITG-3701 has both I2C and SPI serial interfaces. The device always acts as a slave when
communicating to the system processor. The logic level for communications to the master is set by the
voltage on the VDDIO pin. The LSB of the of the I2C slave address is set by the AD0 pin. The I2C and SPI
protocols are described in more detail in Section 6.
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5.5 Internal Clock Generation
The ITG-3701 uses a flexible clocking scheme, allowing for a variety of internal clock sources for the internal
synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, various control
circuits, and registers.
Allowable internal sources for generating the internal clock are:
•
•
An internal relaxation oscillator
PLL (gyroscope based clock)
In order for the gyroscope to perform to spec, the PLL must be selected as the clock source. When the
internal 20MHz oscillator is chosen as the clock source, the device can operate while having the gyroscope
disabled. However, this is only recommended if the user wishes to use the internal temperature sensor in this
mode.
5.6 Sensor Data Registers
The sensor data registers contain the latest gyro and temperature data. They are read-only registers, and
are accessed via the Serial Interface. Data from these registers may be read anytime, however, the interrupt
function may be used to determine when new data is available.
5.7 FIFO
The ITG-3701 contains a 512-byte FIFO register that is accessible via the both the I2C and SPI Serial
Interfaces. The FIFO configuration register determines what data goes into it, with possible choices being
gyro data, temperature readings and FSYNC input. A FIFO counter keeps track of how many bytes of valid
data are contained in the FIFO. The FIFO register supports burst reads. The interrupt function may be used
to determine when new data is available.
5.8 Interrupts
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include
the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that
can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock
sources), (2) new data is available to be read (from the FIFO and Data registers), and (3) FIFO overflow.
The interrupt status can be read from the Interrupt Status register.
5.9 Digital-Output Temperature Sensor
An on-chip temperature sensor and ADC are used to measure the device’s die temperature. The readings
from the ADC can be read from the FIFO or the Sensor Data registers.
5.10 Bias and LDO
The bias and LDO section generates the internal supply and the reference voltages and currents required by
the ITG-3701. Its two inputs are unregulated VDD of 1.71V to 3.6V and a VDDIO logic reference supply
voltage of 1.71V to 3.6V. The LDO output is bypassed by a 0.1µF capacitor at REGOUT.
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6
Digital Interface
6.1 I2C Serial Interface
The internal registers and memory of the ITG-3701 can be accessed using the I2C interface.
Serial Interface
Pin Number
Pin Name
VDDIO
Pin Description
3
6
Digital I/O supply voltage.
AD0 / SDO
SCL / SCLK
SDA / SDI
I2C Slave Address LSB (AD0); SPI serial data output (SDO)
I2C serial clock (SCL); SPI serial clock (SCLK)
I2C serial data (SDA); SPI serial data input (SDI)
16
1
6.1.1 I2C Interface
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the
lines are open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can
be a master or a slave. The master device puts the slave address on the bus, and the slave device with the
matching address acknowledges the master.
The ITG-3701 always operates as a slave device when communicating to the system processor, which thus
acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is
400 kHz.
The slave address of the device is b110100X which is 7 bits long. The LSB bit of the 7 bit address is
determined by the logic level on pin AD0. This allows the device to be connected to the same I2C bus. When
used in this configuration, the address of the one of the devices should be b1101000 (pin AD0 is logic low)
and the address of the other should be b1101001 (pin AD0 is logic high). The I2C address is stored in
WHO_AM_I register.
I2C Communications Protocol
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is
defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is
considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to
HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
START and STOP Conditions
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Data Format / Acknowledge
I2C data bytes are defined to be 8 bits long. There is no restriction to the number of bytes transmitted per
data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the
acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal
by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and is unable to transmit or receive another byte of data until some other task has been
performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes
when the slave is ready, and releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address
followed by an 8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from
or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge
signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To
acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line.
Data transmission is always terminated by the master with a STOP condition (P), thus freeing the
communications line. However, the master can generate a repeated START condition (Sr), and address
another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while
SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
SDA
SCL
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
S
P
START
STOP
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
condition
condition
Complete I2C Data Transfer
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To write the internal registers, the master transmits the start condition (S), followed by the I2C address and
the write bit (0). At the 9th clock cycle (when the clock is high), the device acknowledges the transfer. Then
the master puts the register address (RA) on the bus. After the device acknowledges the reception of the
register address, the master puts the register data onto the bus. This is followed by the ACK signal, and
data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal,
the master can continue outputting data rather than transmitting a stop signal. In this case, the device
automatically increments the register address and loads the data to the appropriate register. The following
figures show single and two-byte write sequences.
Single-Byte Write Sequence
Master
Slave
S
AD+W
RA
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
ACK
Burst Write Sequence
Master
Slave
S
AD+W
DATA
P
ACK
ACK
To read the internal device registers, the master sends a start condition, followed by the I2C address and a
write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the
device, the master transmits a start signal followed by the slave address and read bit. As a result, the device
sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a
stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9th clock
cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
RA
RA
S
S
AD+R
AD+R
NACK
ACK
P
ACK
ACK
ACK
ACK DATA
ACK DATA
Burst Read Sequence
Master
Slave
S
AD+W
NACK
P
ACK
DATA
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I2C Terms
Signal
S
Description
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
AD
W
Write bit (0)
R
Read bit (1)
ACK
NACK
RA
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
The internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
6.1.2 SPI interface
SPI is a 4-wire synchronous serial interface that uses two control and two data lines. The ITG-3701 always
operates as a Slave device during standard Master-Slave SPI operation. With respect to the Master, the
Serial Clock output (SCLK), the Data Output (SDO) and the Data Input (SDI) are shared among the Slave
devices. The Master generates an independent Chip Select (/CS) for each Slave device; /CS goes low at the
start of transmission and goes back high at the end. The Serial Data Output (SDO) line, remains in a high-
impedance (high-z) state when the device is not selected, so it does not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. SCLK frequency is 1MHz max for SPI in full read/write capability mode. When the SPI frequency
is set to 20MHz, its operation is limited to reading sensor registers only.
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The
first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first
bit of the first byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation.
The following 7 bits contain the Register Address. In cases of multiple-byte Read/Writes, data is
two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
SPI Data format
MSB
D7
LSB
D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
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SCLK
SDI
SPI Master
SPI Slave 1
SDO
/CS
/CS1
/CS2
SCLK
SDI
SDO
/CS
SPI Slave 2
Typical SPI Master / Slave Configuration
Each SPI slave requires its own Chip Select (/CS) line. SDO, SDI and SCLK lines are shared. Only one /CS
line is active (low) at a time ensuring that only one slave is selected at a time. The /CS lines of other slaves
are held high which causes their respective SDO pins to be high-Z.
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7
Serial Interface Considerations
7.1 Supported Interfaces
The ITG-3701 supports I2C and SPI communications.
7.2 Logic Levels
The I/O logic levels are set to VDDIO. VDDIO may be set to be equal to VDD or to another voltage, such that
it is between 1.71 V and 3.6V at all times. Both I2C and SPI communication support VDDIO.
(0V - VDDIO)
SYSTEM BUS
VDD
VDDIO
VDDIO
ITG-3701
(0V - VDDIO)
INT
System
Processor
(0V - VDDIO)
FSYNC
VDDIO
(0V - VDDIO)
(0V - VDDIO)
(0V, VDDIO)
(0V, VDDIO)
SDA/SDI
SCL/SCLK
AD0/SDO
/CS
SDA
VDDIO
SCL
AD0/SDO
/CS
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8
Assembly
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems
(MEMS) gyros packaged in Quad Flat No leads package (QFN) surface mount integrated circuits.
8.1 Orientation of Axes
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1
identifier in the figure.
+Z
I
T
G
-
3
7
0
1
+Y
+X
Orientation of Axes of Sensitivity and Polarity of Rotation
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8.2 Package Dimensions
Dimensions in Millimeters
Dimension
Min
Nom
Max
A
A1
b
0.70
0.00
0.18
---
0.75
0.02
0.25
0.15 ref
3.00
1.70
3.00
1.50
0.50
0.40
0.50
---
0.80
0.05
0.30
---
c
D
2.90
1.65
2.90
1.45
---
3.10
1.75
3.10
1.55
---
D2
E
E2
e
L
0.35
0.45
0.000
0.45
0.55
0.075
L1
y
8.3 PCB Design Guidelines
Do not solder the center Exposed Pad (E-pad). This is a solder keep-out area.
Recommendations:
Size the PCB pad layout to match the QFN pad leads. Use the package dimensions shown in the Table
above. The Dimensions Table is supplemented with the first figure that follows.
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Design the PCB pad layout with Non Solder Mask Defined pads (NSMD). NSMD pads are recommended
over Solder Mask Defined (SMD) pads. NSMD pads provide a tighter tolerance on copper etching, provide a
larger copper pad area, and allow the solder to anchor to the edges of the copper pads to improve solder
joint reliability. As a recommendation, set the solder mask aperture a minimum of 0.05 mm larger than the
component solder pad per edge. Two alternative PCB layouts are shown below for reference.
Blocked Areas – Solder Mask
Individually Outlined Pads – Solder Mask
D
SOLDERꢀMASK
EXTENT
SOLDERꢀMASK
EXTENT
E
PACKAGE
OUTLINE
PACKAGE
OUTLINE
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8.4 Product Marking Specification
Part number Identification:
Product
TopꢀMark
IT37
ITG-3701
8.5 Tape & Real Specification
ꢀ
ꢀ
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Package Orientation
User Direction
of Feed
Pin 1
INVENSENSE
INVENSENSE
Cover Tape
(Anti-Static)
Carrier Tape
(Anti-Static)
Reel
Terminal Tape
Label
Tape and Reel Specification
Reel Specifications
Quantity Per Reel
5,000
Reels per Pizza Box
1
5
Pizza Boxes Per Carton (max)
Pcs/Carton (max)
25,000
Note: empty pizza boxes are included to ensure that pizza boxes don’t shift.
ꢀꢀ
ꢀ
ꢀ
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8.6 Assembly Precautions
8.6.1 Gyroscope Surface Mount Guidelines
InvenSense MEMS Gyros sense rate of rotation. In addition, gyroscope sense mechanical stress coming
from the printed circuit board (PCB). This PCB stress can be minimized by adhering to certain design rules:
When using MEMS gyroscope components in plastic packages, PCB mounting and assembly can cause
package stress. This package stress in turn can affect the output offset and its value over a wide range of
temperatures. This stress is caused by the mismatch between the Coefficient of Linear Thermal Expansion
(CTE) of the package material and the PCB. Care must be taken to avoid package stress due to mounting.
Traces connected to pads should be as symmetric as possible. Maximizing symmetry and balance for pad
connection will help component self alignment and will lead to better control of solder paste reduction after
reflow.
Any material used in the surface mount assembly process of the MEMS gyroscope should be free of
restricted RoHS elements or compounds. Pb-free solders should be used for assembly.
8.6.2
Exposed Die Pad Precautions
The ITG-3701 have very low active and standby current consumption. There is no electrical connection
between the exposed die pad and the internal CMOS circuits. The exposed die pad is not required for heat-
sinking, and should not be soldered to the PCB. Underfill is also not recommended. Soldering or adding
underfill to the e-pad can induce performance changes due to package thermo-mechanical stress.
8.6.3
Trace Routing
Routing traces or vias under the gyro package such that they run under the exposed die pad is prohibited.
Routed active signals may harmonically couple with the gyro MEMS devices, compromising gyro response.
The gyro drive frequency is ~27 KHz. To avoid harmonic coupling don’t route active signals in non-shielded
signal planes directly below, or above the gyro package. Note: For best performance, design a ground plane
under the e-pad to reduce PCB signal noise from the board on which the gyro device is mounted. If the gyro
device is stacked under another PCB board, design a ground plane directly above the gyro device to shield
active signals from the PCB board mounted above.
8.6.4
Component Placement
Do not place large insertion components such as keyboard or similar buttons, connectors, or shielding boxes
at a distance of less than 6 mm from the MEMS gyro. Maintain generally accepted industry design practices
for component placement near ITG-3701 to prevent noise coupling and thermo-mechanical stress.
8.6.5
PCB Mounting and Cross-Axis Sensitivity
Orientation errors of the gyroscope as mounted to the printed circuit board can cause cross-axis sensitivity in
which one gyro sense axis responds to rotation or acceleration about an orthogonal axis. For example, the
X-gyro sense axis may respond to rotation about the Y or Z axes. The orientation mounting errors are
illustrated in the figure on the next page.
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Z
Φ
Y
I
T
G
-
3
7
0
1
X
Θ
Package Gyro Axis (
) Relative to PCB Axis (
) with Orientation Errors (Θ and Φ)
The table below shows the cross-axis sensitivity as a percentage of the gyroscope’s sensitivity for a given
orientation error, respectively.
Cross-Axis Sensitivity vs. Orientation Error
Orientation Error
Cross-Axis Sensitivity
(θ or Φ)
(sinθ or sinΦ)
0º
0.5º
1º
0%
0.87%
1.75%
The specification for cross-axis sensitivity includes the effect of the die orientation error with respect to the
package.
8.6.6
MEMS Handling Instructions
MEMS (Micro Electro-Mechanical Systems) are a time-proven, robust technology used in hundreds of
millions of consumer, automotive and industrial products. MEMS devices consist of microscopic moving
mechanical structures. They differ from conventional IC products, even though they can be found in similar
packages. Therefore, MEMS devices require different handling precautions than conventional ICs prior to
mounting onto printed circuit boards (PCBs).
The ITG-3701 has been qualified to a shock tolerance of 10,000g. InvenSense packages its gyroscope as it
deems proper for protection against normal handling and shipping. It recommends the following handling
precautions to prevent potential damage.
•
Do not drop individually packaged gyroscope, or trays of gyroscope onto hard surfaces. Components
placed in trays could be subject to g-forces in excess of 10,000g if dropped.
•
Printed circuit boards that incorporate mounted gyroscope should not be separated by manually
snapping apart. This could also create g-forces in excess of 10,000g.
•
Do not clean MEMS gyroscope in ultrasonic baths. Ultrasonic baths can induce MEMS damage if the
bath energy causes excessive drive motion through resonant frequency coupling.
8.6.7
ESD Considerations
Establish and use ESD-safe handling precautions when unpacking and handling ESD-sensitive devices.
•
Store ESD sensitive devices in ESD safe containers until ready for use, such as the original moisture
sealed bags, until ready for assembly.
•
Restrict all device handling to ESD protected work areas that measure less than 200V static charge.
Ensure that all workstations and personnel are properly grounded to prevent ESD.
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8.6.8 Reflow Specification
Qualification Reflow Profile: The ITG-3701 was qualified in accordance with IPC/JEDEC J-STD-020D.1.
This standard classifies proper packaging, storage and handling in order to avoid subsequent thermal and
mechanical damage during the solder reflow attachment phase of PCB assembly.
The qualification preconditioning process specifies a sequence consisting of a bake cycle, a moisture soak
cycle (in a temperature humidity oven), and three consecutive solder reflow cycles, followed by functional
device testing.
The peak solder reflow classification temperature requirement for package qualification is (260 +5/-0°C) for
lead-free soldering of components measuring less than 1.6 mm in thickness. The qualification profile and a
table explaining the set-points are shown below:
SOLDER REFLOW PROFILE FOR QUALIFICATION
LEAD-FREE IR/CONVECTION
F
TPmax
E
G
TPmin
10-30sec
H
D
TLiquidus
Tsmax
C
Liquidus
60-120sec
Tramp-up
( < 3 C/sec)
B
I
Tramp-down
( < 4 C/sec)
Tsmin
Preheat
60-120sec
Troom-Pmax
(< 480sec)
A
Time [Seconds]
Temperature Set Points Corresponding to Reflow Profile Above
CONSTRAINTS
Step Setting
Temp (°C)
Time (sec)
Max. Rate (°C/sec)
A
B
C
D
Troom
25
TSmin
150
200
217
TSmax
TLiquidus
60 < tBC < 120
r(TLiquidus-TPmax) < 3
r(TLiquidus-TPmax) < 3
r(TLiquidus-TPmax) < 3
r(TPmax-TLiquidus) < 4
E
TPmin
255
[255°C, 260°C]
F
TPmax
TPmin
260
255
tAF < 480
[ 260°C, 265°C]
[255°C, 260°C]
G
10< tEG < 30
H
I
TLiquidus
Troom
217
25
60 < tDH < 120
Notes: Customers must never exceed the Classification temperature (TPmax = 260°C).
All temperatures refer to the topside of the QFN package, as measured on the package body surface.
Production Reflow: Check the recommendations of your solder manufacturer. For optimum results, use
lead-free solders that have lower specified temperature profiles (Tpmax ~ 235°C). Also use lower ramp-up and
ramp-down rates than those used in the qualification profile. Never exceed the maximum conditions that we
used for qualification, as these represent the maximum tolerable ratings for the device.
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8.7 Storage Specifications
The storage specification of the ITG-3701 conforms to IPC/JEDEC J-STD-020D.1 Moisture Sensitivity Level
(MSL) 3.
Calculated shelf-life in moisture-sealed bag 12 months -- Storage conditions: <40°C and <90% RH
After opening moisture-sealed bag
168hours -- Storage conditions: ambient ≤30°C at 60%RH
8.8 Label
ITG-3701
Barcode Label
Location of Label on Reel
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
8.9 Packaging
To improve protection for QFN contained in the reel, the reel is packed directly in 10mm thick ESD foam inside the moisture soak bag.
The QFN devices are still protected by a foam liner after the pizza box is discarded.
REEL – with Barcode &
Caution labels
Sealed Moisture Barrier Bag
(Foam Liner & Labels: ESD,
MSL3, Caution, & Barcode)
MSL3 Label
Caution Label
ESD Label
Moisture Sealed Reel
Pizza Box
Pizza Boxes Placed in
foam-lined shipper box
Outer Shipper Label
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
8.10 Representative Shipping Carton Label
ITG-3701
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
9
Reliability
Qualification Test Policy
9.1
InvenSense’s products complete a Qualification Test Plan before being released to production. The
Qualification Test Plan for the ITG-3701 followed the JEDEC JESD47I Standard, “Stress-Test-Driven
Qualification of Integrated Circuits.” The individual tests are described below.
9.2
Qualification Test Plan
Accelerated Life Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
High Temperature
Operating Life (HTOL/LFR)
JEDEC JESD22-A108D, Dynamic,
3.63V biased, Tj>125°C
[read-points 168, 500, 1000 hours]
3
3
3
77
77
77
(0/1)
(0/1)
(0/1)
Accelerated Moisture
Resistance – Unbiased
HAST(1)
JEDEC JESD22-A118A
Condition A, 130°C, 85%RH, 33.3 psia., Unbiased, [read-
point 96 hours]
High Temperature Storage
Life (HTS)
JEDEC JESD22-A103D, Cond. A, 125°C,
Unbiased [read-points 168, 500, 1000 hours]
Device Component Level Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
ESD-HBM
ESD-MM
Latch Up
JEDEC/ESDA JS-001-2012, (Class 2, 2000V)
JEDEC JESD22-A115C, (250V)
1
1
1
3
3
6
(0/1)
(0/1)
(0/1)
JEDEC JESD78D Class II (2), 125°C;
±100mA
Mechanical Shock
JEDEC JESD22-B104C,
3
30
(0/1)
Mil-Std-883H, method 2002.5,
Cond. E, 10,000g’s, 0.2ms,
±X, Y, Z – 6 directions, 5 times/direction
Vibration
JEDEC JESD22-B103B, Variable Frequency
(random), Cond. B, 5-500Hz,
X, Y, Z – 4 times/direction
1
3
5
(0/1)
(0/1)
Temperature Cycling (TC) (1) JEDEC JESD22-A104D Condition G,
77
[-40°C to +125°C], Soak Mode 2 [5’], 850 cycles
Board Level Tests
TEST
Method/Condition
Lot
Quantity
Sample
/ Lot
Acc /
Reject
Criteria
Board Mechanical Shock
JEDEC JESD22-B104C,
1
5
(0/1)
Mil-Std-883H, method 2002.5,
Cond. E, 10000g’s, 0.2ms,
+-X, Y, Z – 6 directions, 5 times/direction
(1) Tests are preceded by MSL3 Preconditioning in accordance with JEDEC JESD22-A113F
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Document Number: PS-ITG-3701A-00
Revision: 1.0
Release Date: 12/13/2013
ITG-3701 Product Specification
10 Environmental Compliance
The ITG-3701 is RoHS Green and environmental compliant.
Environmental Declaration Disclaimer:
InvenSense believes this environmental information to be correct but cannot guarantee accuracy or completeness. Conformity
documents for the above component constitutes are on file. InvenSense subcontracts manufacturing and the information contained
herein is based on data received from vendors and suppliers, which has not been validated by InvenSense.
This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense
for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to
change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to
improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding
the information and specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising
from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited
to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by
implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information
previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors
should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for
any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime
prevention equipment.
InvenSense® is a registered trademark of InvenSense, Inc. ITG-3701™ is a trademark of InvenSense, Inc.
©2013 InvenSense, Inc. All rights reserved.
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