IQ65033QGA12ENF-G [SYNQOR]
DC-DC Regulated Power Supply Module, 2 Output, 39.6W, Hybrid, PACKAGE-18;
| 型号： | IQ65033QGA12ENF-G |
| 厂家： | 
SYNQOR WORLDWIDE HEADQUARTERS |
| 描述： | DC-DC Regulated Power Supply Module, 2 Output, 39.6W, Hybrid, PACKAGE-18 输出元件 |
| 文件： | 总14页 (文件大小：2096K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Technical
Specification
IQ65033QGA12
34-75 V @ 12A
3.3 V & 5.0 V
Quarter-brick ATCA
Power Interface Module
Input / Output
MGMT Power
The IQ65033QGA12 iQor Power Interface Module
integrates all features required by the AdvancedTCA
Base Specification into a Quarter-Brick footprint. The
iQor offers industry leading external hold-up capacitor
volumetric density for a compact overall solution. At
90V hold-up capacitor voltage (trimmable 50-95 V),
only 564 uF is required to achieve 8.70ms hold-up time
at 200Win. The -48 V output voltage is conditioned
for smooth operation through severe input transient
events. The iQor is designed thermally and electrically
to drive higher power wide-range-input DC/DC
converters such as the 400W SynQor PQ60120QZB33.
RoHS Compliant (see last page).
Operational Features
IQ65033QGA12 Module
• Improved common-mode noise
• Input ORing for A & B power feeds
(MOSFET-based for low power dissipation)
• Hot swap control with seamless ride-through of input
voltage transient
• EMI filter meets CISPR 22 Class B when used as directed
(see applications section)
Protection Features
agement power over-voltage protection
agement power over-current protection
output over-current protection
mal shutdown protects the unit from abnormal
ronmental conditions
• External hold-up capacitor trimmable from 50-95 V
• Automatic discharge of external hold-up capacitor
• Isolated management power of 3.3 V at 3.6 A and 5.0 V at 150 mA
• Dual input side enable
• I2C interface data reporting (optional)
t fuse/feed loss alarm
Safety Features
Mechanical Features
0V, 30 MΩ VRTN_A/B to LOGIC_GND and SHELF_GND isolation
60950-1:2007
N/CSA-C22.2 No. 60950-1:2007
0950-1/A1:2010
• Industry standard quarter-brick size: 1.45" x 2.3" (36.8x58.4 mm)
• Overall height of 0.54" (13.7 mm), permits better airflow
and smaller card pitch
• Total weight: 1.2 oz (34 g)
• Flanged pins designed to permit surface mount soldering
(avoid wave solder) using FPiP technique
• External hold-up capacitor footprint much smaller than
other solutions currently available on the market
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 1
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Mechanical Diagram
2.30
Top View
.15
1.400
1.250
1.100
.100
.050
.150
.150
.200
.200
.950
.050
14
13
12
11
10
9
1
18 17 16 15
.400
.600
.400
2
3
.800
.600
1.000
.800
1.225
1.000
1.45
1.225
4
5
6
7
8
2.00
Bottom side
Clearance
0.064 ±0.028
Side View
Overall
Height
0.54 ±0.02
.145
PIN DESIGNATIONS
Function
NOTES
Pin No. Name
1) All Pins are 0.040" (1.02 mm) diameter with 0.080" (2.03 mm)
1
2
3
4
5
-48V_A
-48V_B
Negative A Feed (Externally Fused)
Negative B Feed (Externally Fused)
Positive A Feed (Externally Fused)
Positive B Feed (Externally Fused)
Enable A Input (Externally Fused)
(Short Pin Tied to VRTN_A on Backplane)
Enable B Input (Externally Fused)
(Short Pin Tied to VRTN_B on Backplane)
Shelf Ground
diameter standoff shoulders.
2) Other pin extension lengths available. Recommended pin
length is 0.03" (0.76 mm) greater than the PCB thickness.
3) All Pins: Material - Copper Alloy
VRTN_A
VRTN_B
ENABLE_A
Finish - Matte Tin over Nickel plate
4) Undimensioned components are shown for visual reference only.
5) All dimensions in inches
6
ENABLE_B
Tolerances: x.xx +0.02"
7
8
SHELF_GND
5.0V
x.xxx +0.010"
5.0V (Relative to LOGIC_GND)
9
3.3V
3.3V (Relative to LOGIC_GND)
6) Weight: 1.2 oz (34 g) typical
10
I2C_ADR
I2C Address Input *
7) Workmanship: Meets or exceeds IPC-A-610C Class II
8)
(Connect External Resistor to LOGIC_GND) **
I2C Data (Relative to LOGIC_GND) *
I2C Clock (Relative to LOGIC_GND) *
Logic Ground
Isolated A/B Feed Loss or Open Fuse Alarm
(Relative to LOGIC_GND)
Negative Output to Payload Power Converter
Hold-Up Voltage Trim
(Connect External Resistor to -48V_OUT)
Positive Output to Payload Power Converter
Positive Connection to Hold-Up Capacitor
(Negative Connection to -48V_OUT)
The flanged pins are designed to permit surface mount soldering
(allowing to avoid the wave soldering process)
11
12
13
14
I2C_DAT
I2C_CLK
LOGIC_GND
ALARM
through the use of the flanged pin-in-paste technique.
*
Pins 10, 11, and 12 are only available on the full feature version.
See the ordering page for more information.
15
16
-48V_OUT
HU_TRIM
** Single resistor connected externally to LOGIC_GND selects the three
least significant bits of I2C Address “0101xxx”.
17
18
VRTN_OUT
HU_CAP
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 2
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Technical Specification
IQ65033QGA12 Electrical Characteristics
Specifications subject to change without notice. Specifications in bold are guaranteed by design over the temperature range -40º to 125ºC.
Parameter
ABSOLUTE MAXIMUM RATINGS
Min.
Typ.
Max. Units Notes & Conditions
Input Voltage
Continuous
Transient
Reverse Polarity
-1
-75
-100
+75
V
V
V
Limited by internal TVS zener diode
1ms transient, square wave
No damage, low current, output diode clamped
Isolation Voltage
(VRTN_A/B to LOGIC_GND)
(VRTN_A/B to SHELF_GND)
Operating Temperature
2250
2250
100
125
100
V
V
°C
°C
V
-40
-55
Subject to thermal derating; see Figures 1 & 3
Storage Temperature
Hold-up Capacitor Voltage (Relative to -48V_OUT)
-48V DUAL FEED INPUT CHARACTERISTICS
Input Voltage Range
-34
-48
-75
12
30
70
22
V
A
mA
mA
μF
Ω
Subject to the Threshold Protocol used
25ºC 950 LFM, Vin = -48V; see Figure 1
Operating Current
Disabled Input Current below Turn-Off Threshold
Enabled No-Load Input Current
Internal Input Filter Capacitance (Not Hot-Swapped)
Recommended EARLY_A/B Resistors
Recommended Input Fuses
3.3V ISOLATED MANAGEMENT POWER
Startup Delay
At 36Vin
At 48Vin
At 75Vin
Turn-On Rise Time
20
40
18
Vin = -48V
Should be precharged by resistors to EARLY_A/B pins
Surge rated 2010 case size (KOA SG73 series or equiv.)
100
15
0.5
20
A
Time from ENABLE_A/B to 3.3/5.0Vout
0.43
0.31
0.20
5
s
s
s
0.15
1
ms
0% to 90%; see Figure 10
Input Under-Voltage Lockout
Turn-On Voltage Threshold (ETSI)
Turn-Off Voltage Threshold (ETSI)
Total Output Voltage Range
Output Voltage Ripple and Noise
Peak-to-Peak
-25.5
-24.0
3.170
-26.5
-26.0
3.350
-28.0
-27.5
3.430
V
V
V
At Mangement Power Converter input;
see Figure A; overridden by enable
Including line, load, sample, life, and temp
See Figure 12
Full load, 10μF ceramic, 500MHz bandwidth
"
40
16
75
30
3.6
6.9
mV
mV
A
A
V
ms
mA
μF
kHz
V
RMS
Operating Output Current Range
Output DC Current-Limit Inception
Current Limit Shutdown Voltage
Hiccup Mode Restart Time
Back-Drive Current
0
3.9
Subject to thermal derating; see Figures 1 & 3
5.4
1.5
130
Initiates hiccup mode
Vin = -48V
Negative current drawn from output source
10
1000
240
Maximum Output Capacitance
Switching Frequency
200
4.10
220
4.33
Management power converter
Over-Voltage Protection Setpoint
5.0V POWER (Derived From 3.3V Converter)
Total Output Voltage Range
Operating Output Current Range
Short Circuit Current
4.55
4.80 1
0
5.00
400
5.20
150
V
Including line, load, sample, life, and temp
mA
mA
Ω
Independent Thermal Protection
Negative current drawn from output source
Back-Drive Current
1
Maximum Output Capacitance
1000
μF
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 3
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Technical Specification
IQ65033QGA12 Electrical Characteristics (continued)
Specifications subject to change without notice. Specifications in bold are guaranteed by design over the temperature range -40º to 125ºC.
Parameter
DUAL ENABLE INPUT CHARACTERISTICS
Min.
Typ.
Max. Units Notes & Conditions
ENABLE_A/B Threshold
ETSI
32.0
34.0
36.0
0.36
V
mA
"
Current Drain per Enable Pin (Vin = -75V)
-48V OUTPUT
Efficiency
No load on 3.3V/5.0V outputs, Vin = -48V
400W Output Power
300W Output Power
97.7
98.0
98.2
98.5
80
100
230
250
40
50
2
2
Equivalent Resistance from Input Feed
Recommended External Output Filter Capacitance
Hot-Swap Startup Ramp dv/dt
Output Voltage Delay
Output Current Limit (Turns Off Hot-Swap Momentarily)
Input dv/dt Limit (Turns Off Hot-Swap Momentarily)
Short Circuit Duration to Initiate Hiccup Mode
Restart Time Hiccup Mode
140
270
280
650
46
mΩ
μF
V/s
ms
A
V/ms
ms
s
80
180
See Note 2
No load; depends on external cap.; see Figure 5
Hold-up still active
"
34
1.8
2.2
INPUT ORING
ORing MOSFET Turn On Current
ORing MOSFET Turn Off Current
ORing MOSFET Current Hysteresis
Turn On Time
0.4
0.1
0.3
1
2.4
1.1
1.3
A
A
A
μs
μs
0.4
0.6
600
0.25
Turn Off Time
HOLD-UP CAPACITOR INTERFACE
Hold-up Capacitor Trim Range
50
90
95
V
V
Can be set either above or below input voltage
2.49kΩ external trim resistance, 1% 100ppm/
ﾺC
Hold-up Capacitor Charge Accuracy
87.2
90.0
95.0
160
External Hold-up Voltage Trim Resistor Power Dissipation
Hold-up Capacitor Charge Current
Switching Frequency
μW
mA
KHz
40
450
405
495
Hold-up power converter
-48V_OUT Threshold
See Note 3
To Arm Hold-up Connect (ETSI)
To Initiate Hold-up Connect (ETSI)
dV/dt on Hold-up Connect
-32.4
-32.4
-34.5
-34.5
80
-36.4
-36.4
V
V
V/ms
s
At VRTN_OUT w.r.t. -48V_OUT; see Figure A
"
Duration of Hold-up Connect
0.1
See Note 4
Delay Before Hold-up Connect is (Re)Armed
Hold-up Capacitor Discharge Resistance
2
1.65
s
kΩ
μF
48V output still enabled
1.55
36.4
1.75
3300
Maximum Hold-up Capacitance
Yields 55ms (200 W at 90 V cap charge)
ISOLATED ALARM OUTPUT (ALARM = HIZ)5
Input A/B Feed Voltage Alarm Threshold
Open Circuit Voltage
38.4
40
40.4
0.4
V
V
At input feed voltage -48V_A/B; see Figure A
On-State Voltage
0.2
V
At 50mA
On-State Transistor Collector Current
Off-State Transistor Collector Current
50
1
mA
μA
Note 1: If the 5.0 V load current exceeds 100 mA, up to 200 mV of additional voltage drop is possible on the 5.0 V output.
Note 2: Maximum DC load at startup is 50 mA. Full load can be applied 700 ms after enable or 400 ms after the management power is up and running.
Note 3: Hold-up operation with Vin < 43 V not required by ATCA specification.
Note 4: 48 V output does not recover after hold-up event unless input is above Arm Hold-up threshold.
Note 5: Does not inhibit 48 V output and is non-latching.
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 4
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Technical Specification
IQ65033QGA12 Electrical Characteristics (continued)
Specifications subject to change without notice. Specifications in bold are guaranteed by design over the temperature range -40º to 125ºC.
Parameter
Min.
Typ.
Max. Units Notes & Conditions
I2C DATA REPORTING INTERFACE
Maximum Clock Rate
100
400
kHz
Clock stretching happens at the maximum rate
Measurement Error
Feed Voltage A/B
Holdup Voltage
-48V_OUT Current
Temperature
±3
±3
±3
±3
%
%
%
°C
OVER-TEMPERATURE PROTECTION
Shutdown Point
Restart Hysteresis
135
10
°C
°C
Clock stretching happens at the maximum rate
Automatic restart
RELIABILITY CHARACTERISTICS
Calculated MTBF (Telcordia)
Calculated MTBF (MIL-217)
Field Demonstrated MTBF
3.6
3.27
106 Hrs. TR-NWT-000332; 80% load,300LFM, 40°C Ta
106 Hrs MIL-HDBK-217F; 80% load, 300LFM, 40°C Ta
See website for details
TEMPERATURE LIMITS FOR POWER DERATING CURVES
Semiconductor Junction Temperature
Board Temperature
125
125
125
°C
°C
°C
Package rated to 150°C
UL rated max operating temp 130°C
See Figure 3 for derating curve
Transformer Temperature
Parameter
STANDARDS COMPLIANCE
Notes & Conditions
UL 60950-1:2007
Basic insulation
EN60950-1/A1:2010
CAN/CSA-C22.2 No. 60950-1:2007
Note: An external input fuse must always be used to meet these safety requirements. Contact SynQor for official safety certificates on new
releases or download from the SynQor website.
Parameter
QUALIFICATION TESTING
Life Test
# Units Test Conditions
32
95% rated Vin and load, units at derating point, 1000 hours
Vibration
5
5
10
5
5
5
10-55 Hz sweep, 0.060" total excursion, 1 min./sweep, 120 sweeps for 3 axis
100g minimum, 2 drops in x, y and z axis
Mechanical Shock
Temperature Cycling
Power/Thermal Cycling
Design Marginality
Humidity
-40 °C to 100 °C, unit temp. ramp 15 °C/min., 500 cycles
Toperating = min to max, Vin = min to max, full load, 100 cycles
Tmin-10 °C to Tmax+10 °C, 5 °C steps, Vin = min to max, 0-105% load
85 °C, 95% RH, 1000 hours, continuous Vin applied except 5 min/day
MIL-STD-883, method 2003
Solderability
15 pins
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 5
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Technical Specification
12
11
10
9
8
7
6
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
5
200 LFM (1.0 m/s)
4
3
100 LFM (0.5 m/s)
10
25
40
55
70
85
Ambient Air Temperature (°C)
Figure 1: -48V output (maximum power) derating curves vs. ambient air
Figure 2: Thermal plot of converter at 8.0A load current from -48V output
(384W) with 55°C air flowing at the rate of 200 LFM. Air is flowing across the
converter from pin 7 to pin 1 (48 Vin, 3.3V output @ 1.5 A).
temperature for airflow rates of 100 LFM through 400 LFM with air flowing
across the converter from pin 7 to pin 1 (48 Vin, 3.3V mgmt power output @
1.5 A).
4.0
3.5
3.0
2.5
2.0
400 LFM (2.0 m/s)
300 LFM (1.5 m/s)
1.5
1.0
200 LFM (1.0 m/s)
100 LFM (0.5 m/s)
10
25
40
55
70
85
Ambient Air Temperature (°C)
Figure 3: 3.3V output (maximum power) derating curves vs. ambient air
Figure 4: Thermal plot of converter at 3.0A load current from 3.3V output
(9.9W) with 55°C air flowing at the rate of 200 LFM. Air is flowing across the
converter from pin 7 to pin 1 (48 Vin, -48V output @ 4 A).
temperature for airflow rates of 100 LFM through 400 LFM with air flowing
across the converter from pin 7 to pin 1 (48 Vin, main output power output @
4 A).
Figure 5: 48V hot-swap turn-on transient (100uF electrolytic filter capacitor
CF). Top trace: VRTN_OUT w.r.t. -48V_OUT (20V/div), Bottom trace: Input
Feed Current (1A/div).
Figure 6: 8.70ms zero volt transient (564uF electrolytic hold-up capacitor CH,
100uF electrolytic filter capacitor CF). Ch 1: Input Feed A/B Voltage (20V/div).
Ch 2: VRTN_OUT w.r.t. -48V_OUT (20V/div). Ch 3: HU_CAP w.r.t. -48V_OUT
(20V/div). Ch 4: 3.3V_OUT (200mV/div).
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 6
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Technical Specification
Figure 7: Instantaneous input transient from 48V Feed A to 60V Feed B. Ch 1:
Input Feed A Voltage (20V/div). Ch 2: Input Feed B Voltage (20V/ div). Ch 3:
VRTN_OUT w.r.t. -48V_OUT (20V/div). Ch 4: 3.3V_OUT (200mV/div).
Figure 8: Inductive Switching event on Feed A from 48V to 0V to TVS Zener
clamping voltage. No load on -48V output. Ch1: Input Feed A Voltage (20V/
div). Ch3: VRTN_OUT w.r.t. -48V_OUT (20V/div). Ch 4: 3.3V_OUT (50mV/
div).
8
7
6
5
4
3
2
36 Vin
48 Vin
1
75 Vin
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Load Current (A)
Figure 9: Power dissipation vs. 3.3V load current.
Figure 10: Management Power turn on transient at 50% load (4ms/div). Load
capacitance: 10uF ceramic capacitor. Ch 2: 3.3Vout (1V/div). Ch 3: 5.0Vout
(1V/div).
Figure 11: 3.3Vout response to a step-change in load current [50%-75%-50%
of Iout(max): dI/dt = 1A/us]. Load capacitance: 10uF ceramic capacitor. Top
trace: 3.3Vout (500mV/div). Bottom trace: Iout (1A/ div).
Figure 12: 3.3Vout ripple at nominal input voltage at rated load current (20mV/
div). Load capacitance: 10uF ceramic capacitor. Bandwidth: 500MHz.
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 7
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Application Section
FEATURE DESCRIPTIONS
Input ORing MOSFETs: ORing of dual -48V feeds is provided by four
MOSFETs, which are individually controlled so as to operate as an ideal
diode (see Figure A). If there is an input feed short of any kind, a control
circuit will detect reverse current and turn off the MOSFET in 250ns (typ.),
to avoid disturbing the other feed voltage. At zero current, the MOSFET is
guaranteed to be off. In the case of a fuse failure, this triggers the ALARM
output, due to an apparent input feed loss. Current hysteresis prevents
limit cycling around the transition point between body diode and MOSFET
conduction. Due to the ‘Turn On Current’ feature, at fixed Input- Voltages
the Output Voltage will experience one or two Diode drops (0.6V or 1.2V)
for currents at or below ‘Turn On Current’ thresholds.
External Input Fuse Failure Detection: At zero current, the input
ORing MOSFETs are guaranteed to be off. In the case of a fuse failure,
an on-board bleed resistor pulls the input feed voltage down. This triggers
the ALARM output due to an apparent input feed loss. There are two main
down-sides to this approach. First, there is no way to distinguish between
a feed loss and a fuse failure. Second, an enable fuse loss is not detected,
since the enables are diode OR’d.
The full featured version of the iQor offers additional data reporting that
makes full fuse detection possible. Among other data, each feed voltage
and each enable voltage is reported through the I2C port. These voltages
can be compared with the voltages reported by the shelf manager to
determine whether any board fuse is blown.
ALARM Output: The ALARM pin gives an external indication of a fault
condition. It is an isolated and buffered open-collector output, which is
normally pulled low. In the presence of an input feed loss (which can be
caused by a fuse failure), the ALARM output will be tri-stated.
Input Enable: The ENABLE_A/B signals connect to VRTN_A/B on the
backplane via the shortest pins in the zone 1 connector. They are the last
pins to mate during board insertion, and the first to disconnect during board
extraction. The ENABLE_A and ENABLE_B signals are diode-ORed together
which lets either signal enable the module. Whenever both ENABLE pins
are open, the hot-swap switch is opened. This prevents -48V output power
from being drawn though the EARLY pre-charge resistors.
ENABLE_A
HU_CAP
5
18
ENABLE_B
6
Temp
sense
VRTN_A
Enable Logic
Hold-up
connect control
circuits
3
FET
control
E
dV/dt
sense
F
A
VRTN_B
VRTN_OUT
4
17
FET
control
E
F
Current-
B
Hot Swap
Control Logic
controlled hold-
up charging
converter
HU_TRIM
EMI Filter
-48_A
16
1
FET
control
-48V_OUT
C
15
-48_B
2
Dis-
charge
FET
control
Management
Power
converter
A
B
C
D
D
Isolation barrier
Monitoring
circuits
SHELF_GND
3.3V
9
7
8
E
F
5.0 V
11
12
14 13
10
Figure A: Internal Block Diagram
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 8
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Application Section
The ENABLE signals also control the management power. On board
insertion, the management power remains off until at least one of
ENABLE_A/B is connected. On board extraction, the management power
is disabled at the end of the 100ms hold-up period, and remains off
until ENABLE_A/B is reconnected. This prevents the IPMI controller from
reading an invalid hardware address when a board is partially inserted.
Management power flows through the EARLY pre-charge resistors for a
maximum of 100ms, which provides a margin similar to the pre-charge
event in terms of resistor safe-operating-area.
48V
0
Input voltage
Holdup time, tH
Holdup event
48V
0
EARLY Precharge Resistors: The EARLY_A/B signals connect to the
longest pins in the zone 1 power connector, and therefore first to mate
during board insertion. External resistors connected between these signals
and -48V (A and B) allow the relatively small EMI filter capacitance to be
pre-charged before the main power pins make contact. A 100W surge
rated 2010 case size resistor is recommended (KOA SG73 series or
equivalent).
35V typ.
(12A DS Version only)
26.6 V
typ.
Payload output 48V
Thresholds at -48Vout
3.3V
0
Management power
Hot Swap - Thermal Shutdown: To protect the unit from damage
in an abnormal thermal environment, the hot-swap switch will be disabled
when the thermal sensor temperature rises above the turn-off threshold. The
switch will be automatically enabled again when the temperature goes
below the turn-on threshold. The management power remains on during an
over-temperature condition.
Alarm
(Pull-up voltage lost)
0
Figure B: Sudden Loss of Input Power
The full featured version of the iQor reports the actual temperature through
the I2C port.
48V
34.4 V
typ.
34.9 V
typ.
26.0
Higher of A/B input feed voltages
RTN A/B - (-48V_A/B)
Thresholds at -48V_A/B
V
0
Holdup event
48V
Output is off after
delay if input
34.5 V
typical
(12A DS
voltage doesn’t
recover above
38.9V typ.
-48V output voltage
VRTNOUT - (-48V_OUT)
Thresholds at -48Vout
100ms
Version only)
0
Management power turned
3.3V
off at higher of ENABLE
threshold or MP UVLO.
Management power output
(3.3V) - LOGIC_GND
0
Alarm - (LOGIC_GND)
(Pullup voltage lost)
Figure C: Gradual Loss of Input Power
Product # IQ65033QGA12
Phone 1-888-567-9596
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Doc.# 005-0006070 Rev. B
09/06/2012
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Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Application Section
48V
0V
Hot Swap - Over-Current Protection: If the -48V output current rises
above the current limit threshold, the hot-swap switch will be disabled, and
will immediately enter another soft-start sequence. If an output short is
detected, the hot-swap switch will be disabled and will enter a hiccup mode
of operation with automatic restart.
Turn on threshold
48V in
High
Low
Enable A/B
The full featured version of the iQor reports actual output current through
the I2C port.
5V
3.3V
3.3V, 5V
outputs
Hot Swap - Transient Suppression: Input transient events can occur if
there is a short on an adjacent board or backplane. The short builds up a
large current in the wiring inductance, and when a fuse blows, the voltage
behind the fuse spikes very quickly. This can cause a loss of redundancy
since many other boards could be exposed to this spike.
0V
15 ms
0.5s
On
HotSwap Switch
Outputvoltage
Off
The iQor unit conditions the -48V output, providing for seamless ride-
through of input voltage transients. If the positive dV/dt of the input voltage
is too high, the hot-swap switch will be disabled and will immediately enter
another soft-start sequence. This limits the dV/dt seen on the -48V output,
which prevents the 12V payload power converter from having such a large
glitch on its output that it shuts down. The -48V output hold-up function
remains active throughout, in case the hot-swap switch is forced off for too
long.
Vo
Payload converter
Turn on threshold
0V
650ms
Full payload current
0.5A
Payload (output)
50mA
0A
current
Passive Transient Suppression: Each input feed has a dedicated
internal bidirectional TVS zener diode, rated for a minimum clamp voltage
of 77.8V at 1mA. A TVS diode short due to electrical overstress will not
disable the iQor module: a fuse will open, and the module can continue to
run from the other feed.
Payload converter should be
enabled aꢀer this delay.
650ms
Inrush: ~5ms
Notes:
• Time relaꢁonships shown have tolerance defined in the specificaꢁons table.
• Hot Swap switch output is not available to the user for monitoring
• Power up inrush duraꢁon is typical with Early mate resistor of 100 Ohms.
External Hold-up Capacitor Charge: A current controlled DC-DC
converter charges the external hold-up capacitor to a voltage of 50V-95V,
set by an external resistor. The charge voltage can range either above
or below the input feed voltage. Constant current charging takes place
whenever the hot-swap switch is enabled.
Figure D: Power up (Board insertion) timing diagram
In the event of a gradual loss of input voltage (Fig. C), the main -48Vout
will shut down 100ms after the beginning of the hold-up event.
-48Vout will enter a hiccup mode of operation for input voltages below
the Hold-up Arm Threshold. Management power will continue to run until
the input voltage (plus 0V to 1.2V for the ORing MOSFETs) decays to the
management power under-voltage turn-off threshold.
The
Hold-up Capacitor Connect: When the hot-swap switch is enabled,
2 seconds are allocated to charge the hold-up capacitor. After this time,
a comparator is armed, which connects the hold-up capacitor to the -48V
output should the output ever drop below the given connect threshold.
A
current limit circuit protects against damage during a short circuit condition.
A dV/dt limit circuit regulates the hold-up connect switch turn-on speed.
When the comparator is tripped, the hold-up connect switch remains closed
for 100ms, is off for 2 seconds to allow the hold-up capacitor to recharge,
and then is automatically rearmed (if the output voltage is above the given
arm threshold).
20
PH=200W
CF=100µF
VI=-43V
PH=Power at Holdup
CF=Output Capacitor (Filter)
VI=Voltage at Input
15
10
5
Hold-up Capacitor Discharge:
Whenever the hot-swap switch
is disabled, an internal resistor bank is connected across the hold-up
capacitor. This is intended to reduce the voltage on the hold-up capacitor
below 60V within 1 second.
Management Power: An isolated management power converter
delivers both 3.3V and a low power 5.0V relative to LOGIC_GND. Over-
current protection operates in constant current with a hiccup mode if the
output voltage drops too far. Output over-voltage circuitry is included with
a redundant reference and optocoupler.
90V
80V
70V
0
The events from power up to availability of output voltage and full payload
current are illustrated in the timing diagram shown in Figure D.
300
400
500
600
700
800
900
1000
Hold-up Capacitance (µF)
Hot Swap – Shutdown Timing: In the event of a sudden loss of input
voltage (see Figure B), a hold-up event will be triggered. When the output
voltage (plus a diode drop for the hot-swap body diode) decays to the
management power under-voltage turn-off threshold, the main -48V output
and the 3.3V/5.0V outputs will shut down simultaneously.
Figure E: Hold-up Time (ms) vs. Hold-up Capacitance (µF) at Hold-up Charge
Voltages of 70V, 80V, and 90V (see Equation A). The AdvancedTCA hold-
up time requirement is at most 8.70ms (solid horizontal line). The capacitor
tolerance is not factored into this result. Error bars indicate the worst case
range of hold-up time for a given hold-up capacitance.
Product # IQ65033QGA12
Phone 1-888-567-9596
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Doc.# 005-0006070 Rev. B
09/06/2012
Page 10
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Application Section
EXTERNAL HOLD-UP CAPACITOR SELECTION
100
90
80
70
60
50
40
30
20
10
0
C is the hold-up capacitance (electrolytic capacitors typically have a 20ꢀ
toHlerance):
Fuse-Blowing type transient that cause a drop
in both input feeds simultaneously.
2tHPH
V2H - V2U
CH =
Equation A
Typically a strong function of VH (see Figure E).
The ATCA specification requirement is 8.70ms (see Figure F).
Where:
43.0V
41.0V
36.0V
VH
VU
=
=
hold-up capacitor charge voltage.
minimum operating voltage on the 48V output; the greater
of the under-voltage lockout threshold of the payload power
converter, and the under-voltage lockout threshold of the
management power converter.
0
1
2
3
4
5
6
7
8
9
10
8.70ms
tU
=
time from when the highest input feed voltage drops below
VF, to the time when the highest input feed voltage rises
above VU.
Time (ms)
Figure F: The PICMG 3.0 R2.0 AdvancedTCA Base Specification requires
continuous operation through a zero-volt transient, lasting 5ms (Section
VF
PH
=
=
voltage at which the hold-up capacitor is engaged.
power drawn from the hold-up capacitor, the sum of the input
power of the payload power converter, and the input power
of the 3.3V mgmt power converter (see Figure 9):
4.1.2.2). However, this is not a square wave: the voltage starts at a minimum
amplitude of -43V, falls at 50V/ms, remains at 0V for 5ms, and then rises at
12.5V/ms. At the worst case values of the hold-up connect threshold and the
management power under-voltage lockout threshold, the required hold-up time
is 8.70ms
Pout 12V
PH =
+ PIN 3.3V
Equation A
η12V
Pout12V
=
=
=
output power delivered by the payload converter.
efficiency of the 12V payload converter.
η12V
PIN 3.3V
output power delivered by the payload converter.
EXTERNAL HOLD-UP TRIM RESISTOR SELECTION
Rtrim is the external hold-up trim resistance for a given desired nominal hold-
up capacitor charge voltage (VHU) (see Figure G):
EXTERNAL HOLD-UP CAPACITOR VOLTAGE RATING
Operating electrolytic capacitors near their voltage rating does not
significantly affect their reliability, as it does with tantalum or ceramic
type capacitors. The operating life of electrolytic capacitors is primarily
determined by the capacitor internal temperature. The capacitor lifetime
roughly doubles for every 10ºC reduction in internal temperature. SynQor
recommends running 100V rated electrolytic capacitors at 90V, which
dramatically increases hold-up time for a given capacitor volume (see
Figure E). A built-in circuit automatically discharges the hold-up capacitor
when the input voltage is removed.
500,000
Equation C
Rtrim
=
(
- 10,000 ) Ω
VHU - 50.0
100000
10000
1000
50
60
70
80
90
100
Hold-up Charge Voltage (V)
Figure G: Plot of Equation C, used to choose the external trim resistor value
based on the desired Hold-up Capacitor charge voltage. Error bars indicate
the worst case range of charge voltage for a given external trim resistor
value (assumes 1%, 100ppm for external trim resistor tolerance). Worst case
calculation over temp range -40ºC to 125ºC.
Product # IQ65033QGA12
Phone 1-888-567-9596
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Doc.# 005-0006070 Rev. B
09/06/2012
Page 11
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Application Section
FULL FEATURE APPLICATION NOTES
I2C Data Reporting Interface: Available on the full feature version of
the module, the iQor I2C Serial Interface monitors 5 analog parameters
and 6 status bits. The actual analog parameter values are calculated by
multiplying by the specified scaling factors (see Table 1). The status bits
are interpreted in Table 2. The initial value of all registers is zero. Data in
the registers begins updating 300 ms after management power startup, and
continues updating at approximately 100 ms intervals during steady-state
operation. All registers are updated simulatneously.
Data_
Pointer
Value
Parameter
Description
Scaling Factor
N/A
Digital Signals
(see Table 2)
1Eh
1Fh
21h
22h
Status Bits
Voltage between
HU_CAP and
-48V_OUT
HU_CAP
0.398 V/bit
0.094 A/bit
0.325 V/bit
I2C Protocol: Reading from any internal register of the iQor monitor
requires that an internal (pseudo) register, Data_Pointer, be initialized prior
to reading (see Figure I).
Data_Pointer is write-only. It is written from the second byte of any I2C
WRITE message (the first byte is the 7 bit I2C Address and the R√W bit).
Subsequent data bytes in a WRITE message (3rd Byte and beyond) only
increment Data_Pointer.
-48Vout
Current
-48V_Current
-48V_A
Voltage between
VRTN_A and
-48V_A
Voltage between
VRTN_B
and -48V_B
23h
28h
-48V_B
0.325 V/bit
Any READ message will return the value of the internal register referenced
by Data_Pointer and increments Data_Pointer by one. For instance, if
the master acknowledges (AK), the next internal register referenced by
Data_Pointer will be returned and Data_Pointer will be incremented by one.
This process is repeated until the master does not acknowledge (NACK)
and issues a STOP bit.
Average Unit
Temperature
Temperature
(1.961 ºC/bit) – 50 ºC
Table 1: Internal register memory map.
Data_Pointer is an 8bit value. It is initialized to 00h at reset, and after
reaching FFh, it will not overflow.
Writing to registers not defined in Table 1 has no effect. Reading from
these undefined registers will return 00h. In both cases Data_Pointer is
incremented.
* Shield plane should extend
under payload power
converter
Shield Plane*
Holdup capacitor
CH
12V
Payload
Power
100µF
100V
Converter
-48V A
Early A
PQ60120QEA25
(from IPM)
100Ohms
100Ohms
Alarm
-48V_A
-48V_B
ALARM
-48V B
Early B
LOGIC_GND
VRTN_A
VRTN_B
RTN 48V A
RTN 48V B
Enable A
I2C CLOCK
I2C DATA
I2C ADDRESS
SynQor
iQor
ATCA
Power Input Module
ENABLE_A
ENABLE_B
SHELF_GND
3.3 V
5.0V
3.3V to IPM
Blue LED bias
Enable B
Shelf Gnd
I2C interface on full-
featured version only
Figure H: Application Diagram
Product # IQ65033QGA12
Phone 1-888-567-9596
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Doc.# 005-0006070 Rev. B
09/06/2012
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Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Application Section
Example from the point of view of the I2C Master:
Bit Name
ENABLE_A
Description Value Translation
1) START transmission.
0
1
0
1
0
1
EN_A is Disabled
EN_A is Enabled
EN_B is Disabled
EN_B is Enabled
Primary side Alarm is not SET
Primary side Alarm is SET
Enable A
Signal State
0
2) Send 56h (addresses unit for writing, given address 56h was
selected as shown in Table 4).
Enable B
Signal State
1 ENABLE_B
3) Send 22h (loads 22h into Data_Pointer).
4) STOP transmission.
5) START next transmission.
6) Send 57h (addresses unit for reading).
7) Unit will respond with the value of -48V_A (register 22h as shown
in Table 1).
Alarm Signal
State
2 ALARM
3 N/A
Reserved
Holdup Cap is not connected to
-48V Out
0
1
Holdup
Switch
State
4 HOLDUP
8) ACK (Data_Pointer is automatically incremented to 23h).
9) Unit will respond with the value of -48V_B (register 23h).
10) NACK.
Holdup Cap is connected to
-48Vout
0
1
Hotswap switch is OFF
Hotswap switch is ON
Hotswap
Switch State
5 HOTSWAP
11) Stop Transmission.
-48Vout
Under-Voltage
Alarm
0
1
Vout is below threshold
Vout is above threshold
I2C Address structure:
7 bit I2C Address + R/W bit
VOUT_
6
LOW
Four bits are fixed (0101), three bits (xyz) are variable, and the least-
significant bit is the read/write bit.
7 N/A
Reserved
Table 2: The status byte represents 6 different digital signals and their digital
8 bit I2C Address
state. Note: 1) Bit0 ⇒ LSb, Bit7 ⇒ MSb
0 1 0 1
x y z *
R/W
Table 3: I2C address structure.
I2C Protocol: Reading from any internal register of the iQor monitor
requires that an internal (pseudo) register, Data_Pointer, be initialized
prior to reading (see Figure I).
I2C Address selection: The three bits (xyz) of the I2C Address are set
with a single external resistor from the I2C_ADR (pin 10) to LOGIC_GND
(pin 13). The 8 possible addresses are shown in Table 4 with the
respective resistance values.
Data_Pointer is write-only. It is written from the second byte of any I2C
WRITE message (the first byte is the 7 bit I2C Address and the R√W bit).
Subsequent data bytes in a WRITE message (3rd Byte and beyond) only
increment Data_Pointer.
External programming resistances for I2C Address Selection
I2C address for write
Any READ message will return the value of the internal register referenced
by Data_Pointer and increments Data_Pointer by one. For instance, if the
master acknowledges (AK), the next internal register referenced by Data_
Pointer will be returned and Data_Pointer will be incremented by one. This
process is repeated until the master does not acknowledge (NACK) and
issues a STOP bit.
xyz from Table 3
R (Ω)
(R/W = 0)
5Eh
5Ch
5Ah
58h
56h
54h
52h
50h
111
110
101
100
11
10
1
0
Open
100000
40200
20000
10000
4020
Data_Pointer is an 8bit value. It is initialized to 00h at reset, and after
reaching FFh, it will not overflow.
2000
Short
Writing to registers not defined in Table 1 has no effect. Reading from
these undefined registers will return 00h. In both cases Data_Pointer is
incremented.
Table 4: I2C address selection.
PCB layout
Connections to the address selection resistor must follow the Kelvin method
to minimize effects of DC offsets and ripple/noise present in the general
GND. The interconnection between Digital GND and Power GND or GND
plane should also be in such a way that noise is not coupled to the address
selection circuitry. See Figure J
8 bits
8 bits
8 bits
1 bit
1 bit
1 bit
S 7bit Address W
Data_Pointer
Dummy
P
P
● ● ●
● ● ●
AK
AK
AK
8 bits
1 bit
1 bit
AK
1 bit
8 bits
8 bits
ADDR
S 7bit Address R
NACK
Pin 10
AK Register Value
Register Value
PIM
Address selection resistor
DIG_GND
Figure I: Typical I2C read transmission. Note: S = START, W = WRITE, R =
READ, AK = acknowledged, NACK = NOT acknowledged, P = STOP. Clear
boxes originate in the I2C Master and shaded boxes originate in the I2C Slave.
DIG_GND
(Gnd plane)
Pin 13
(from other
circuits and
RTNs from
other power
supplies)
Figure J: Resistor Diagram
Product # IQ65033QGA12
Phone 1-888-567-9596
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Doc.# 005-0006070 Rev. B
09/06/2012
Page 13
Input:34-75 V
Outputs:3.3 V & 5.0 V
Current:12A
Package:Quarter-brick
Ordering Section
PART NUMBERING SYSTEM
ORDERING INFORMATION
The part numbering system for SynQor’s dc-dc converters
follows the format shown in the example below.
The tables below show the valid model numbers and ordering
options for converters in this product family. When ordering
SynQor converters, please ensure that you use the complete
15 character part number consisting of the 12 character base
part number and the additional 3 characters for options.
Add “-G” to the model number for 6/6 RoHS compliance.
IQ 65 033 Q G A 12 ERS
- G
6/6 RoHS
Options (see
Ordering Information)
Input
Voltage
MGMT
Power
Max Output
Current
Model Number
Output Current
IQ65033QGA12xyz-G
34-75 V 3.3V & 5.0V
12A
Thermal Design
Performance Level
Package Size
The following options must be included in place of the w x y z
spaces in the model numbers listed above.
Output Voltage
Input Voltage
Product Family
Options Description: x y z
Feature
Threshold Protocols
Pin Style
Set
K - 0.110"
N - 0.145"
R - 0.180"
Y - 0.250"
S - Standard
F - Full
Feature
E - ETSI
The first 12 characters comprise the base part number and
the last 3 characters indicate available options. The “-G”
suffix indicates 6/6 RoHS compliance.
Not all combinations make valid part numbers, please contact
SynQor for availability. See the Product Summary web page for more
options.
Application Notes
A variety of application notes and technical white papers can
be downloaded in pdf format from our website.
RoHS Compliance: The EU led RoHS (Restriction of Hazardous
Substances) Directive bans the use of Lead, Cadmium,
Hexavalent Chromium, Mercury, Polybrominated Biphenyls
(PBB), and Polybrominated Diphenyl Ether (PBDE) in Electrical
and Electronic Equipment. This SynQor product is 6/6 RoHS
compliant. For more information please refer to SynQor’s RoHS
addendum available at our RoHS Compliance / Lead Free Initiative web
PATENTS
page or e-mail us at rohs@synqor.com
.
SynQor holds the following U.S. patents, one or more of which apply to
each product listed in this document. Additional patent applications may
be pending or filed in the future.
5,999,417
6,894,468
7,119,524
7,765,687
6,222,742
6,896,526
7,269,034
7,787,261
6,545,890
6,927,987
7,272,021
8,023,290
6,577,109
7,050,309
7,272,023
8,149,597
6,594,159
7,072,190
7,558,083
6,731,520
7,085,146
7,564,702
Contact SynQor for further information:
Phone:
Toll Free: 888-567-9596
978-849-0600
Warranty
SynQor offers a three (3) year limited warranty. Complete warranty information
is listed on our website or is available upon request from SynQor.
Fax:
978-849-0602
E-mail:
Web:
power@synqor.com
www.synqor.com
Information furnished by SynQor is believed to be accurate and reliable.
However, no responsibility is assumed by SynQor for its use, nor for any
infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any
patent or patent rights of SynQor.
Address: 155 Swanson Road
Boxborough, MA 01719
USA
Product # IQ65033QGA12
Phone 1-888-567-9596
www.synqor.com
Doc.# 005-0006070 Rev. B
09/06/2012
Page 14
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