MD1811K6-G [SUPERTEX]
HIGH SPEED QUAD MOSFET DRIVER; 高速四通道MOSFET驱动器
| 型号： | MD1811K6-G |
| 厂家： | 
Supertex, Inc |
| 描述： | HIGH SPEED QUAD MOSFET DRIVER |
| 文件： | 总6页 (文件大小：459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MD1811
Initial Release
High Speed Quad MOSFET Driver
General Description
Features
The Supertex MD1811 is a high speed, quad MOSFET driver designed to
drive high voltage P/N-channel MOSFETs for medical ultrasound applications
and other applications requiring a high output current for a capacitive load.
The high-speed input stage of the MD1811 can operate from a 1.2 to 5.0
volt logic interface with an optimum operating input signal range of 1.8 to 3.3
volts. An adaptive threshold circuit is used to set the level translator switch
threshold to the average of the input logic 0 and logic 1 levels. The input
logic levels may be ground referenced, even though the driver is putting
out bipolar signals. The level translator uses a proprietary circuit, which
provides DC coupling together with high-speed operation.
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6ns rise and fall time
2 A peak output source/sink current
1.2V to 5V input CMOS compatible
5V to 12V total supply voltage
Smart Logic threshold
Low jitter design
Quad matched channels
Drives two N and two P Channel MOSFETs
Outputs can swing below ground
Low inductance quad flat no-lead package
High-performance thermally-enhanced
The output stage of the MD1811 has separate power connections enabling
the output signal L and H levels to be chosen independently from the supply
voltages used for the majority of the circuit. As an example, the input logic
levels may be 0 and 1.8 volts, the control logic may be powered by +5 and
–5 volts, and the output L and H levels may be varied anywhere over the
range of –5 to +5 volts. The output stage is capable of peak currents of up
to 2 amps, depending on the supply voltages used and load capacitance
present. The OE pin serves a dual purpose. First, its logic H level is used
to compute the threshold voltage level for the channel input level translators.
Secondly, when OE is low, the outputs are disabled, with the A & C output
high and the B & D output low. This assists in properly pre-charging the AC
coupling capacitors that may be used in series in the gate drive circuit of an
external PMOS and NMOS transistor pair.
Applications
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Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
PIN diode driver
Clock driver/buffer
High speed level translator
Typical Application Circuit
+100V
+10V
+10V
1 F
0.22 F
0.47 F
V
V
10nF
DD
H
To Piezoelectric
Transducer #1
OE
ENAB
OUTA
INA
+PLS1
#1
10nF
-100V
1 F
+100V
1 F
OUTB
INB
3.3V CMOS
Logic Inputs
-PLS1
Supertex
TC6320
OUTC
OUTD
INC
IND
+PLS2
#2
-PLS2
V
SS
V
L
GND
10nF
10nF
To Piezoelectric
Transducer #2
Supertex MD1811
-100V
1 F
Supertex
TC6320
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MD1811
Ordering Information
Package Options
DEVICE
16-Lead 4x4x0.9 QFN
MD1811
θJA
MD1811K6-G
45°C/W (1oz. 4-layer 3x4inch PCB)
-G indicates package is RoHS compliant (‘Green’)
Product Marking Information
Device Number
1ST Line
2ND Line
1811
Absolute Maximum Ratings*
VDD-VSS, Logic Supply Voltage
-0.5V to +13.5V
Year, Week Code, Lot Number
YWLL
VH, Output High Supply Voltage
VL, Output Low Supply Voltage
Vss, Low Side Supply Voltage
Logic Input Levels
VL-0.5V to VDD+0.5V
VSS-0.5V to VH+0.5V
-7V to +0.5V
VSS-0.5V to VSS+7V
+125°C
Example: 5A88 means Lot #88 of first or second week in 2005
Pin 1
1811
YWLL
Maximum Junction Temperature
Storage Temperature
-65°C to 150°C
235°C
Soldering Temperature
Package Power Dissipation
2.2W
Top View
*Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
DC Electrical Characteristics (VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25°C)
Sym.
VDD-VSS
VSS
VH
Parameter
Min.
Typ.
Max.
Units
Conditions
Logic supply voltage
Low side supply voltage
Output high supply voltage
Output low supply voltage
VDD quiescent current
VH quiescent current
VDD average current
4.5
13
V
-5.5
VSS+2
VSS
0
V
VDD
VDD-2
V
VL
V
IDDQ
IHQ
0.8
mA
µA
mA
mA
V
No input transitions, OE = 1
10
IDD
8.0
26
One channel on at 5.0Mhz, No load
IH
VH average current
VIH
VIL
Input logic voltage high
Input logic voltage low
Input logic current high
Input logic current low
OE Input logic voltage high
OE Input logic voltage low
VOE-0.3
0
5
0.3
1.0
1.0
5
V
For logic inputs INA, INB, INC, and IND
For logic input OE
IIH
µA
µA
V
IIL
VIH
VIL
1.2
0
0.3
V
RIN
CIN
Input logic impedance to GND
Logic input capacitance
12
20
5
30
10
KΩ
pF
Outputs (VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25°C)
Sym.
Parameter
Min.
Typ. Max.
Units
Conditions
Ω
Ω
A
A
RSINK
Output sink resistance
12.5
12.5
ISINK = 50mA
RSOURCE
ISINK
Output source resistance
Peak output sink current
Peak output source current
ISOURCE = 50mA
2.0
2.0
ISOURCE
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MD1811
AC Electrical Characteristics (VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25°C)
Sym.
tirf
Parameter
Min.
Typ.
Max.
Units
ns
Conditions
Input or OE rise & fall time
10
Logic input edge speed requirement
Propagation delay when output
is from low to high
Propagation delay when output
is from high to low
tPLH
7
7
ns
tPHL
ns
CLOAD = 1000pF, see timing diagram
Input signal rise/fall time 2ns
tPOE
Propagation delay OE to output
Output rise time
9
6
ns
ns
ns
ns
tr
tf
Output fall time
6
l tr - tf l
Rise and fall time matching
1.0
for each channel
Propagation low to high and
high to low matching
l tPLH-tPHL
l
1.0
2.0
ns
ns
∆tdm
Propagation delay matching
Device to device delay match
Logic Truth Table
Logic Inputs
Output
OE
H
INA
INB
L
OUTA
VH
OUTB
L
L
VH
VL
H
H
VH
H
H
L
VL
VH
H
H
H
VL
VL
L
X
X
VH
VL
OE
H
INC
L
IND
L
OUTC
VH
OUTD
VH
H
L
H
VH
VL
H
H
L
VL
VH
H
H
H
VL
VL
L
X
X
VH
VL
V
vs V
Timing Diagram and VTH / VOE Curve
TH
OE
VTH
2.0
VOE/2
1.8V
50%
50%
IN
1.5
0V
tPLH
tPHL
1.0
12V
OUT
0.6V
90%
90%
0.5
0
10%
10%
0V
tr
t
f
0
1.0
2.0
3.0
4.0
5.0
VOE
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MD1811
Simplified Block Diagram
VDD
VH
MD1811
OE
OUTA
OUTB
INA
INB
OUTC
OUTD
INC
IND
GND
VSS
VL
Detailed Block Diagram
VH
VDD
Level
Shifter
OE
OUTA
Level
Shifter
INA
VSS
VDD
V
VLH
OUTB
OUTC
OUTD
Level
INB
Shifter
VSS
VDD
VL
VH
Level
Shifter
INC
IND
VSS
VDD
V
VLH
Level
Shifter
SUB
VL
VSS
GND
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MD1811
Application Information
For proper operation of the MD1811, low inductance bypass next to the chip pins. A ceramic capacitor of up to 1.0µF may be
capacitors should be used on the various supply pins. The GND appropriate, with a series ferrite bead to prevent resonance in the
pin should be connected to the logic ground. The INA, INB INC, power supply lead coming to the capacitor. Pay particular attention
IND, and OE pins should be connected to a logic source with a to minimizing trace lengths, current loop area and using sufficient
swing of GND to VLL, where VLL is 1.2 to 5.0 volts. Good trace trace width to reduce inductance. Surface mount components are
practices should be followed corresponding to the desired operating highly recommended. Since the output impedance of this driver is
speed. The internal circuitry of the MD1811 is capable of operating very low, in some cases it may be desirable to add a small series
up to 100MHz, with the primary speed limitation being the loading resistance in series with the output signal to obtain better waveform
effects of the load capacitance. Because of this speed and the transitions at the load terminals. This will of course reduce the
high transient currents that result with capacitive loads, the bypass output voltage slew rate at the terminals of a capacitive load.
capacitors should be as close to the chip pins as possible. Unless
the load specifically requires bipolar drive, the VSS, and VL pins Pay particular attention that parasitic couplings are minimized from
should have low inductance feed-through connections directly to a the output to the input signal terminals. The parasitic feedback may
ground plane. If these voltages are not zero, then they need bypass cause oscillations or spurious waveform shapes on the edges of
capacitors in a manner similar to the positive power supplies. The signal transitions. Since the input operates with signals down to
power connection V should have a ceramic bypass capacitor to 1.2V even small coupled voltages may cause problems. Use of
the ground plane wiDthD short leads and decoupling components to a solid ground plane and good power and signal layout practices
prevent resonance in the power leads.
will prevent this problem. Be careful that a circulating ground
return current from a capacitive load cannot react with common
The voltages of VH and VL decide the output signal levels. These inductance to cause noise voltages in the input logic circuitry.
two pins can draw fast transient currents of up to 2A, so they
should be provided with an appropriate bypass capacitor located
Pin Description
VDD
High side analog circuit, level shifter and gate drive supply voltage.
Low side analog circuit, level shifter and gate drive supply voltage. VSS must be connected to the most negative
potential of voltage supplies and powered-up first.
VSS
VH
Supply voltage for P-channel output stage
Supply voltage for N-channel output stage
Logic input ground reference
VL
GND
Output-Enable logic input. When OE is high, (V +V )/2 sets the logic threshold level for inputs, When OE is low,
OUTA and OUTC are at VH, OUTB and OUTD aOreE atGVNLD, regardless of the inputs INA, INB, INC or IND. Keep OE
low until IC powered up
OE
INA, INB,
INC, IND
Logic input. Controls output when OE is high. Input logic high will cause the output to swing to VL. Input logic low
will cause the output to swing to VH. Keep all logic inputs low until IC powered up.
Output driver. Swings from VH to V . Intended to drive the gate of an external P-channel MOSFET via a series
capacitor. When OE is low, the outLput is disabled. OUTA will swing to VH turning off the external P-channel
MOSFET.
OUTA
OUTB
OUTC
Output driver. Swings from VH to V . Intended to drive the gate of an external N-channel MOSFET via a series
capacitor. When OE is low, the outLput is disabled. OUTB will swing to VL turning off the external N-channel
MOSFET.
Output driver. Swings from VH to V . Intended to drive the gate of an external P-channel MOSFET via a series
capacitor. When OE is low, the outLput is disabled. OUTC will swing to VH turning off the external P-channel
MOSFET.
Output driver. Swings from VH to V . Intended to drive the gate of an external N-channel MOSFET via a series
capacitor. When OE is low, the outLput is disabled. OUTD will swing to VL turning off the external N-channel
MOSFET.
OUTD
Substrate
The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally.
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MD1811
Pin Configuration
Pin #
1
Function
INB
2.64
16
13
2
VL
3
GND
VL
4
1
4
12
5
INC
6
IND
QFN-16
4x4x0.9
2.64
7
VSS
8
OUTD
OUTC
VH
9
9
10
11
12
13
14
15
16
VH
OUTB
OUTA
VDD
5
8
0.65
0.325
0.28
INA
(Top View, mm)
OE
Thermal Pad, and Pin #7 (V ), must be
connected externaSllSy
Note
Doc.# DSFP - MD1811
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