MD1812 [SUPERTEX]

High Speed Quad MOSFET Driver; 高速四通道MOSFET驱动器


型号：	MD1812
厂家：	Supertex, Inc
描述：	High Speed Quad MOSFET Driver 高速四通道MOSFET驱动器驱动器
文件：	总6页 (文件大小：220K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MD1812

Supertex inc.

Initial Release

High Speed Quad MOSFET Driver

General Description

Features

The Supertex MD1812 is a hiꢀh-speed quad MOSFET driver. It is

desiꢀned to drive two N and two P-channel hiꢀh voltaꢀe DMOS FETs for

medical ultrasound applications but may be used in any application that

needs a hiꢀh output current for a capacitive load. The input staꢀe of the

MD1812 is a hiꢀh-speed level translator that is able to operate from loꢀic

input siꢀnals of 1.2 to 5.0 volt amplitude. An adaptive threshold circuit

is used to set the level translator threshold to the averaꢀe of the input

loꢀic 0 and loꢀic 1 levels. The level translator uses a proprietary circuit,

which provides DC couplinꢀ toꢀether with hiꢀh-speed operation. The

output staꢀe of the MD1812 has separate power connections enablinꢀ

the output siꢀnal L and H levels to be chosen independently from the

driver supply voltaꢀes.

♦

6ns rise and fall time

2A peak output source/sink current

1.2V to 5V input CMOS compatible

5V to 12V supply voltaꢀe operation

Smart Loꢀic threshold

Low jitter desiꢀn

Quad matched channels

Drives two N and two P-channel MOSFETs

Outputs can swinꢀ below ꢀround

Built-in level translator for neꢀative ꢀate bias

User-deﬁned dampinꢀ for return-to-zero application

Low inductance quad ﬂat no-lead packaꢀe

Thermally-enhanced packaꢀe

As an example, the input loꢀic levels may be 0V and 1.8V, the control

loꢀic may be powered by +5V and –5V, and the output L and H levels

may be varied anywhere over the ranꢀe of –5V to +5V. The output staꢀe

is capable of peak currents of up to 2 amps, dependinꢀ on the supply

voltaꢀes used and load capacitance. The OE pin serves a dual purpose.

First, its loꢀic H level is used to compute the threshold voltaꢀe level for the

channel input level translators. Secondly, when OE is low, the outputs are

disabled, with the A and C outputs hiꢀh and the B and D outputs low. This

assists in properly pre-charꢀinꢀ the couplinꢀ capacitors that may be used

in series in the ꢀate drive circuit of an external PMOS and NMOS. A built-

in level shifter provides P-MOS ꢀate neꢀative bias drive. This enables the

user-deﬁned dampinꢀ control to ꢀenerate return-to-zero bipolar output

pulses.

Applications

♦

Ultrasound PN code transmitter

Medical ultrasound imaꢀinꢀ

Piezoelectric transducer drivers

Nondestructive evaluation

Hiꢀh speed level translator

Hiꢀh voltaꢀe bipolar pulser

Typical Application Circuit

+100V

+10V

1 F

0.22 F

0.47 F

V_H

V_DD

10nF

IN_A

OUT_A

10nF

-100V

1 F

OUT_B

OUT_G

OUT_C

IN_B

3.3V CMOS

Loꢀic Inputs

Supertex

TC6320

IN_C

IN_D

OUT_D

V_SS

V_L

GND

V_NEG

10nF

-10V

0.47 F

Supertex

MD1812

Supertex

TC2320

NR031706

Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com

MD1812

Package Option

16-lead 4x4x0.9 QFN

MD1812K6-G

Device

MD1812

-G indicates package is RoHS compliant (‘Green’)

16-Lead QFN (K6) Pin Conﬁguration

16-Lead QFN (K6) Package

MD1812

Top View

Pin Description

Pin #

Function

IN_B

Description

Loꢀic input. Controls OUT_Bwhen OE is hiꢀh._.

Supply voltaꢀe for N-channel output staꢀe.

Device ꢀround.

V_L

GND

V_NEG

IN_C

Supply voltaꢀe the auxiliary ꢀate drive.

Loꢀic input. Controls OUT_Cwhen OE is hiꢀh.

Loꢀic input. Controls OUT_Dwhen OE is hiꢀh.

IN_D

V_SS

Supply voltaꢀe for low-side analoꢀ, level shifter, and ꢀate drive circuit.

OUT_D

OUT_C

OUT_G

V_H

Output driver.

Auxiliary output driver.

Supply voltaꢀe for P-channel output staꢀe

Output driver.

OUT_B

OUT_A

V_DD

Output driver.

Supply voltaꢀe for hiꢀh-side analoꢀ, level shifter, and ꢀate drive circuit.

Loꢀic input. Controls OUT_Awhen OE is hiꢀh.

Output enable loꢀic input.

IN_A

Note: Thermal pad and pin #4, V_NEGmust be connected externally.

NR031706

MD1812

Absolute Maximum Ratings

Parameter

Value

V_DD-V_SS, Loꢀic Supply Voltaꢀe

V_H, Output Hiꢀh Supply Voltaꢀe

V_L, Output Low Supply Voltaꢀe

Vss, Low Side Supply Voltaꢀe

V_NEG-V_SS, Neꢀative Supply Voltaꢀe

Loꢀic Input Levels

-0.5V to +13.5V

V_L-0.5V to V_DD+0.5V

V_SS-0.5V to V_H+0.5V

-7V to +0.5V

V_SS-13.5V to V_SS+0.5V

V_SS-0.5V to V_SS+7V

+125°C

Maximum Junction Temperature

Storaꢀe Temperature

-65°C to 150°C

235°C

Solderinꢀ Temperature

Packaꢀe Power Dissipation

2.2W

Absolute Maximum Ratings are those values beyond which damage to the

device may occur. Functional operation under these conditions is not implied.

Continuous operation of the device at the absolute rating level may affect

device reliability. All voltages are referenced to device ground.

DC Electrical Characteristics

(V_H= V_DD= 12V, V_L= V_SS= GND = 0V, V_NEG= -12V, V_OE= 3.3V, T_J= 25^OC)

Symbol Parameter

Min

Typ Max Units Conditions

---

V_DD- V_SS

V_SS

V_H

Loꢀic supply voltaꢀe

4.5

Low side supply voltaꢀe

Output hiꢀh supply voltaꢀe

Output low supply voltaꢀe

Neꢀative supply voltaꢀe

V_DDquiescent current

V_Hquiescent current

-5.5

V_SS+2

V_DD

V_DD-2

V_SS-2

V_L

V_SS

V_NEG

I_DDQ

I_HQ

-13

May connect to V_SSif OUT_Gnot used

1.5

µA

No input transitions, OE = 1

I_NEGQ

I_DD

V_NEGquiescent current

V_DDaveraꢀe current

7.0

1.5

I_H

V_Haveraꢀe current

One channel on at 5.0Mhz, No load

For loꢀic inputs IN_A, IN_B, IN_C, and IN_D

I_NEG

V_IH

V_NEGaveraꢀe current

Input loꢀic voltaꢀe hiꢀh

Input loꢀic voltaꢀe low

Input loꢀic current hiꢀh

Input loꢀic current low

OE Input loꢀic voltaꢀe hiꢀh

OE Input loꢀic voltaꢀe low

Input loꢀic impedance to GND

Loꢀic input capacitance

V_OE-0.3

V_IL

0.3

1.0

I_IH

µA

I_IL

V_IH

1.2

V_IL

0.3

For loꢀic input OE

R_IN

C_IN

KΩ

---

NR031706

MD1812

Outputs

(V_H= V_DD= 12V, V_L= V_SS= GND = 0V, V_NEG= -12V, V_OE= 3.3V, T_J= 25^OC)

Symbol Parameter

Min

Typ Max Units Conditions

R_SINK

Output sink resistance

12.5

Ω

I_SINK= 50mA

R_SOURCE

I_SINK

Output source resistance

Peak output sink current

Peak output source current

12.5

I_SOURCE= 50mA

2.0

---

I_SOURCE

AC Electrical Characteristics

(V_H= V_DD= 12V, V_L= V_SS= GND = 0V, V_NEG= -12V, V_OE= 3.3V, T_J= 25^OC)

Symbol

Parameter

Min

Typ Max Units Conditions

t_irf

Input or OE rise & fall time

Loꢀic input edꢀe speed requirement

Propaꢀation delay when output is

from low to hiꢀh

Propaꢀation delay when output is

from hiꢀh to low

t_PLH

t_PHL

C_LOAD= 1000pF, see timinꢀ diaꢀram

Input siꢀnal rise/fall time 2ns

t_POE

t_PCG

t_r

Propaꢀation delay OE to output

Propaꢀation delay IN_Cto OUT_G

Output rise time

t_f

Output fall time

l t_r- t_fl

Rise and fall time matchinꢀ

1.0

for each channel

Propaꢀation low to hiꢀh and hiꢀh

to low matchinꢀ

l t_PLH-t_PHL

∆t_dm

1.0

2.0

Propaꢀation delay matchinꢀ

Device to device delay match

Logic Truth Table

Logic Inputs

Output

IN_A

IN_B

OUT_A

V_H

OUT_B

V_H

V_L

V_H

V_L

V_H

V_L

V_H

V_L

IN_C

IN_D

OUT_C

V_H

OUT_G

V_SS

OUT_D

V_H

V_SS

V_L

V_NEG

V_SS

V_H

V_L

V_H

V_L

NR031706

MD1812

Application Information

For proper operation of the MD1812, low inductance bypass The voltaꢀes of V_Hand V_Ldecide the output siꢀnal levels. These

capacitors should be used on the various supply pins. The GND pin two pins can draw fast transient currents of up to 2A, so they

should be connected to the loꢀic ꢀround. The IN , IN , IN_C, IN and should be provided with an appropriate bypass capacitor located

OE pins should be connected to a loꢀic source w^Aith a^Bswinꢀ of^DGND next to the chip pins. A ceramic capacitor of up to 1.0µF may be

to V , where V_CCis 1.2 to 5.0 volts. When input loꢀic(s) is hiꢀh, appropriate, with a series ferrite bead to prevent resonance in the

outp^Cu^Ct(s) will swinꢀ to V_L, and when input(s) loꢀic is low, output(s) will power supply lead cominꢀ to the capacitor. Pay particular attention

swinꢀ to V_H. All inputs must be kept low until the device is powered to minimizinꢀ trace lenꢀths, current loop area, and usinꢀ sufﬁcient

up. Good trace practices should be followed correspondinꢀ to the trace width to reduce inductance. Surface mount components are

desired operatinꢀ speed. The internal circuitry of the MD1812 is hiꢀhly recommended. Since the output impedance of this driver is

capable of operatinꢀ up to 100MHz, with the primary speed limitation very low, in some cases it may be desirable to add a small series

beinꢀ the loadinꢀ effects of the load capacitance. Because of this resistance in series with the output siꢀnal to obtain better waveform

speed and the hiꢀh transient currents that result with capacitive transitions at the load terminals. This will reduce the output voltaꢀe

loads, the bypass capacitors should be as close to the chip pins as slew rate at the terminals of a capacitive load.

possible. Unless the load speciﬁcally requires bipolar drive, the V_SS

and V pins should have low inductance feed-throuꢀh connections The OE pin sets the threshold level of loꢀic for inputs (V_OE+ V_GND

)

directl^Ly to a ꢀround plane. If these voltaꢀes are not zero, then they / 2. When OE is low, OUT_Aand OUT are at V_H. OUT_Band OUT_D

need bypass capacitors in a manner similar to the positive power are at V_L. Auxiliary output OUT_G, is at^CV_SS, reꢀardless of the inputs

supplies. The power connection V_DDshould have a ceramic bypass IN_Aor IN_B.

capacitor to the ꢀround plane, with short leads and decouplinꢀ

components to prevent resonance in the power leads.

Pay particular attention that parasitic couplinꢀs are minimized from

the output to the input siꢀnal terminals. The parasitic feedback may

Output drivers, OUT_Aand OUT , drive the ꢀate of an external P- cause oscillations or spurious waveform shapes on the edꢀes of

channel MOSFET, while output^Cdrivers OUT and OUT_Ddrive the siꢀnal transitions. Since the input operates with siꢀnals down to

ꢀate of an external N-channel MOSFET, an^Bd they all swinꢀ from 1.2V, even small coupled voltaꢀes may cause problems. Use of

V_Hto V . The auxiliary output drive, OUT_G, swinꢀs from V_SSto V_NEG

a solid ꢀround plane and ꢀood power and siꢀnal layout practices

and driv^Les the ꢀate of an external P-channel MOSFET via a 2KΩ will prevent this problem. Be careful that a circulatinꢀ ꢀround

series resistor.

return current from a capacitive load cannot react with common

inductance to cause noise voltaꢀes in the input loꢀic circuitry. Best

timinꢀ performance is obtained for OUT_Cwhen the voltaꢀe of (V_SS-

V_NEG) = (V_H-V_L).

NR031706

MD1812

16-Lead QFN Package Outline (K6)

Datum A or B

D/2

INDEX AREA

(D/2 xE/2)

-B-

Chamfer/Radius

e/2

N-1

Terminal Tip

Symbol

Height Dimensions

Tolerance of Form &

Position

aaa

C 2x

Min

Nom

4.0

Max

TOP VIEW

aaa

bbb

ccc

0.15

0.10

0.05

D BSC

ccc C

0.08 C

E BSC

4.0

SEATING

PLANE

-C-

SIDE VIEW

0.65

2.15

0.30

0.55

0.90

0.02

0.20 ref

---

ddd

Issue

2.0

2.25

0.35

0.65

1.0

D2/2

0.25

0.45

0.80

0.00

---

Issue

0.05

---

-B-

0.03

0.15

NXb

bbb

N-1

INDEX AREA

(D/2 xE/2)

A B

ddd

Bottom ID Dimensions

BTM VIEW

SEE

DETAIL B

.344

.181

Notes:

1. Dimensioning and tolerancing conform to ASME Y14.5m - 1994.

2. All dimensions are in millimeters, all angles are in degrees (^O).

3. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95, SPP-002. Details of terminal #1 identifier are

optional, but must be located within the zone indicated. The terminal #1identifier may be either a mold or marked feature.

4. Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to or greater than

0.33mm.

5. Dimension B applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminalhas the optional radius

on the other end of the terminal, the dimension B should not be measured in that radius area.

(The package drawing(s) in this data sheet may not reﬂect the most current speciﬁcations. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Supertex inc. does not recommend the use of its products in life support applications, and will not knowinꢀly sell its products for use in such applications, unless it receives an adequate

"product liability indemnification insurance aꢀreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices

determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to chanꢀe without notice. For the latest

product specifications, refer to the Supertex website: http//www.supertex.com.

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 / FAX: (408) 222-4895

Doc.# DSFP - MD1812

NR031706

www.supertex.com

MD1812 [SUPERTEX]

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