HV9931P-G [SUPERTEX]
LED Driver, 1-Segment, PDIP8, GREEN, PLASTIC, DIP-8;
| 型号： | HV9931P-G |
| 厂家： | 
Supertex, Inc |
| 描述： | LED Driver, 1-Segment, PDIP8, GREEN, PLASTIC, DIP-8 驱动 光电二极管 接口集成电路 |
| 文件： | 总7页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV9931
Initial Release
HV9931 Unity Power Factor LED Lamp Driver
Features
General Description
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Constant Output Current
The HV9931 is a fixed frequency PWM controller IC designed
to control an LED lamp driver using a single-stage PFC
buckboost-buck topology. It can achieve a unity power factor
and a very high step-down ratio that enables driving a single
high-brightness LED from the 85-264VAC input without a
need for a power transformer. This topology allows reducing
the filter capacitors and using non-electrolytic capacitors to
improve reliability. The HV9931 uses open-loop peak current
control to regulate both the input and the output current. This
control technique eliminates a need for loop compensation,
limits the input inrush current, and is inherently protected
from input under-voltage condition. Capacitive isolation
protects the LED Lamp from failure of the switching MOSFET.
HV9931 provides a low-frequency PWM dimming input that
can accept an external control signal with a duty ratio of 0-
100% and a frequency of up to a few kilohertz. The PWM
dimming capability enables HV9931 phase control solutions
that can work with standard wall dimmers.
Large Step-Down Ratio
Unity Power Factor
Low Input Current Harmonic Distortion
Fixed Frequency or Fixed Off-Time Operation
Internal 450V Linear Regulator
Input and output current sensing
Input Current limit
Enable, PWM and Phase Dimming
Applications
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Offline LED Lamps and Fixtures
Street lamps
Traffic Signals
Decorative Lighting
Typical Application Circuit
D1
L1
L2
C1
D4
D2
VIN
-
CIN
Q1
D3
VO
~AC
~AC
RS1
RS2
+
RCS2
RCS1
Rref1
Rref2
HV9931
R
T
VIN
GATE
RT
PWMD
CS1
CS2
VDD
GND
C2
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HV9931
Ordering Information
Package Options
DEVICE
8-Lead SOIC
8-Lead DIP
HV9931
HV9931LG-G
HV9931P-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
VIN to GND
-0.5V to +470V
VDD to GND
-0.3V to +13.5V
CS1, CS2 to GND
PWMD to GND
GATE to GND
-0.3V to VDD + 0.3V
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
-
Continuous Power Dissipation (TA = +25°C) Also limited by package power dissipation limit, whichever is lower.
8-Pin DIP (derate 9mW/°C above +25°C)
8-Pin and 14-Pin SO (derate 6.3mW/°C above +25°C)
Operating Temperature Range
900mW
630mW
-40°C to +85°C
+125°C
Junction Temperature
Storage Temperature Range
-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Electrical Characteristics
(The * denotes the specifications which apply over the full operating junction temperature range of -40°C < TA < +85°C, otherwise the specifications are at
TA = 25°C, VIN = 100V, unless otherwise noted)
Symbol Parameter
Input
Min
Typ Max Units Conditions
VINDC
IINSD
Internal Regulator
Input DC supply voltage range*
8
450
1
V
DC input voltage
Shut-Down mode supply current*
0.5
mA
PWMD connected to GND, VIN = 12V
VDD
Internally regulated voltage*
7.12
6.45
7.5
6.7
7.88
6.95
V
V
VIN = 8–450V, IDD(ext) = 0, GATE open
VIN rising
UVLO
∆UVLO
V
DD undervoltage lockout threshold
DD undervoltage lockout hysteresis
V
500
mV
PWM Dimming
VPWMD(lo)
VPWMD(hi)
RPWMD
GATE
VGATE(hi)
VGATE(lo)
TRISE
PWMD input low voltage*
1.0
V
V
VIN = 8–450V
VIN = 8–450V
VPWMD = 5V
PWMD input high voltage*
PWMD pull-down resistance
2.4
50
100
150
kΩ
GATE high output voltage*
GATE low output voltage*
GATE output rise time
GATE output fall time
Delay from CS trip to GATE
Blanking delay
VDD-0.3
0
VDD
0.3
50
V
IGATE = 10mA
V
IGATE = -10mA
30
30
ns
ns
ns
ns
CGATE = 500pF
TFALL
50
CGATE = 500pF
TDELAY
TBLANK
150
215
300
280
VIN = 12V, VCSI, VCS2 = -50mV
VCSI, VCS2 = -0.15V
150
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HV9931
Symbol Parameter
Oscillator
Min
Typ Max Units Conditions
FOSC
∆FT
Initial Accuracy
80
100
3
120
kHz
%
RT = 230K
Temperature Stability
Tj = -40°C to +125°C
Comparators
VOFFSET1
VOFFSET2
Comparator Input offset voltage*
-12
12
mV
∆VOFFSET1
∆VOFFSET2
Input offset voltage temperature drift
10
µV/°C Tj = -40°C to +125°C
Pin Description
Pinout
VIN – This pin is the input of a high voltage regulator.
SOIC-8, DIP-8
V
DD – This is a power supply pin for all internal circuits. It must be bypassed with a low
ESR capacitor to GND.
1
8
7
VIN
RT
GATE – This pin is the output gate driver for an external N-channel power MOSFET.
2
3
4
CS2
CS1
GND
GND – Ground return for all the internal circuitry. This pin must be electrically connected
to the ground of the power train.
HV9931
6
VDD
RT – Oscillator control. A resistor connected between this pin and GND sets the PWM
frequency. A resistor connected between this pin and GATE sets the PWM off-time.
5
PWMD
GATE
PWMD – When this pin is pulled to GND, switching of the HV9931 is disabled. When the
PWMD pin is released, or external TTL high level is applied to it, switching will resume.
This feature is provided for applications that require PWM dimming of the LED lamp.
CS1 and CS2 – These pins are used to sense the input and output currents of the
converter. They are the inverting inputs of the internal comparators.
Functional Block Diagram
VIN
REGULATOR
VDD
7.5V
RT
OSC
CS1
S
R
Q
GATE
CS2
AGND
PWMD
HV9931
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HV9931
Typical Performance Characteristics (TJ = 25OC, VIN=100V unless otherwise noted)
VDD vs. Junction Temperature (LIN = 2mA)
Blanking Delay vs. Junction Temperature
7.7
7.65
7.6
300
250
200
150
100
50
7.55
7.5
7.45
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
Frequency vs. Junction Temperature (RT = 226K)
VDD vs. Regulator Current (VIN = 100V)
8
7.5
7
93
92
91
90
89
88
6.5
6
5.5
5
4.5
4
0
2
4
6
8
10
12
14
16
18
20
-40
-20
0
20
40
60
80
100
120
IIN (mA)
Junction Temperature (°C)
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HV9931
Functional Description
than the output one. Therefore, disabling the HV9931 via its PWMD
or VIN pins can interrupt the output LED current in accordance with
the phase-controlled voltage waveform of a standard wall dimmer.
Power Topology
The HV9931 is optimized to drive Supertex’s proprietary single-
stage, single-switch, non-isolated topology, cascading an input
power factor correction (PFC) buck-boost stage and an output
buck converter power stage. This power converter topology offers
numerous advantages useful for driving high-brightness light
emitting diodes (HB LED). These advantages include unity power
factor, low harmonic distortion of the input AC line current, and low
output current ripple. The output load is decoupled from the input
voltage with a capacitor making the driver inherently failure-safe for
the output load. The power converter topology also permits reducing
the size of a filter capacitor needed, enabling use of non-electrolytic
capacitors. The latter advantage greatly improves reliability of the
overall solution.
Oscillator
Connecting an external resistor from RT pin to GND programs
switching frequency:
25000
F kHz =
S [ ]
R KΩ + 22
T [ ]
Connecting the resistor from RT pin to GATE programs constant
off-time:
R KΩ + 22
T [ ]
TOFF µs =
[ ]
25
The HV9931 is a peak current-mode controller that is specifically
designed to drive a constant current buckboost-buck power
converter. This patent pending control scheme features two identical
current sense comparators for detecting negative current signal
levels. One of the comparators regulates the output LED current.
The other one is used for sensing the input inductor current. The
second comparator is mainly responsible for the converter start-
up. The control scheme inherently features low inrush current
and input under-voltage protection. The HV9931 can operate with
programmable constant frequency or constant off-time. In many
cases, the constant off-time operating mode is preferred, since
it improves line regulation of the output current, reduces voltage
stress of the power components and simplifies regulatory EMI
compliance. (See Application Note AN-H52.)
Input and Output Current Feedback
Two current sense comparators are included in the HV9931. Both
comparators have their non-inverting inputs internally connected to
ground (GND). The CS1 and CS2 inputs are inverting inputs of the
comparators. Connecting a resistor divider into either of these inputs
from a positive reference voltage and a negative current sense
signal programs the current sense threshold of the comparator. The
VDD voltage of the HV9931 can be used as the reference voltage.
(If more accuracy is needed, an external reference voltage can be
applied.) When either the CS1 or the CS2 pin voltage falls below
GND, the GATE pulse is terminated. A leading edge blanking delay
of 215ns (typ) is added. The GATE voltage becomes high again
upon receiving the next clock pulse of the oscillator circuit.
Input Voltage Regulator
The HV9931 can be powered directly from its VIN pin and takes a
voltage from 8V to 450V. When a voltage is applied at the VIN pin,
the HV9931 seeks to maintain a constant 7.5V at the V pin. The
VDD voltage can be also used as a reference for the curDreD nt sense
comparators. The regulator is equipped with an under-voltage
protection circuit which shuts off the HV9931 when the voltage at
the VDD pin falls below 6.2V.
Referring to the Functional Circuit Diagram, the CS2 comparator is
responsible for regulating output current. The output LED current
can be programmed using the following equation:
1
Io + ∆IL2
2
RCS 2
=
⋅ RREF 2 ⋅ RS 2
7.5V
The V pin must be bypassed by a low ESR capacitor (≥ 0.1µF) to
providDeDa low impedance path for the high frequency current of the
output gate driver.
where ∆I is the peak-to-peak current ripple in L2. The CS1
comparatLo2r limits the current in the input inductor L1. There is
no charge in the capacitor C1 upon the start-up of the converter.
Therefore, L2 cannot develop the output current, and the HV9931
starts-up in the input current limiting mode. The CS1 current
threshold must be programmed such that no input current limiting
occurs in normal steady-state operation. The CS1 threshold can be
programmed in accordance with a similar equation:
The HV9931 can also be operated by supplying a voltage at the VDD
pin greater than the internally regulated voltage. This will turn off
the internal linear regulator and the HV9931 will function by drawing
power from the external voltage source connected to the VDD pin.
IL1( PK )
RCS1
=
⋅ RREF1 ⋅ RS1
PWM Dimming and Wall Dimmer Compatibility
7.5V
PWM Dimming can be achieved by applying a TTL-compatible
square wave signal at the PWMD pin. When the PWMD pin is
pulled high, the gate driver is enabled and the circuit operates
normally. When the PWMD pin is left open or connected to GND,
the gate driver is disabled and the external MOSFET turns off. The
HV9931 is designed so that the signal at the PWMD pin inhibits the
driver only, and the IC need not go through the entire start-up cycle
each time ensuring a quick response time for the output current.
where IL1(PK) is the maximum peak current in L1.
MOSFET Gate Driver
Typically, the gate driving capability of the HV9931 is limited by the
amount of power dissipation in its linear regulator. Thus, care must
be taken selecting a switching MOSFET to be used in the circuit.
An optimal trade-off must be found between the gate charge and
the on-resistance of the MOSFET to minimize the input regulator
current.
The power topology requires little filter capacitance at the output,
since the output current of the buck stage is continuous, and since
AC line filtering is accomplished through the middle capacitor rather
NR081505
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HV9931
Functional Circuit Diagram
D1
L1
L2
iL2
D4
C1
D2
VIN
-
_
VC1
iL1
+
CIN
Q1
D3
VO
~AC
~AC
RCS1
RS1
VS1
RS2
+
_
_
VS2
+
+
RT
RCS2
GATE
PWMD
RT
OSC
S Q
R
CS2
CS1
R
ref1
Rref2
REG
VIN
HV9931
VDD
GND
7. 5V
CDD
Switching Waveform
VDD
GATE
0
t
t
iL2
0
iL1
0
t
NR081505
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HV9931
8-Lead Small Outline Package (LG)
0.192 0.005
(4.8895 0.1143)
D
H
0.236 0.008
(5.9944 0.2032)
0.154 0.004
H
E
1
0.193 0.012
(3.9116 0.1016)
(4.9022 0.3048)
0.020 0.009
(0.508 0.2286)
h
7° (4 PLCS)
0.010 0.002
(0.254 0.0508)
C
45°
0.061 0.008
A
L
1
(1.5494 0.2032)
0° - 8 °
e
B
A
1
0.0275 0.0025
(0.6985 0.0635)
L
0.050
(1.270)
0.016 0.002
(0.4064 0.0508)
0.035 0.015
(0.889 0.381)
0.007 0.003
(0.1778 0.0762)
TYP.
8-Lead Plastic Dual In-Line Package (P)
0.040
(1.016)
TYP
0.395 max
0.250
0.015
0.250
0.005
0.030 -
0.110
1
0.300 - 0.320
0.130 0.005
0.125 min.
0.020
0° - 10°
0.020 min.
0.018 0.003
0.100 0.010
0.009 - 0.015
+0.025
-0.015
0.325
Dimensions in Inches
(Dimensions in Millimeters)
Note: Circle (e.g. B ) indicates JEDEC Reference.
Measurement Legend =
Doc.# DSFP - HV9931
NR081505
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