HV9931_07 [SUPERTEX]
HV9931 Unity Power Factor LED Lamp Driver; HV9931的高功率因数LED灯驱动器
| 型号： | HV9931_07 |
| 厂家： | 
Supertex, Inc |
| 描述： | HV9931 Unity Power Factor LED Lamp Driver |
| 文件： | 总8页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV9931
HV9931 Unity Power Factor LED Lamp Driver
Features
► Constant output current
► Large step-down ratio
► Unity power factor
► Low Input current harmonic distortion
► Fixed frequency or fixed off-time operation
► Internal 450V linear regulator
► Input and output current sensing
► Input current limit
General Description
The HV9931 is a fixed frequency PWM controller IC designed
to control an LED lamp driver using a single-stage PFC
buckboost-buck topology. It can achieve a unity power factor
and a very high step-down ratio that enables driving a single
high-brightness LED from the 85-264VAC input without a
need for a power transformer. This topology allows reducing
the filter capacitors and using non-electrolytic capacitors to
improve reliability. The HV9931 uses open-loop peak current
control to regulate both the input and the output current. This
control technique eliminates a need for loop compensation,
limits the input inrush current, and is inherently protected from
input under-voltage condition.
► Enable, PWM and phase dimming
Applications
Capacitive isolation protects the LED Lamp from failure of the
switching MOSFET. HV9931 provides a low-frequency PWM
dimming input that can accept an external control signal with a
duty ratio of 0-100% and a frequency of up to a few kilohertz.
The PWM dimming capability enables HV9931 phase control
solutions that can work with standard wall dimmers.
► Offline LED lamps and fixtures
► Street lamps
► Traffic signals
► Decorative lighting
Typical Application Circuit
D1
L2
L1
C1
D4
D2
VIN
-
D3
Q1
VO
CIN
~AC
~AC
RS2
RS1
+
RCS2
RCS1
Rref2
Rref1
RT
VIN
RT
GATE
CS1
PWMD
CS2
GND
VDD
C2
HV9931
HV9931
Ordering Information
Package Options
DEVICE
8-Lead SOIC (Narrow Body)
HV9931
HV9931LG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
VIN to GND
Pin Configuration
Value
-0.5V to +470V
1
2
3
4
VIN
CS1
GND
RT
8
7
6
5
VDD to GND
CS1, CS2 to GND
-0.3V to +13.5V
-0.3V to VDD + 0.3V
CS2
HV9931
PWMD to GND
GATE to GND
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
VDD
Continuous Power Dissipation (TA = +25°C)
Also limited by package power dissipation limit, whichever is lower.
PWMD
GATE
8-Lead SOIC (derate 9mW/°C
above +25°C)
900mW
8-Lead SOIC
Operating temperature range
Junction temperature
Storage temperature range
Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
-40°C to +85°C
+125°C
-65°C to +150°C
Product Marking
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
YWW
H9931
LLLL
= “Green” Packaging
8-Lead SOIC
Electrical Characteristics
(The * denotes the specifications which apply over the full operating junction temperature range of -40°C < TA < +85°C, otherwise the specifications are
at TA = 25°C, VIN = 12V, unless otherwise noted)
Symbol Parameter
Input
Min
Typ Max Units Conditions
VINDC
Input DC supply voltage range*
8
-
-
450
1
V
DC input voltage
Shut-down mode supply
current*
IINSD
0.5
mA
PWMD connected to GND, VIN = 12V
Internal Regulator
VIN = 8, IDD(ext) = 0, PWMD = VDD,
CGATE = 500pF
VDD
Internally regulated voltage*
7.12
0
7.5
7.88
1
V
V
VIN = 8 - 450V, IDD(ext) = 0, 500pF at
GATE; RT = 226kΩ, PWMD = VDD
VDD, line
VDD, load
Line regulation of VDD
Load regulation of VDD
-
-
IDD(ext) = 0 – 1mA, 500pF at GATE;
RT = 226kΩ, PWMD = VDD
0
100
mV
VDD undervoltage lockout
threshold
VDD undervoltage lockout
hysteresis
UVLO
6.45
-
6.7
6.95
-
V
VIN rising
---
∆UVLO
500
mV
2
HV9931
Symbol Parameter
PWM Dimming
Min
Typ Max Units Conditions
VPWMD(lo)
VPWMD(hi)
RPWMD
PWMD input low voltage*
-
-
-
1.0
-
V
V
VIN = 8 – 450V
VIN = 8 – 450V
VPWMD = 5V
PWMD input high voltage*
PWMD pull-down resistance
2.4
50
100
150
kΩ
GATE
VGATE(hi)
GATE high output voltage*
GATE low output voltage*
GATE output rise time
GATE output fall time
Delay from CS trip to GATE
Blanking delay
VDD-0.3
-
VDD
0.3
50
V
IGATE = 10mA
IGATE = -10mA
CGATE = 500pF
CGATE = 500pF
VGATE(lo)
TRISE
0
-
V
-
30
30
150
215
ns
ns
ns
ns
TFALL
-
-
50
TDELAY
TBLANK
300
280
VIN = 12V, VCSI, VCS2 = -100mV
VCSI, VCS2 = -100mV
150
Oscillator
FOSC
Initial accuracy
80
100
-
120
15
kHz RT = 226KΩ
Comparators
VOFFSET1
VOFFSET2
Comparator Input offset voltage*
-15
mV
---
Functional Block Diagram
VIN
Regulator
VDD
7.5V
RT
Osc
CS1
S
R
Leading
Edge
Blanking
Q
GATE
CS2
AGND
PWMD
HV9931
3
HV9931
Typical Performance Characteristics (TJ = 25OC, VIN=100V unless otherwise noted)
VDD vs. Junction Temperature (LIN = 2mA)
Blanking Delay vs. Junction Temperature
7.7
7.65
7.6
300
250
200
150
100
50
7.55
7.5
7.45
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Junction Temperature (°C)
Junction Temperature (°C)
Frequency vs. Junction Temperature (RT = 226K)
VDD vs. Regulator Current (VIN = 100V)
8
7.5
7
93
92
91
90
89
88
6.5
6
5.5
5
4.5
4
0
2
4
6
8
10
12
14
16
18
20
-40
-20
0
20
40
60
80
100
120
IIN (mA)
Junction Temperature (°C)
Functional Description
Power Topology
The HV9931 is a peak current-mode controller that is
specifically designed to drive a constant current buck-
boost-buck power converter. This patent pending control
scheme features two identical current sense comparators
for detecting negative current signal levels. One of the
comparators regulates the output LED current, while the
other is used for sensing the input inductor current. The
second comparator is mainly responsible for the converter
start-up. The control scheme inherently features low inrush
current and input under-voltage protection. The HV9931 can
operate with programmable constant frequency or constant
off-time. In many cases, the constant off-time operating mode
is preferred, since it improves line regulation of the output
current, reduces voltage stress of the power components
and simplifies regulatory EMI compliance. (See Application
Note AN-H52.)
The HV9931 is optimized to drive Supertex’s proprietary
single-stage, single-switch, non-isolated topology, cascading
an input power factor correction (PFC) buck-boost stage
and an output buck converter power stage. This power
converter topology offers numerous advantages useful
for driving high-brightness light emitting diodes (HB LED).
These advantages include unity power factor, low harmonic
distortion of the input AC line current, and low output current
ripple. The output load is decoupled from the input voltage
with a capacitor making the driver inherently failure-safe for
the output load. The power converter topology also permits
reducing the size of a filter capacitor needed, enabling use
of non-electrolytic capacitors. The latter advantage greatly
improves reliability of the overall solution.
4
HV9931
Input Voltage Regulator
Input and Output Current Feedback
The HV9931 can be powered directly from its VIN pin, and Two current sense comparators are included in the HV9931.
takes a voltage from 8V to 450V. When a voltage is applied Both comparators have their non-inverting inputs internally
at the VIN pin, the HV9931 seeks to maintain a constant connected to ground (GND). The CS1 and CS2 inputs are
7.5V at the VDD pin. The VDD voltage can be also used as a inverting inputs of the comparators. Connecting a resistor
reference for the current sense comparators. The regulator divider into either of these inputs from a positive reference
is equipped with an under-voltage protection circuit which voltage and a negative current sense signal programs the
shuts off the HV9931 when the voltage at the VDD pin falls current sense threshold of the comparator. The VDD voltage
below 6.2V.
of the HV9931 can be used as the reference voltage. If more
accuracy is needed, an external reference voltage can be
The VDD pin must be bypassed by a low ESR capacitor applied. When either the CS1 or the CS2 pin voltage falls
(≥ 0.1µF) to provide a low impedance path for the high below GND, the GATE pulse is terminated. A leading edge
frequency current of the output gate driver.
blanking delay of 215ns (typ) is added. The GATE voltage
becomes high again upon receiving the next clock pulse of
The HV9931 can also be operated by supplying a voltage the oscillator circuit.
at the VDD pin greater than the internally regulated voltage.
This will turn off the internal linear regulator and the HV9931 Referring to the Functional Circuit Diagram, the CS2
will function by drawing power from the external voltage comparator is responsible for regulating output current. The
source connected to the VDD pin.
output LED current can be programmed using the following
equation:
1
PWM Dimming and
Wall Dimmer Compatibility
Io + ∆IL2
2
RCS 2
=
⋅ RREF 2 ⋅ RS 2
7.5V
PWM Dimming can be achieved by applying a TTL-
compatible square wave signal at the PWMD pin. When the
PWMD pin is pulled high, the gate driver is enabled and the
circuit operates normally. When the PWMD pin is left open
or connected to GND, the gate driver is disabled and the
external MOSFET turns off. The HV9931 is designed so that
the signal at the PWMD pin inhibits the driver only, and the
IC need not go through the entire start-up cycle each time
ensuring a quick response time for the output current.
where ∆IL2 is the peak-to-peak current ripple in L2. The CS1
comparator limits the current in the input inductor L1. There
is no charge in the capacitor C1 upon the start-up of the
converter. Therefore, L2 cannot develop the output current,
and the HV9931 starts-up in the input current limiting mode.
The CS1 current threshold must be programmed such that no
input current limiting occurs in normal steady-state operation.
The CS1 threshold can be programmed in accordance with
a similar equation:
The power topology requires little filter capacitance at
the output, since the output current of the buck stage is
continuous, and since AC line filtering is accomplished
through the middle capacitor rather than the output one.
Therefore, disabling the HV9931 via its PWMD or VIN pins
can interrupt the output LED current in accordance with
the phase-controlled voltage waveform of a standard wall
dimmer.
IL1( PK )
RCS1
=
⋅ RREF1 ⋅ RS1
7.5V
where IL1(PK) is the maximum peak current in L1.
MOSFET Gate Driver
Typically, the gate driving capability of the HV9931 is limited
by the amount of power dissipation in its linear regulator.
Thus, care must be taken selecting a switching MOSFET
to be used in the circuit. An optimal trade-off must be found
between the gate charge and the on-resistance of the
MOSFET to minimize the input regulator current.
Oscillator
ConnectinganexternalresistorfromRTpintoGNDprograms
switching frequency:
25000
F kHz =
S [ ]
RT KΩ + 22
[ ]
Connecting the resistor from RT pin to GATE programs
constant off-time:
R KΩ + 22
T [ ]
TOFF µs =
[ ]
25
5
HV9931
Functional Circuit Diagram
D1
L1
L2
iL2
D4
C1
D2
VIN
-
_
VC1
iL1
+
Q1
D3
CIN
VO
~AC
~AC
RCS1
RS1
VS1
RS2
+
_
_
VS2
+
+
RT
RCS2
GATE
PWMD
RT
OSC
S Q
R
CS2
CS1
R
ref1
Rref2
REG
VIN
VDD
GND
HV9931
7. 5V
CDD
Switching Waveform
VDD
GATE
0
t
t
iL2
0
iL1
0
t
6
HV9931
Pin Description
Pin #
Pin Name Description
1
VIN
This pin is the input of a high voltage regulator.
These pins are used to sense the input and output currents of the converter. They are the
inverting inputs of the internal comparators.
2, 7
CS1, CS2
Ground return for all the internal circuitry. This pin must be electrically connected to the ground
of the power train.
3
4
GND
GATE
This pin is the output gate driver for an external N-channel power MOSFET.
When this pin is pulled to GND, switching of the HV9931 is disabled. When the PWMD pin
is released, or external TTL high level is applied to it, switching will resume. This feature is
provided for applications that require PWM dimming of the LED lamp.
5
PWMD
This is a power supply pin for all internal circuits. It must be bypassed with a low ESR capacitor
to GND.
6
8
VDD
RT
Oscillator control. A resistor connected between this pin and GND sets the PWM frequency. A
resistor connected between this pin and GATE sets the PWM off-time.
7
HV9931
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
D
θ1
8
E
E1
Gauge
Plane
L2
Note 1
(Index Area
D/2 x E1/2)
Seating
Plane
L
θ
1
L1
Top View
View B
A
View B
Note 1
h
h
A2
A
Seating
Plane
b
e
A1
A
Side View
View A-A
Note 1:
This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either
a mold, or an embedded metal or marked feature.
Symbol
A
A1
A2
b
D
E
E1
e
h
L
L1
L2
θ
0O
-
θ1
5O
-
MIN 1.35 0.10 1.25 0.31 4.80 5.80 3.80
0.25 0.40
Dimension
(mm)
1.27
BSC
1.04 0.25
REF BSC
NOM
-
-
-
-
4.90 6.00 3.90
-
-
MAX 1.75 0.25
-
0.51 5.00 6.20 4.00
0.50 1.27
8O
15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9931
A042307
8
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