HV9112NG-G [SUPERTEX]
High-Voltage Current-Mode PWM Controller; 高压电流模式PWM控制器
| 型号： | HV9112NG-G |
| 厂家： | 
Supertex, Inc |
| 描述： | High-Voltage Current-Mode PWM Controller |
| 文件： | 总8页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV9112
High-Voltage Current-Mode PWM Controller
General Description
Features
► 10V to 120V Input Voltage Range
► Current-mode control
► High efficiency
► Up to 1.0MHz internal oscillator
► Internal start-up circuit
► Low internal noise
The Supertex HV9112 is a BiCMOS/DMOS single-output,
pulse width modulator IC intended for use in high-speed,
high-efficiency switch mode power supplies. It provides all the
functions necessary to implement a single-switch current mode
PWM, in any topology, with a minimum of external parts.
Because the HV9112 utilizes Supertex’s proprietary BiCMOS/
DMOS technology, it requires less than one tenth of the operating
power of conventional bipolar PWM ICs, and can operate at
more than twice their switching frequency. The dynamic range
for regulation is also increased, to approximately 8 times that
of similar bipolar parts. It starts directly from any DC input
voltage between 10 and 120VDC, requiring no external power
resistor. The output stage is push-pull CMOS and thus requires
no clamping diodes for protection, even when significant lead
length exists between the output and the external MOSFET. The
clock frequency is set with a single external resistor.
Applications
► DC/DC converters
► Distributed power systems
► ISDN equipment
► PBX systems
► Modems
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching) and under voltage shutdown.
Ordering Information
For similar ICs intended to operate directly from up to 450VDC
input, please consult the data sheets for the HV9120 and
HV9123.
Package Option
Device
14-Lead Narrow Body SOIC (NG)
HV9112
HV9112NG-G
For detailed circuit and application information, please refer to
application notes AN-H13 and AN-H21 to AN-H24.
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
OSC IN
DISCHARGE
VREF
SHUTDOWN
RESET
COMP
FB
Absolute Maximum Ratings
OSC OUT
VDD
Parameter
Value
80V
-VIN
OUTPUT
SENSE
Input voltage, VIN
Logic voltage, VDD
Logic linear input,
FB and sense input voltage
Storage temperature
Power dissipation
+VIN
BIAS
15.5V
14-Lead Narrow Body SOIC (NG)
-0.3V to VDD +0.3V
Product Marking
-65°C to +150°C
750mW
Top Marking
Y = Last Digit of Year Sealed
HV9112NG
WW = Week Sealed
L = Lot Number
YWW LLLLLLLL
Bottom Marking
CCCCCCCCC AAA
Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
14-Lead Narrow Body SOIC (NG)
HV9112
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
Units
Conditions
Reference
VREF
Output voltage
-
#
-
3.88
4.00
30
4.12
45
V
RL = 10MΩ
---
ZOUT
ISHORT
ΔVREF
Output impedence
15
-
KΩ
μA
Short circuit current
Change in VREF with temperature
125
0.25
250
-
VREF = -VIN
#
-
mV/°C TA = -55°C to 125°C
Oscillator
fMAX
Oscillator frequency
Initial accuracy(1)
-
-
1.0
80
160
-
3.0
100
200
-
-
MHz
KHz
%
ROSC = 1.0MΩ
ROSC = 330KΩ
ROSC = 150KΩ
VSYNC = 0.1V
120
240
15
-
fOSC
-
-
-
Voltage stability
-
Temperature coefficient
#
-
170
ppm/°C TA = -55°C to 125°C
PWM
DMAX
Maximum duty cycle
Deadtime
-
#
-
49.0
49.4
49.6
%
ns
%
---
---
---
-
-
-
-
-
Minimum duty cycle
0
DMIN
Maximum pulse width before pulse
drops out
#
-
80
125
ns
---
Current Limit
Maximum input signal
-
1.0
-
1.2
80
1.4
V
VFB = 0V
VSENSE = 1.5V,
VCOMP ≤ 2.0V
tD
Delay to output
#
120
ns
Error Amplifier
VFB
IIN
Feedback voltage
-
-
3.92
-
4.00
25
4.08
500
V
nA
-
VFB shorted to comp
Input bias current
VFB = 4.0V
VOS
Input offset voltage
Open loop voltage gain
Unity gain bandwidth
Out impedance
-
nulled during trim
---
AVOL
GB
#
#
#
-
60
80
1.3
-
-
dB
MHz
Ω
---
1.0
---
ZOUT
ISOURCE
ISINK
see Fig. 1
-2.0
---
Output source current
Output sink current
Power supply rejection
-1.4
-
-
mA
mA
dB
VFB = 3.4V
VFB = 4.5V
---
-
0.12
0.15
PSRR
#
see Fig. 2
Notes:
#
Guaranteed by design. Not subject to production test.
(1) Stray capacitance on OSC In pin must be ≤5pF.
2
HV9112
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
Units
Conditions
Pre-regulator/Startup
+VIN
Input voltage
-
-
9.0
-
-
-
80
10
V
IIN < 10µA; VCC > 9.4V
VDD > 9.4V
+
Input leakage current
μA
IIN
Vdd pre-regulator turn-off threshold
voltage
VTH
-
-
8.0
7.0
8.7
8.1
9.4
8.9
V
V
IPREREG = 10µA
---
VLOCK
Undervoltage lockout
Supply
IDD
Supply current
-
-
-
-
-
-
0.75
0.55
20
1.0
mA
mA
μA
V
CL < 75pF
IQ
Quiescent supply current
Nominal Bias current
Operating range
-
-
Shutdown = -VIN
IBIAS
VDD
-
---
---
9.0
-
13.5
Shutdown Logic
tSD
tSW
tRW
tLW
VIL
VIH
IIH
Shutdown delay
#
#
#
#
-
-
50
50
25
-
50
100
-
ns
ns
ns
ns
V
CL = 500pF, VSENSE = -VIN
Shutdown pulse width
RESET pulse width
-
-
-
-
---
Latching pulse width
-
Shutdown and reset low
Input low voltage
-
2.0
-
---
Input high voltage
-
7.0
-
-
V
---
Input current, input high voltage
Input current, input low voltage
-
1.0
-25
5.0
-35
μA
μA
VIN = VDD
VIN = 0V
IIL
-
-
Output
VOH
Output high voltage
Output low voltage
-
-
VDD - 0.3
-
-
V
V
IOUT = 10mA,
IOUT = -10mA
VOL
-
-
-
-
-
-
-
-
0.2
25
20
30
30
75
75
Pull up
-
15
8.0
20
10
30
20
Ω
IOUT = 10mA
Pull down
Pull up
-
Ω
ROUT
Output resistance
-
Ω
IOUT = 10mA,
TA = -55°C to 125°C
Pull down
-
Ω
tR
tF
Rise time
Fall time
#
#
ns
ns
CL = 500pF
CL = 500pF
Notes:
# Guaranteed by design. Not subject to production test.
3
HV9112
Truth Table
Shutdown
Reset
Output
H
H
Normal operation
Normal operation, no change
Off, not latched
H
H → L
L
L
H
L
L
Off, latched
L → H
Off, latched, no change
Shutdown Timing Waveforms
tF ≤ 10ns
1.5V
V
DD
50%
50%
Sense
Shutdown
Output
tR ≤ 10ns
0
0
t
t
SD
d
V
V
DD
DD
90%
90%
Output
0
0
t
SW
V
DD
50%
50%
Shutdown
tR, tF ≤ 10ns
0
t
LW
V
DD
50%
50%
50%
Reset
0
t
RW
Functional Block Diagram
OSC
IN
OSC
OUT
FB
14
COMP
13
(18)
Discharge
9
(12)
8 (11)
7 (10)
(19)
Error
Amplifier
OSC
–
10 (14)
To VDD
VREF
+
2V
T
Q
Modulator
Comparator
–
+
+
–
4V
R
Q
S
4 (6)
Output
REF
GEN
5 (8)
Current Limit
Comparator
-VIN
To
Internal
Circuits
1 (20)
Current
Sources
1.2V
BIAS
3 (5)
Current Sense
6 (9)
2 (3)
VDD
VDD
+VIN
11 (16)
Undervoltage
Comparator
–
+
Shutdown
Reset
S
Q
R
8.1V
8.6V
–
+
12 (17)
Pre-regulator/Startup
4
HV9112
Typical Performance Curves
Output Switching Frequency
vs. Oscillator Resistance
Fig. 1
Fig. 4
Error Amplifier Output Impedance (Z0)
106
105
104
103
102
10
1
1M
100k
.1
100Hz
10k
10k
100 k
1M
1KHz
100KHz
10KHz
1MHz
10MHz
Frequency
PSRR — Error Amplifier and Reference
ROSC (Ω)
Fig. 2
Fig. 5
Error Amplifier
Open Loop Gain/Phase
0
-10
-20
-30
-40
-50
-60
-70
-80
80
70
60
50
40
30
20
10
0
180
120
60
0
-60
-120
-180
-10
10
100
1K
10K
100K
1M
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz)
RDISCHARGE vs. tOFF (9113 only)
100
104
Fig. 3
Fig. 6
ROSC = 100K
VDD = 12V
VDD = 10V
10
103
ROSC = 10K
ROSC = 1K
103 104
1
102
106
105
107
10-1
100
101
102
105
106
RDISCHARGE (Ω)
Bias Resistance (Ω)
5
HV9112
Test Circuits
Error Amp ZOUT
PSRR
0.1V swept 10Hz – 1MHz
+10V
1.0V swept 100Hz – 2.2MHz
(VDD
)
100K1%
60.4K
–
+
100K1%
10.0V
V1
–
+
(FB)
Tektronix
P6021
(1 turn
4.00V
Reference
Reference
V1
V2
secondary)
V2
40.2K
GND
(–VIN
0.1µF
)
0.1µF
NOTE: Set Feedback Voltage so that
COMP = VDIVIDE 1mV before connecting transformer
V
Detailed Description
Preregulator
Bias Circuit
The preregulator/startup circuit for the HV9112 consists of An external bias resistor, connected between the BIAS pin
a high-voltage n-channel depletion-mode DMOS transis- and VSS is required by the HV9112 to set currents in a se-
tor driven by an error amplifier to form a variable current ries of current mirrors used by the analog sections of the
path between the VIN terminal and the VDD terminal. The chip. The nominal external bias current requirement is 15 to
maximum current (about 20 mA) occurs when VDD = 0, with 20µA, which can be set by a 390KΩ to 510KΩ resistor if a
current reducing as VDD rises. This path shuts off altogether 10V VDD is used, or a 510kΩ to 680KΩ resistor if VDD will be
when V rises to somewhere between 7.8 and 9.4V, so that 12V. A precision resistor is not required; 5% is fine.
if VDD isDhDeld at 10 or 12V by an external source(generally the
supply the chip is controlling). No current other than leakage
is drawn through the high voltage transistor. This minimizes
dissipation.
Clock Oscillator
The clock oscillator of the HV9112 consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and,
in the 50% maximum duty cycle versions, a frequency divid-
ing flip-flop. A single external resistor between the OSC IN
and OSC OUT is required to set the oscillator frequency (see
graph). For the 50% maximum duty cycle versions the Dis-
charge pin is internally connected to GND. For the 99% duty
cycle version, the Discharge pin can either be connected to
VSS directly or connected to VSS through a resistor used
to set a deadtime. One major difference exists between the
Supertex HV9112 and competitive 9110’s. On the Supertex
part, the oscillator is shut off when a shutoff command is re-
ceived. This saves about 150µA of quiescent current, which
aids in the construction of power supplies that meet CCITT
specification I-430, and in other situations where an abso-
lute minimum of quiescent power dissipation is required.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
CSTORAGE ≥ 100 x (gate charge of FET at 10V ÷ 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable.
A common resistor divider string is used to monitor VDD for
both the under voltage lockout circuit and the shutoff circuit
of the high voltage FET. Setting the under voltage sense
point about 0.6V lower on the string than the FET shutoff
point guarantees that the under voltage lockout always re-
leases before the FET shuts off.
6
HV9112
Reference
Current Sense Comparators
The Reference of the HV9112 consists of a stable bandgap The HV9112 uses a true dual comparator system with in-
reference followed by a buffer amplifier which scales the dependent comparators for modulation and current limiting.
voltage up to approximately 4.0V. The scaling resistors of This allows the designer greater latitude in compensation
the reference buffer amplifier are trimmed during manufac- design, as there are no clamps (except ESD protection) on
ture so that the output of the error amplifier, when connected the compensation pin. Like the error amplifier, the compara-
in a gain of –1 configuration, is as close to 4.0V as possible. tors are of low-noise BiCMOS construction.
This nulls out any input offset of the error amplifier. As a con-
sequence, even though the observed reference voltage of a
Remote Shutdown
specific part may not be exactly 4.0V, the feedback voltage
required for proper regulation will be.
The shutdown and reset pins of the 9110 can be used to
perform either latching or non-latching shutdown of a con-
verter as required. These pins have internal current source
pull-ups so they can be driven from open drain logic. When
not used they should be left open, or connected to VDD.
A ≈ 50KΩ resistor is placed internally between the output of
the reference buffer amplifier and the circuitry it feeds (refer-
ence output pin and non-inverting input to the error ampli-
fier). This allows overriding the internal reference with a low
impedance voltage source ≤6.0V. Using an external refer-
ence reinstates the input offset voltage of the error amplifier,
and its effect of the exact value of feedback voltage required.
Because the reference of the HV9112 is a high impedance
node, and usually there will be significant electrical noise
near it, a bypass capacitor between the reference pin and
VSS is strongly recommended. The reference buffer ampli-
fier is intentionally compensated to be stable with a capaci-
tive load of 0.01 to 0.1µF.
Output Buffer
The output buffer of the HV9112 is of standard CMOS con-
struction (P-channel pull-up, N-channel pull-down). Thus the
body-drain diodes of the output stage can be used for spike
clipping if necessary, and external Schottky diode clamping
of the output is not required.
Error Amplifier
The error amplifier in the HV9112 is a true low-power dif-
ferential input operational amplifier intended for around the
amplifier compensation. It is of mixed CMOS-bipolar con-
struction: A PMOS input stage is used so the common mode
range includes ground and the input impedance is very high.
This is followed by bipolar gain stages which provide high
gain without the electrical noise of all-MOS amplifiers. The
amplifier is unity gain stable.
7
HV9112
14-Lead SOIC (Narrow Body) Package Outline (NG)
8.65x3.90mm body, 1.27mm pitch
θ1
D
14
E1
E
Note 1
(Index Area
D/2 x E1/2)
Gauge
Plane
L2
1
Seating
Plane
L
θ
L1
Top View
View B
A
View
B
h
Note 1
A A2
A1
h
Seating
Plane
e
b
A
Side View
View A-A
Note 1:
This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a
mold, or an embedded metal or marked feature.
Symbol
A
1.35
-
A1
0.10
-
A2
1.25
-
b
0.31
-
D
E
E1
e
h
0.25
-
L
0.40
-
L1
L2
θ
0O
-
θ1
5O
-
MIN
NOM
MAX
8.55
8.65
8.75
5.80
6.00
6.20
3.80
3.90
4.00
Dimension
(mm)
1.27
BSC
1.04
REF
0.25
BSC
1.75
0.25
1.65
0.51
0.50
1.27
8O
15O
JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005.
Drawinngs not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9112
A101007
8
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