HV9112NG-GM905 [MICROCHIP]
SWITCHING CONTROLLER;
| 型号： | HV9112NG-GM905 |
| 厂家： | 
MICROCHIP |
| 描述： | SWITCHING CONTROLLER 开关 |
| 文件： | 总8页 (文件大小：597K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
HV9112
High-Voltage, Current-Mode
PWM Controller
General Description
Features
The Supertex HV9112 is a BiCMOS/DMOS single-output, pulse width
modulator IC intended for use in high-speed, high-efficiency switch
mode power supplies. It provides all the functions necessary to
implement a single-switch current mode PWM, in any topology, with a
minimum of external parts.
► 9.0 to 80V input voltage range
► Current-mode control
► High efficiency
► Up to 1.0MHz internal oscillator
► Internal start-up circuit
► Low internal noise
Because the HV9112 utilizes Supertex’s proprietary BiCMOS/DMOS
technology, it requires less than one tenth of the operating power of
conventional bipolar PWM ICs, and can operate at more than twice
their switching frequency. The dynamic range for regulation is also
increased, to approximately 8 times that of similar bipolar parts. It starts
directly from any DC input voltage between 9.0 and 80VDC, requiring
no external power resistor. The output stage is push-pull CMOS and
thus requires no clamping diodes for protection, even when significant
lead length exists between the output and the external MOSFET. The
clock frequency is set with a single external resistor.
► 50% maximum duty cycle
Applications
► DC/DC converters
► Distributed power systems
► ISDN equipment
► PBX systems
► Modems
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching) and under voltage shutdown.
For similar ICs intended to operate directly from up to 450VDC input,
please consult the data sheets for the HV9120 and HV9123.
For detailed circuit and application information, please refer to
application notes AN-H13 and AN-H21 to AN-H24.
Functional Block Diagram
OSC
IN
8
OSC
OUT
7
FB
COMP
13
14
Error
Amplifier
OSC
–
10
VREF
+
2V
T
Q
Modulator
To VDD
–
+
+
–
Comparator
R
S
4V
Q
REF
GEN
4
5
OUTPUT
-VIN
Current Limit
Comparator
1
To
Current
Sources
BIAS
Internal
Circuits
3
6
2
1.2V
VDD
+VIN
SENSE
VDD
Undervoltage
Comparator
–
+
11
12
–
+
8.1V
8.6V
SHUTDOWN
RESET
S
R
Q
Pre-regulator/Startup
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
HV9112
Ordering Information
Pin Configuration
OSC IN
Part Number
Package Options
Packing
NC
VREF
HV9112NG-G
14-Lead SOIC (Narrow Body) 53/Tube
SHUTDOWN
RESET
COMP
FB
HV9112NG-G M905 14-Lead SOIC (Narrow Body) 2500/Reel
-G denotes a lead (Pb)-free / RoHS compliant package
OSC OUT
VDD
-VIN
OUTPUT
Absolute Maximum Ratings
Parameter
SENSE
+VIN
Value
80V
BIAS
14-Lead SOIC (Narrow Body)
Input voltage, VIN
Logic voltage, VDD
15.5V
Product Marking
Logic linear input,
FB and sense input voltage
-0.3V to VDD +0.3V
Top Marking
Y = Last Digit of Year Sealed
HV9112NG
Operating temperature range
Storage temperature range
Power dissipation
-55°C to +125°C
-65°C to +150°C
750mW
WW = Week Sealed
L = Lot Number
YWW LLLLLLLL
C = Country of Origin*
A = Assembler ID*
Bottom Marking
= “Green” Packaging
CCCCCCCCC AAA
*May be part of top marking
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package may or may not include the following marks: Si or
14-Lead SOIC (Narrow Body)
Typical Thermal Resistance
Package
θja
14-Lead SOIC (Narrow Body) 75°C/W
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, -VIN = 0V, RBIAS = 390kΩ, ROSC = 330kΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
Units
Conditions
Reference
VREF
Output voltage
-
#
-
3.88
4.00
30
4.12
45
V
RL = 10MΩ
---
ZOUT
ISHORT
ΔVREF
Output impedence
15
-
kΩ
μA
Short circuit current
Change in VREF with temperature
125
0.25
250
-
VREF = -VIN
#
-
mV/°C TA = -55°C to 125°C
Oscillator
fMAX
Oscillator frequency
Initial accuracy1
-
-
1.0
80
160
-
3.0
100
200
-
-
MHz
kHz
%
ROSC = 0Ω
120
240
15
-
ROSC = 330kΩ
ROSC = 150kΩ
9.5V< VDD <13.5V
fOSC
-
-
Voltage stability
-
-
Temperature coefficient
#
-
170
ppm/°C TA = -55°C to 125°C
Notes:
#
Guaranteed by design.
1. Stray capacitance on OSC IN pin must be ≤5.0pF.
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
2
HV9112
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, -VIN = 0V, RBIAS = 390kΩ, ROSC = 330kΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
Units
Conditions
PWM
DMAX
Maximum duty cycle
Minimum duty cycle
#
-
49.0
49.4
49.6
%
%
---
---
-
-
0
DMIN
Maximum pulse width before
pulse drops out
#
-
80
125
ns
---
Current Limit
Maximum input signal
Delay to output
Error Amplifier
-
1.0
-
1.2
80
1.4
V
VFB = 0V
tD
#
120
ns
VSENSE = 1.5V, VCOMP ≤ 2.0V
VFB
IIN
Feedback voltage
-
-
3.92
-
4.00
4.08
V
nA
-
VFB shorted to COMP
Input bias current
25
500
VFB = 4.0V
VOS
Input offset voltage
Open loop voltage gain
Unity gain bandwidth
Out impedance
-
nulled during trim
---
AVOL
GB
#
#
#
-
60
80
1.3
-
-
dB
MHz
Ω
---
1.0
---
ZOUT
ISOURCE
ISINK
see Fig. 1
-2.0
---
Output source current
Output sink current
Power supply rejection
-1.4
-
-
mA
mA
dB
VFB = 3.4V
VFB = 4.5V
---
-
0.12
0.15
PSRR
#
see Fig. 2
Pre-regulator/Startup
+VIN
+IIN
Input voltage
-
-
9.0
-
-
-
80
10
V
IIN < 10µA; VCC > 9.4V
VDD > 9.4V
Input leakage current
μA
VDD pre-regulator turn-off
threshold voltage
VTH
-
-
8.0
7.0
8.7
8.1
9.4
V
V
IPREREG = 10µA
---
VLOCK
Undervoltage lockout
8.9
Supply
IDD
Supply current
-
-
-
-
-
-
0.75
0.55
20
1.0
mA
mA
μA
V
CL < 75pF
IQ
Quiescent supply current
Nominal bias current
Operating range
-
-
SHUTDOWN = -VIN
IBIAS
-
---
---
VDD
9.0
-
13.5
Note:
#
Guaranteed by design.
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
3
HV9112
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, -VIN = 0V, RBIAS = 390kΩ, ROSC = 330kΩ, TA = 25°C.)
Sym
Parameter
#
Min
Typ
Max
Units Conditions
Shutdown Logic
tSD
tSW
tRW
tLW
VIL
VIH
IIH
SHUTDOWN delay
#
#
#
#
-
-
50
50
25
-
50
100
-
ns
ns
ns
ns
V
CL = 500pF, VSENSE = -VIN
SHUTDOWN pulse width
RESET pulse width
-
-
-
-
---
Latching pulse width
-
SHUTDOWN and RESET low
Input low voltage
-
2.0
-
---
Input high voltage
-
7.0
-
-
V
---
Input current, input high voltage
Input current, input low voltage
-
1.0
-25
5.0
-35
μA
μA
VIN = VDD
VIN = 0V
IIL
-
-
Output
VOH
Output high voltage
Output low voltage
Pull up
-
-
VDD -0.3
-
-
V
V
IOUT = 10mA
IOUT = -10mA
VOL
-
-
-
-
-
-
-
-
0.2
25
20
30
30
75
75
-
15
8.0
20
10
30
20
Ω
Ω
IOUT = ±10mA
Pull down
Output resistance
Pull up
-
ROUT
-
IOUT = ±10mA,
TA = -55°C to 125°C
Pull down
-
tR
tF
Rise time
Fall time
#
#
ns
ns
CL = 500pF
CL = 500pF
Note:
# Guaranteed by design.
Truth Table
SHUTDOWN
RESET
Output
Normal operation
H
H
H
H → L
Normal operation, no change
Off, not latched
L
L
H
L
L
Off, latched
L → H
Off, latched, no change
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
4
HV9112
Test Circuits
0.1V swept
10Hz - 1.0MHz
Error Amp ZOUT
PSRR
+10V
1.0V swept 100Hz - 2.2MHz
(VDD
)
100k 1%
60.4k
40.2k
100k 1%
10.0V
4.0V
–
+
–
+
(FB)
Tektronix
P6021
Reference
Reference
V2
V1
V1
(1 turn
V2
secondary)
GND
(-VIN)
0.1µF
0.1µF
NOTE:
Set Feedback Voltage so that VCOMP = VDIVIDE ꢀ1.0V
before connecting transfor0er
Detailed Description
Preregulator
Bias Circuit
The preregulator/startup circuit for the HV9112 consists of An external bias resistor, connected between the BIAS pin
a high-voltage n-channel depletion-mode DMOS transis- and VSS is required by the HV9112 to set currents in a se-
tor driven by an error amplifier to form a variable current ries of current mirrors used by the analog sections of the
path between the VIN terminal and the VDD terminal. The chip. The nominal external bias current requirement is 15
maximum current (about 20 mA) occurs when VDD = 0, with to 20µA, which can be set by a 390kΩ to 510kΩ resistor if a
current reducing as VDD rises. This path shuts off altogether 10V VDD is used, or a 510kΩ to 680kΩ resistor if VDD will be
when VDD rises to somewhere between 7.8 and 9.4V, so that 12V. A precision resistor is not required; ±5% is fine.
if VDD is held at 10 or 12V by an external source(generally the
supply the chip is controlling). No current other than leakage
is drawn through the high voltage transistor. This minimizes
dissipation.
Clock Oscillator
The clock oscillator of the HV9112 consists of a ring of
CMOS inverters, timing capacitors, and, a frequency divid-
ing flip-flop. A single external resistor between the OSC IN
and OSC OUT is required to set the oscillator frequency (see
graph). One major difference exists between the Supertex
HV9112 and competitive 9112s. On the Supertex part, the
oscillator is shut off when a shutoff command is received.
This saves about 150µA of quiescent current, which aids in
the construction of power supplies that meet CCITT specifi-
cation I-430, and in other situations where an absolute mini-
mum of quiescent power dissipation is required.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
CSTORAGE ≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable.
A common resistor divider string is used to monitor VDD for
both the under voltage lockout circuit and the shutoff circuit
of the high voltage FET. Setting the under voltage sense
point about 0.6V lower on the string than the FET shutoff
point guarantees that the under voltage lockout always re-
leases before the FET shuts off.
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
5
HV9112
amplifier compensation. It is of mixed CMOS-bipolar con-
struction: A PMOS input stage is used so the common mode
range includes ground and the input impedance is very high.
This is followed by bipolar gain stages which provide high
gain without the electrical noise of all-MOS amplifiers. The
amplifier is unity gain stable.
Reference
The Reference of the HV9112 consists of a stable bandgap
reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of
the reference buffer amplifier are trimmed during manufac-
ture so that the output of the error amplifier, when connected
in a gain of –1 configuration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplifier. As a con- Current Sense Comparators
sequence, even though the observed reference voltage of a The HV9112 uses a true dual comparator system with in-
specific part may not be exactly 4.0V, the feedback voltage dependent comparators for modulation and current limiting.
required for proper regulation will be.
This allows the designer greater latitude in compensation
design, as there are no clamps (except ESD protection) on
A ≈ 50kΩ resistor is placed internally between the output of the compensation pin. Like the error amplifier, the compara-
the reference buffer amplifier and the circuitry it feeds (refer- tors are of low-noise BiCMOS construction.
ence output pin and non-inverting input to the error ampli-
fier). This allows overriding the internal reference with a low
Remote Shutdown
impedance voltage source ≤6.0V. Using an external refer-
ence reinstates the input offset voltage of the error amplifier,
and its effect of the exact value of feedback voltage required.
Because the reference of the HV9112 is a high impedance
node, and usually there will be significant electrical noise
near it, a bypass capacitor between the reference pin and
VSS is strongly recommended. The reference buffer ampli-
fier is intentionally compensated to be stable with a capaci-
tive load of 0.01 to 0.1µF.
The SHUTDOWN and RESET pins of the 9112 can be used
to perform either latching or non-latching shutdown of a con-
verter as required. These pins have internal current source
pull-ups so they can be driven from open drain logic. When
not used they should be left open, or connected to VDD.
Output Buffer
The output buffer of the HV9112 is of standard CMOS con-
struction (P-channel pull-up, N-channel pull-down). Thus the
body-drain diodes of the output stage can be used for spike
clipping if necessary, and external Schottky diode clamping
of the output is not required.
Error Amplifier
The error amplifier in the HV9112 is a true low-power dif-
ferential input operational amplifier intended for around the
Shutdown Timing Waveforms
tF ≤ 10ns
1.5V
VDD
SHUTDOWN
50%
50%
SENSE
tR ≤ 10ns
0
0
tD
tSD
VDD
0
VDD
0
90%
90%
OUTPUT
OUTPUT
VDD
0
tSW
50%
50%
SHUTDOWN
RESET
tR, tF ≤ 10ns
tLW
VDD
0
50%
50%
50%
tRW
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
6
HV9112
Typical Performance Curves
Output Switching Frequency
vs. Oscillator Resistance
Fig. 1
Fig. 4
Error Amplifier Output Impedance (Z0)
106
105
104
103
102
10
1M
100k
10k
HV9113
HV9110, 9111, 9112
1.0
0.1
100
1k
10k
100k
1M
10M
10k
100k
1M
ROSC (Ω)
Frequency (Hz)
Error Amplifier
Fig. 2
Fig. 5
Open Loop Gain/Phase
PSRR - Error Amplifier and Reference
0
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
180
120
60
0
-60
-120
-180
-10
10
100
1k
10k
100k
1M
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Fig. 3
100
10
0
VDD = 12V
VDD = 10V
105
106
107
Bias Resistance (Ω)
Doc.# DSFP-HV9112
A031314
Supertex inc.
www.supertex.com
7
HV9112
14-Lead SOIC (Narrow Body) Package Outline (NG)
8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch
D
θ1
14
Note 1
(Index Area
D/2 x E1/2)
E1
E
Gauge
Plane
L2
L
Seating
Plane
θ
L1
e
b
1
Top View
View B
View B
A
h
h
A2
A
Seating
Plane
A1
Side View
View A-A
A
Note:
1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be:
a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol
A
A1
MIN 1.35* 0.10 1.25 0.31 8.55* 5.80* 3.80*
NOM 8.65 6.00 3.90
MAX 1.75 0.25 1.65* 0.51 8.75* 6.20* 4.00*
A2
b
D
E
E1
e
h
L
L1
L2
θ
0O
-
θ1
5O
-
0.25 0.40
Dimension
(mm)
1.27
BSC
1.04 0.25
REF BSC
-
-
-
-
-
-
0.50 1.27
8O 15O
JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-14SOICNG, Version F041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2014 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-HV9112
A031314
8
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