HV860K7-G [SUPERTEX]

Low Noise Dimmable EL Lamp Driver; 低噪音可调光致发光灯驱动器
HV860K7-G
型号: HV860K7-G
厂家: Supertex, Inc    Supertex, Inc
描述:

Low Noise Dimmable EL Lamp Driver
低噪音可调光致发光灯驱动器

驱动器 接口集成电路
文件: 总7页 (文件大小:315K)
中文:  中文翻译
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Supertex inc.  
HV860  
Initial Release  
Low Noise Dimmable EL Lamp Driver  
The HV860 has two internal oscillators, a switching  
MOSFET, and a high voltage EL lamp driver H-bridge. The  
frequency for the switching MOSFET is set by an external  
resistor connected between the RSW-OSC pin and the supply  
pin V . The EL lamp driver frequency is set by an external  
external inductor is connectedELb-OeStCween the LDXDand VDD  
pins or VIN for split supply applications. A 3.0nF capacitor  
is connected between CS and ground. The EL lamp is  
connected between VA and VB.  
Features  
► Adjustable output regulation for dimming  
► 220VPP output voltage for higher brightness  
► Single cell lithium ion compatible  
► 150nA shutdown current  
► Separately adjustable lamp and converter frequencies  
► 3x3 QFN-12 package  
► Split supply capability  
resistDoDr connected between R  
pin and V pin. An  
Applications  
► Mobile cellular phone keypads  
► PDAs  
► Handheld wireless communication products  
► Global Positioning Systems (GPS)  
The switching MOSFET charges the external inductor and  
discharges it into the capacitor at CS. The voltage at CS will  
start to increase. Once the voltage at CS reaches a nominal  
value of 110V, the switching MOSFET is turned OFF to  
conserve power. The outputs VA and V are configured as  
an H bridge and are switching in opposiBte states to achieve  
110V across the EL lamp.  
General Description  
EL lamp dimming can be accomplished by changing the  
input voltage to the VREG pin. The VREG pin allows an external  
voltage source to control the V amplitude. The VCS voltage  
The Supertex HV860 is a high voltage driver designed for  
driving Electroluminescent, (EL), lamps of up to 5 square  
inches. The input supply voltage range is from 2.5V to 4.5V.  
The device uses a single inductor and a minimum number of  
passive components. Using the internal reference voltage,  
the regulated output voltage is at a nominal voltage of 110V.  
The EL lamp will therefore see 110V. An enable pin, (EN),  
is available to turn the device on and off via a logic signal.  
is approximately 87 times the CvSoltage seen on VREG  
.
Typical Application Circuit  
VIN  
CIN  
LX  
D
RREG  
2
3
5
CS  
VREG  
VDD  
VREF LX  
CS  
10  
12  
7
VDD  
RSW  
CDD  
RSW-OSC  
REL-OSC  
EN  
9
8
VA  
VB  
1
EL  
Lamp  
REL  
1.5V = On  
0V = Off  
11  
GND  
4
HV860K7  
NR040306  
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com  
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1
HV860  
Thermal Resistance  
Ordering Information  
Package Option  
QFN-12  
Package  
θja  
Device  
QFN-12  
60 °C/W  
HV860  
HV860K7-G  
-G indicates package is RoHS compliant (‘Green’)  
Pin Configuration  
V
EN  
R
DD  
SW-OSC  
11 10  
12  
9
8
7
V
1
2
3
R
Absolute Maximum Ratings  
Parameter  
VDD, Supply Voltage  
Operating Temperature  
Storage Temperature  
Power Dissipation QFN-12  
VCS, Output Voltage  
A
B
S
EL-OSC  
Value  
-0.5V to 6.0V  
-40°C to +85°C  
-65°C to +150°C  
1.6W  
V
HV860K7  
V
C
REG  
V
REF  
4
5
6
-0.5V to +120V  
GND  
NC  
L
X
VREG External Input Voltage  
1.33V  
QFN-12 Top View  
Absolute Maximum Ratings are those values beyond which damage to the device may  
occur. Functional operation under these conditions is not implied. Continuous operation  
of the device at the absolute rating level may affect device reliability. All voltages are  
referenced to device ground.  
Note: Pads are at the bottom of the package. Center heat slug is at ground  
potential  
Electrical Characteristics  
DC Characteristics (Over recommended operating conditions unless otherwise specified TA=25°C)  
Symbol  
RDS(ON)  
VCS  
Parameter  
Min  
Typ  
Max Units Conditions  
On-resistance of switching  
transistor  
-
-
6.0  
I = 100mA  
-
-
95  
75  
55  
-
Maximum output regulation voltage  
120  
-
V
VDD = 2.5V to 4.5V  
-
VDD = 2.5V to 4.5V, VREG = 1.092V  
VDD = 2.5V to 4.5V, VREG = 0.862V  
VDD = 2.5V to 4.5V, VREG = 0.632V  
VDD = 2.5V to 4.5V  
VCS  
Output regulation voltage  
-
-
V
-
0
-
VREG  
VREFH  
IDDQ  
External input voltage range  
VREF output high voltage  
1.26  
1.33  
150  
V
V
1.18  
-
1.26  
-
VDD = 2.5V to 4.5V  
Quiescent VDD supply current  
nA  
EN = low  
VDD = 2.5V to 4.5V, REL = 2.0MΩ,  
RSW = 1.0MΩ  
-
-
IDD  
IIN  
Input current going into the VDD pin  
200  
16  
µA  
Input current including inductor  
current  
-
-
mA  
Hz  
see Figure 2  
fEL  
fSW  
D
EL lamp frequency  
160  
76  
-
200  
240  
104  
88  
REL = 2.0MΩ  
Switching transistor frequency  
Switching transistor duty cycle  
Enable input logic high voltage  
Enable input logic low voltage  
Enable input logic high current  
90  
-
kHz RSW = 1.0MΩ  
%
V
---  
-
VIH  
VIL  
IIH  
1.5  
0
VDD  
0.2  
1.0  
VDD = 2.5V to 4.5V  
VDD = 2.5V to 4.5V  
VIH = VDD = 2.5V to 4.5V  
-
V
-
-
µA  
NR040306  
2
HV860  
Electrical Characteristics (cont.)  
Symbol  
Parameter  
Min  
Typ  
Max Units Conditions  
-
-
-
-
IIL  
Enable input logic low current  
Enable input capacitance  
-1.0  
15  
µA  
pF  
VIL = 0V, VDD = 2.5V to 4.5V  
---  
CIN  
Recommended Operating Conditions  
Symbol  
Parameter  
Min  
2.5  
40  
Typ  
Max Units Conditions  
-
-
-
-
-
VDD  
Supply voltage  
4.5  
200  
500  
20  
V
kHz  
Hz  
nF  
---  
---  
---  
---  
---  
fSW  
Switching frequency  
EL output frequency  
EL lamp capacitance load  
Operating Temperature  
fEL  
200  
0
CLOAD  
TA  
-40  
+85  
°C  
Pin Configuration and External Component Description  
Pin #  
Name  
Description  
External resistor from R  
to VDD sets the EL frequency. The EL frequency is inversely proportional  
1
REL-OSC to the external REL resistEoLr-OvSCalue. Reducing the resistor value by a factor of two will result in increasing  
the EL frequency by two.  
Input voltage to set VCS regulation voltage. This pin allows an external voltage source to control the VCS  
amplitude. EL lamp dimming can be accomplished by varying the input voltage to VREG. The VCS voltage  
is approximately 87 times the voltage seen on VREG  
.
2
VREG  
External resistor RREG, connected between VREG and VREF pins controlls the VCS charging rate. The  
charging rate is inversely proportional to the RREG resistor value.  
3
4
VREF  
Switched internal reference voltage.  
GND  
Device ground.  
Drain of internal switching MOSFET. Connection for an external inductor.  
The inductor LX is used to boost the low input voltage by inductive flyback. When the internal switch  
is on, the inductor is being charged. When the internal switch is off, the charge stored in the inductor  
will be transferred to the high voltage capacitor CS. The energy stored in the capacitor is connected  
to the internal H-bridge, and therefore to the EL lamp. In general, smaller value inductors, which can  
handle more current, are more suitable to drive larger size lamps. As the inductor value decreases, the  
switching frequency of the inductor (controlled by RSW) should be increased to avoid saturation.  
5
LX  
A 220µH Cooper (SD3814-221) inductor with 5.5Ω series DC resistance is typically recommended. For  
inductors with the same inductance value, but with lower series DC resistance, lower RSW resistor value  
is needed to prevent high current draw and inductor saturation.  
6
7
NC  
CS  
No internal connections to the device.  
High voltage regulated output. Connection for an external high voltage capacitor to ground  
VB side of the EL lamp driver H-bridge. Connection for one of the EL lamp terminals.  
VA side of the EL lamp driver H-bridge. Connection for one of the EL lamp terminals.  
Low voltage input supply pin.  
8
VB  
9
VA  
10  
11  
VDD  
EN  
Logic input pin. Logic high will enable the device.  
External resistor from R  
will result in increasing the switch converSteWr frequency by two.  
to V sets the switch converter frequency. The switch converter frequency  
12  
RSW-OSC is inversely proportionalStWo-OtShCe extDeDrnal R resistor value. Reducing the resistor value by a factor of two  
NR040306  
3
HV860  
Figure 1: Block Diagram  
CS  
VDD  
Device Enable  
LX  
EN  
PWM Switch  
Oscillator  
RSW-OSC  
0 to 88%  
VA  
+
VSENSE  
C
-
Output  
Drivers  
VREG  
1.26V  
VREF  
60pF  
VCS  
VREF  
2x EL  
Freq.  
VB  
REL-OSC  
EL  
Frequency  
GND  
Figure 2: Typical Application / Test Circuit  
+
4.7μF  
VIN  
-
220μH  
(Cooper Inductor SD3814-221)  
3.3MΩ  
3
5
2
BAS21  
7
3.3nF  
200V  
VREG  
VDD  
VREF LX  
CS  
10  
12  
VDD  
1.0MΩ  
2.0MΩ  
0.1μF  
RSW-OSC  
REL-OSC  
EN  
9
8
VA  
VB  
1
3.0in2  
EL Lamp  
1.5V = ON  
0V = Off  
11  
GND  
4
HV860K7  
Typical Performance  
VDD  
Lamp Size  
VIN  
IIN  
VCS  
fEL  
Brightness  
3.0V  
3.5V  
4.2V  
16.17mA  
14.18mA  
12.13mA  
18.2cd/m2  
19.3cd/m2  
19.9cd/m2  
3.0V  
3.0in2  
100V (peak)  
196Hz  
NR040306  
4
HV860  
Figure 3: Typical Waveform on VA, VB, and Differential Waveform VA - VB  
Split Supply Configuration  
The HV860 can also be used for handheld devices operating necessary to run the internal logic is 200µA max. Therefore,  
from a battery where a regulated voltage is available. This the regulated voltage could easily provide the current without  
is shown in the Figure 4. The regulated voltage can be used being loaded down.  
to run the internal logic of the HV860. The amount of current  
Enable/Disable Configuration  
The HV860 can be easily enabled and disabled via a logic microprocessor signal is high the device is enabled, and  
control signal on the EN pin as shown in the Figure 4. The when the signal is low, it is disabled.  
control signal can be from a microprocessor. When the  
Figure 4: Split Supply and Enable/Disable Configuration  
+
VIN  
CIN  
-
LX  
D
RREG  
2
VREG  
VDD  
3
5
CS  
VREF LX  
CS  
7
10  
12  
Regulated Voltage = VDD  
RSW  
CDD  
RSW-OSC  
REL-OSC  
EN  
9
8
VA  
VB  
1
EL  
Lamp  
REL  
On = 1.5V  
Off = 0V  
11  
GND  
4
HV860K7  
NR040306  
5
HV860  
Audible Noise Reduction  
The EL lamp, when lit, emits an audible noise. This is due The HV860 employs a proprietary circuit to help minimize  
to EL lamp construction. The audible noise generated by the the EL lamp’s audible noise by using a single resistor, RREG  
EL lamp can be a major problem for applications where the as shown in Figure 5.  
EL lamp is held close to the ear, such as cellular phones.  
,
Figure 5: Typical Application Circuit for Audible Noise Reduction  
VIN  
CIN  
LX  
D
RREG  
2
3
5
CS  
VREG  
VDD  
VREF LX  
CS  
10  
12  
7
VDD  
RSW  
CDD  
RSW-OSC  
REL-OSC  
EN  
9
8
VA  
VB  
1
EL  
Lamp  
REL  
1.5V = On  
0V = Off  
11  
GND  
4
HV860K7  
How to Minimize EL Lamp Audible Noise  
The audible noise from the EL lamp can be minimized with to ground. EL lamp noise can be minimized without much  
the proper selection of RREG. R  
is connected between loss in brightness by setting the RC time constant to be  
the VREF and VREG pins. VREG hasRaEnG internal 60pF capacitor approximately 1/12TH of the EL frequency’s period.  
EL Lamp Dimming using PWM  
This section describes the method of dimming the EL lamp. resistor. An n-channel open drain PWM signal is used to pull  
Reducing the voltage amplitude at the VREG pin will reduce the 10kΩ resistor to ground. The effective voltage on the  
the voltage on the VCS pin, which will effectively reduce the  
V
pin will be proportional to the duty cycle of the PWM  
peak the peak voltage the EL lamp sees. Figure 5 shows a siRgEnGal. The PWM operating frequency can be anywhere  
circuit to dim the lamp by changing the duty cycle of a PWM between 20kHz to 100kHz.  
signal. A 10kΩ resistor is connected in series with a 3.3MΩ  
Figure 6: PWM Dimming Circuit  
+
VIN  
4.7μF  
-
220μH  
Open Drain  
n-channel  
PWM Signal  
(Cooper Inductor SD3814-221)  
10kΩ  
3
VREF  
3.3MΩ  
5
LX  
CS  
2
BAS21  
7
3.3nF  
200V  
VREG  
VDD  
10  
12  
+
-
1.0MΩ  
2.0MΩ  
VDD  
0.1μF  
RSW-OSC  
REL-OSC  
EN  
9
8
VA  
VB  
1
EL Lamp  
On = 1.5V  
Off = 0V  
11  
GND  
4
HV860K7  
NR040306  
6
HV860  
12-Lead QFN Package Outline (K7)  
0.73  
0.85  
1.25  
1.65  
All dimensions are in millimeters  
Legend: min  
max  
0.73  
0.85  
Pin #1  
1.25  
1.65  
3.00  
1.55  
2.40  
0.18  
0.30  
0.30  
0.50  
0.5  
3.00  
Top View  
θ ~ 14O  
0.70  
0.80  
0.20  
Side View  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline  
information go to http://www.supertex.com/packaging.html.)  
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate  
"product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices  
determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest  
product specifications, refer to the Supertex website: http//www.supertex.com.  
©2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.  
Supertex inc.  
1235 Bordeaux Drive, Sunnyvale, CA 94089  
TEL: (408) 222-8888 / FAX: (408) 222-4895  
Doc.# DSFP - HV860  
www.supertex.com  
NR040306  
7

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