VN750B5TR-E [STMICROELECTRONICS]
HIGH SIDE DRIVER; 高端驱动器
| 型号： | VN750B5TR-E |
| 厂家： | 
ST |
| 描述： | HIGH SIDE DRIVER |
| 文件： | 总31页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VN750-E / VN750S-E
VN750PT-E / VN750B5-E
HIGH SIDE DRIVER
Table 1. General Features
Figure 1. Package
Type
R
I
V
CC
DS(on)
OUT
VN750-E
VN750B5-E
VN750S-E
VN750PT
60 mΩ
6 A
36 V
SO-8
PENTAWATT
PPAK
■ CMOS COMPATIBLE INPUT
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
2
P PAK
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
Active current limitation combined with thermal
shutdown and automatic restart protect the device
against overload.
■ REVERSE BATTERY PROTECTION (*)
■ IN COMPLIANCE WITH THE 2002/95/EC
The device detects open load condition both is on
EUROPEAN DIRECTIVE
and off state. Output shorted to V is detected in
CC
the off state. Device automatically turns off in case
of ground pin disconnection.
DESCRIPTION
The
VN750-E,
VN750S-E,
VN750PT-E,
VN750B5-E are a monolithic device designed in
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground.
Active V
pin voltage clamp protects the device
CC
against low energy spikes (see ISO7637 transient
compatibility table).
Table 2. Order Codes
Package
Tube
Tape and Reel
-
PENTAWATT
SO-8
VN750-E
VN750S-E
VN750B5-E
VN750PT-E
VN750STR-E
VN750B5TR-E
VN750PTTR-E
2
P PAK
PPAK
Note: (*) See application schematic at page 9.
Rev. 1
1/31
October 2004
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 2. Block Diagram
VCC
OVERVOLTAGE
DETECTION
VCC
CLAMP
UNDERVOLTAGE
DETECTION
GND
Power CLAMP
DRIVER
INPUT
OUTPUT
LOGIC
CURRENT LIMITER
ON STATE OPENLOAD
DETECTION
STATUS
OVERTEMPERATURE
DETECTION
OFF STATE OPENLOAD
AND OUTPUT SHORTED TO VCC
DETECTION
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
2
SO-8 PENTAWATT P PAK PPAK
V
DC Supply Voltage
41
- 0.3
V
V
CC
- V
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
CC
gnd
- I
- 200
mA
A
I
Internally Limited
- 6
OUT
- I
OUT
Reverse DC Output Current
DC Input Current
A
I
IN
+/- 10
mA
mA
I
DC Status Current
+/- 10
STAT
Electrostatic Discharge
(Human Body Model: R=1.5KΩ; C=100pF)
- INPUT
4000
4000
5000
5000
V
V
V
V
V
ESD
- STATUS
- OUTPUT
- V
CC
Maximum Switching Energy
(L=1.8mH; R =0Ω; V =13.5V; T
E
E
100
mJ
mJ
MAX
=150ºC; I =9A)
L
bat
jstart
L
Maximum Switching Energy
(L=2.46mH; R =0Ω; V =13.5V; T
138
60
138
60
MAX
=150ºC; I =9A)
L
bat
jstart
L
P
Power Dissipation T =25°C
4.2
60
W
°C
°C
°C
tot
C
T
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
Internally Limited
- 40 to 150
j
T
c
T
- 55 to 150
stg
2/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
5
4
3
2
1
OUTPUT
STATUS
5
4
VCC
N.C.
OUTPUT
OUTPUT
VCC
STATUS
INPUT
GND
V
CC
INPUT
GND
8
1
2
SO-8
PENTAWATT
PPAK / P PAK
Connection / Pin Status N.C. Output
Input
Floating
X
X
X
X
X
To Ground
Through 10KΩ resistor
Figure 4. Current and Voltage Conventions
IS
VF
IIN
VCC
GND
INPUT
ISTAT
IOUT
VCC
STATUS
OUTPUT
VIN
VOUT
VSTAT
IGND
Table 4. Thermal Data
Value
PENTAWATT P PAK
Symbol
Parameter
Unit
2
S0-8
-
PPAK
R
Thermal Resistance Junction-case
Thermal Resistance Junction-lead
Max
Max
2.1
-
2.1
-
2.1
°C/W
°C/W
thj-case
R
30
-
thj-lead
1
3
3
93 ( )
62.1
62.1
52.1 ( )
77.1 ( ) °C/W
R
Thermal Resistance Junction-ambient Max
thj-amb
2
4
4
82 ( )
37 ( )
44 ( )
°C/W
1
2
( ) When mounted on a standard single-sided FR-4 board with 0.5cm of Cu (at least 35µm thick) connected to all V
pins. Horizontal
CC
mounting and no artificial air flow.
2
2
( ) When mounted on a standard single-sided FR-4 board with 2cm of Cu (at least 35µm thick) connected to all V pins. Horizontal mount-
CC
ing and no artificial air flow.
3
2
( ) When mounted on a standard single-sided FR-4 board with 0.5cm of Cu (at least 35µm thick). Horizontal mounting and no artificial air
flow.
4
2
( ) When mounted on a standard single-sided FR-4 board with 6cm of Cu (at least 35µm thick). Horizontal mounting and no artificial air flow.
3/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
ELECTRICAL CHARACTERISTICS (8V<V <36V; -40°C<T <150°C unless otherwise specified)
CC
j
Table 5. Power
Symbol
Parameter
Test Conditions
Min.
5.5
3
Typ.
13
4
Max.
36
Unit
V
V
CC
Operating Supply Voltage
Undervoltage Shut-down
V
5.5
V
USD
Undervoltage Shut-down
Hysteresis
V
0.5
V
V
USDhyst
V
OV
R
ON
Overvoltage Shut-down
36
I
I
=2A; T =25°C; V >8V
60
mΩ
mΩ
OUT
j
CC
On State Resistance
(#)
10
=2A; V >8V
120
OUT
CC
25
µA
Off State; V =13V; V =V
=0V
CC
IN
OUT
Off State; V =13V; V =V
T =25°C
j
=0V;
OUT
CC
IN
I
Supply Current
S
10
2
20
µA
On State; V =13V; V =5V; I
=0A
CC
IN
OUT
3.5
mA
I
Off State Output Current
Off State Output Current
Off State Output Current
Off State Output Current
V =V =0V
OUT
0
(#)
50
0
µA
µA
µA
µA
L(off1)
L(off2)
L(off3)
L(off4)
IN
I
I
I
V =0V; V
=3.5V
-75
IN
OUT
V =V
=0V; V =13V; T =125°C
5
IN
OUT
CC
j
V =V
=0V; V =13V; T =25°C
3
IN
OUT
CC
j
Table 6. Switching (V =13V)
CC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
R =6.5Ω from V rising edge to
L
IN
t
t
Turn-on Delay Time
40
µs
d(on)
d(off)
V
OUT
=1.3V
R =6.5Ω from V falling edge to
L
IN
Turn-off Delay Time
Turn-on Voltage Slope
Turn-off Voltage Slope
30
(#)
(#)
µs
V
OUT
=11.7V
dV
dt
/
/
R =6.5Ω from V
=1.3V to
OUT
L
OUT
OUT
V/µs
V/µs
V
OUT
=10.4V
(on)
dV
dt
R =6.5Ω from V
L
=11.7V to
OUT
V
OUT
=1.3V
(off)
Table 7. Input Pin
Symbol
Parameter
Test Conditions
Min.
Typ.
(#)
Max.
Unit
V
V
Input Low Level
1.25
IL
I
Low Level Input Current
Input High Level
V =1.25V
1
(#)
µA
V
IL
IN
V
3.25
(#)
IH
IH
I
High Level Input Current
Input Hysteresis Voltage
V =3.25V
IN
(#)
10
8
µA
V
V
hyst
0.5
6
(#)
I =1mA
IN
6.8
V
V
V
ICL
Input Clamp Voltage
I =-1mA
IN
-0.7
Note: (#) See relative diagram
4/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. V - Output Diode
CC
Symbol
Parameter
Test Conditions
Min.
Min
6
Typ.
Max.
Unit
V
Forward on Voltage
-I
=1.3A; T =150°C
0.6
V
F
OUT
j
Table 9. Status Pin
Symbol
Parameter
Test Conditions
Typ
(#)
Max
0.5
10
Unit
V
V
STAT
Status Low Output Voltage I
=1.6mA
STAT
I
Status Leakage Current
Normal Operation; V
=5V
=5V
(#)
µA
LSTAT
STAT
Status Pin Input
Capacitance
C
Normal Operation; V
100
8
pF
STAT
STAT
I
=1mA
6.8
V
V
STAT
V
Status Clamp Voltage
I
SCL
=-1mA
-0.7
STAT
Table 10. Protections (see note 1)
Symbol
Parameter
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
Test Conditions
Min
150
135
7
Typ
Max
Unit
°C
T
175
200
TSD
T
°C
R
T
15
9
°C
hyst
Status delay in overload
condition
t
T >T
20
µs
SDL
j
jsh
9V<V <36V
6
15
15
A
A
CC
I
Current limitation
lim
5V<V <36V
CC
Turn-off Output Clamp
Voltage
V
demag
I
=2A; V =0V; L=6mH
V
-41
V
CC
-48
V -55
CC
V
OUT
IN
CC
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles.
Table 11. Openload Detection
Symbol
Parameter
Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Test Conditions
Min
Typ
Max
Unit
I
OL
V =5V
50
(#)
200
mA
IN
t
I
=0A
200
µs
DOL(on)
OUT
Openload OFF State
Voltage Detection
Threshold
V
OL
V =0V
IN
1.5
(#)
3.5
V
Openload Detection Delay
at Turn Off
t
1000
µs
DOL(off)
Note: (#) See relative diagram
5/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
OVERTEMP STATUS TIMING
T > T
I
< I
OUT OL
V
OUT
> V
OL
j
jsh
V
IN
V
IN
V
STAT
V
STAT
t
t
t
DOL(off)
t
DOL(on)
SDL
SDL
Table 12. Truth Table
CONDITIONS
INPUT
OUTPUT
STATUS
L
H
L
H
H
H
Normal Operation
Current Limitation
L
H
H
L
X
X
H
) H
) L
(T < T
(T > T
j
j
TSD
TSD
L
H
L
L
H
L
Overtemperature
Undervoltage
Overvoltage
L
H
L
L
X
X
L
H
L
L
H
H
L
H
H
H
L
H
Output Voltage > V
OL
L
H
L
H
H
L
Output Current < I
OL
Figure 6. Switching time Waveforms
VOUTn
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VINn
td(on)
td(off)
t
6/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Table 13. Electrical Transient Requirements On V Pin
CC
TEST LEVELS
ISO T/R 7637/1
Test Pulse
Delays and
Impedance
I
II
III
IV
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
ISO T/R 7637/1
TEST LEVELS RESULTS
I
II
C
C
C
C
C
E
III
C
C
C
C
C
E
IV
C
C
C
C
C
E
Test Pulse
1
2
C
C
C
C
C
C
3a
3b
4
5
CLASS
CONTENTS
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
7/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 7. Waveforms
NORMAL OPERATION
INPUT
LOAD VOLTAGE
STATUS
UNDERVOLTAGE
V
V
CC
USDhyst
V
USD
INPUT
LOAD VOLTAGE
STATUS
undefined
OVERVOLTAGE
V
<V
OV
V
>V
OV
CC
CC
V
CC
INPUT
LOAD VOLTAGE
STATUS
OPEN LOAD with external pull-up
INPUT
V
OUT
>V
OL
LOAD VOLTAGE
STATUS
V
OL
OPEN LOAD without external pull-up
INPUT
LOAD VOLTAGE
STATUS
OVERTEMPERATURE
T
T
TSD
R
T
j
INPUT
LOAD CURRENT
STATUS
8/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 8. Application Schematic
+5V
+5V
V
CC
R
prot
STATUS
INPUT
D
ld
R
prot
µC
OUTPUT
GND
R
GND
V
GND
D
GND
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (R
can be used with any type of load.
only). This
GND
The following is an indication on how to dimension the
R
resistor.
GND
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
1) R
2) R
≤ 600mV / (I
).
S(on)max
)
GND
GND
GND
≥ (−V ) / (-I
CC
LOAD DUMP PROTECTION
where -I
is the DC reverse ground pin current and can
GND
be found in the absolute maximum rating section of the
D
is necessary (Voltage Transient Suppressor) if the
ld
device’s datasheet.
load dump peak voltage exceeds V
max DC rating.
CC
The same applies if the device will be subject to
Power Dissipation in R
(when V <0: during reverse
CC
GND
transients on the V
line that are greater than the ones
CC
battery situations) is:
shown in the ISO T/R 7637/1 table.
2
P = (-V ) /R
D
CC
GND
µC I/Os PROTECTION:
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
If a ground protection network is used and negative
calculated with formula (1) where I
becomes the
transients are present on the V line, the control pins will
S(on)max
CC
sum of the maximum on-state currents of the different
be pulled negative. ST suggests to insert a resistor (R
in line to prevent the µC I/Os pins to latch-up.
)
prot
devices.
Please note that if the microprocessor ground is not
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
common with the device ground then the R
will
GND
produce a shift (I
* R
) in the input thresholds
GND
S(on)max
and the status output values. This shift will vary
depending on many devices are ON in the case of several
-V
/I
≤ R
≤ (V -V -V
OHµC IH GND
) / I
CCpeak latchup
prot
IHmax
high side drivers sharing the same R
.
GND
Calculation example:
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤ R
≤ 65kΩ.
prot
Recommended R
value is 10kΩ.
prot
Solution 2: A diode (D
) in the ground line.
GND
A resistor (R
GND
=1kΩ) should be inserted in parallel to
GND
D
if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
9/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
V
OUT
=(V /(R +R ))R <V
PU L PU L Olmin.
OPEN LOAD DETECTION IN OFF STATE
2) no misdetection when load is disconnected: in this
case the V has to be higher than V ; this
OUT
OLmax
Off state open load detection requires an external pull-up
results in the following condition R <(V
V
)/
PU
PU– OLmax
resistor (R ) connected between OUTPUT pin and a
PU
I
.
L(off2)
positive supply voltage (V ) like the +5V line used to
PU
Because I
may significantly increase if V
is
s(OFF)
out
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
pulled high (up to several mA), the pull-up resistor R
PU
should be connected to a supply that is switched OFF
when the module is in standby.
1) no false open load indication when load is connected:
The values of V
, V
OLmin
and I
are available in
L(off2)
OLmax
in this case we have to avoid V
to be higher than
OUT
the Electrical Characteristics section.
V ; this results in the following condition
Olmin
Figure 9. Open Load detection in off state
V batt.
VPU
VCC
RPU
DRIVER
IL(off2)
INPUT
+
LOGIC
OUT
+
-
R
STATUS
VOL
RL
GROUND
10/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 11. High Level Input Current
Figure 10. Off State Output Current
Iih (uA)
7
IL(off1) (uA)
3
2.5
6
Off state
Vin=3.25V
2
Vcc=36V
5
Vin=Vout=0V
1.5
4
3
2
1
0
1
0.5
0
-0.5
-1
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Figure 12. Input Clamp Voltage
Figure 14. Status Leakage Current
Ilstat (uA)
0.05
Vicl (V)
8
7.8
Iin=1mA
0.04
7.6
7.4
7.2
7
Vstat=5V
0.03
0.02
0.01
0
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 13. Status Low Output Voltage
Figure 15. Status Clamp Voltage
Vstat (V)
0.6
Vscl (V)
8
7.8
Istat=1mA
0.5
7.6
Istat=1.6mA
7.4
7.2
7
0.4
0.3
0.2
0.1
0
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
11/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 16. On State Resistance Vs T
Figure 17. On State Resistance Vs V
case
CC
Ron (mOhm)
120
Ron (mOhm)
140
110
120
Iout=2A
Iout=2A
100
Tc= 150°C
Vcc=8V; 13V; 36V
100
90
80
80
60
40
20
0
Tc= 125°C
70
60
50
Tc= 25°C
40
Tc= - 40°C
30
20
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100 125
150
175
Vcc (V)
Tc (ºC)
Figure 18. Openload On State Detection
Threshold
Figure 20. Openload Off State Voltage
Detection Threshold
Iol (mA)
220
Vol (V)
5
200
4.5
Vcc=13V
Vin=5V
180
Vin=0V
4
160
140
120
100
80
3.5
3
2.5
2
60
40
1.5
1
20
0
-50
-25
0
25
50
75
100 125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Figure 19. Input High Level
Figure 21. Input Low Level
Vih (V)
3.6
Vil (V)
2.8
2.6
2.4
2.2
2
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
12/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 25. Turn-off Voltage Slope
Figure 22. Turn-on Voltage Slope
dVout/dt/(on) (V/ms)
1000
dVout/dt(off) (V/ms)
500
900
450
Vcc=13V
Vcc=13V
Rl=6.5Ohm
800
400
Rl=6.5Ohm
700
350
600
500
400
300
200
100
0
300
250
200
150
100
50
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100 125
150
175
Tc (ºC)
Tc (ºC)
Figure 23. Overvoltage Shutdown
Figure 26. I
Vs T
LIM case
Vov (V)
50
Ilim (A)
20
18
16
14
12
10
8
48
46
44
42
40
38
36
34
32
30
Vcc=13V
6
4
2
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (ºC)
Figure 24. Input Hysteresis Voltage
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
13/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 27. SO-8 Maximum turn off current versus load inductance
LMAX (A)
I
100
10
1
A
B
C
0.1
1
10
100
L(mH)
A = Single Pulse at T
=150ºC
Jstart
Values are generated with R =0Ω
L
B= Repetitive pulse at T
=100ºC
Jstart
In case of repetitive pulses, T
(at beginning of
jstart
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
C= Repetitive Pulse at T
=125ºC
Jstart
Conditions:
V
=13.5V
CC
V , I
IN
L
Demagnetization
Demagnetization
Demagnetization
t
14/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
2
Figure 28. PPAK, P PAK Maximum turn off current versus load inductance
LMAX (A)
I
100
10
A
B
C
1
0.1
1
10
100
L(mH)
A = Single Pulse at T
=150ºC
Jstart
Values are generated with R =0Ω
L
B= Repetitive pulse at T
=100ºC
Jstart
In case of repetitive pulses, T
(at beginning of
jstart
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
C= Repetitive Pulse at T
=125ºC
Jstart
Conditions:
V
=13.5V
CC
V , I
IN
L
Demagnetization
Demagnetization
Demagnetization
t
15/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
SO-8 Thermal Data
Figure 29. SO-8 PC Board
Layout condition of R and Z measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
th
th
2
2
2
Cu thickness=35µm, Copper areas: 0.14cm , 0.8cm , 2cm ).
Figure 30. R
Vs PCB copper area in open box free air condition
thj-amb
SO-8 at 2 pins connected to TAB
RTHj_amb (ºC/W)
110
105
100
95
90
85
80
75
70
0
0.5
1
1.5
2
2.5
PCBCu heatsink area (cm^2)
16/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
2
P PAK Thermal Data
2
Figure 31. P PAK PC Board
Layout condition of R and Z measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm,
th
th
2
2
Cu thickness=35µm, Copper areas: 0.97cm , 8cm ).
Figure 32. R
Vs PCB copper area in open box free air condition
thj-amb
RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
17/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
PPAK Thermal Data
Figure 33. PPAK PC Board
Layout condition of R and Z measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm,
th
th
2
2
Cu thickness=35µm, Copper areas: 0.44cm , 8cm ).
Figure 34. R
Vs PCB copper area in open box free air condition
thj-amb
RTHj_amb
(ºC/W)
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
18/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 35. SO-8 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
2
0.5 cm
100
10
2
2 cm
1
0.1
0.01
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 36. Thermal fitting model of a single
channel HSD in SO-8
Pulse calculation formula
= RTH δ + ZTHtp(1 – δ)
δ = tp ⁄ T
THδ
where
Table 14. Thermal Parameter
2
Area/island (cm )
0.5
0.05
0.8
2
28
2
R1 (°C/W)
R2 (°C/W)
R3 ( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
Tj
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
3.5
21
Pd
16
T_amb
58
0.006
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
2.60E-03
0.0075
0.045
0.35
1.05
19/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 37. PPAK Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
0.44 cm2
6 cm2
100
10
1
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 38. Thermal fitting model of a single
channel HSD in PPAK
Pulse calculation formula
= RTH δ + ZTHtp(1 – δ)
δ = tp ⁄ T
THδ
where
Table 15. Thermal Parameter
2
Area/island (cm )
0.5
0.15
0.7
6
24
5
R1 (°C/W)
R2 (°C/W)
R3 ( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Tj
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
1.6
2
Pd
15
T_amb
61
0.0006
0.0025
0.08
0.3
0.45
0.8
20/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
2
Figure 39. P PAK Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
100
10
1
2
0.5 cm
2
6 cm
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 40. Thermal fitting model of a single
channel HSD in P PAK
Pulse calculation formula
2
= RTH δ + ZTHtp(1 – δ)
δ = tp ⁄ T
THδ
where
Table 16. Thermal Parameter
2
Area/island (cm )
0.5
0.15
0.7
6
R1 (°C/W)
R2 (°C/W)
R3 ( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Tj
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
0.7
4
Pd
9
T_amb
37
22
0.0006
0.0025
0.055
0.4
2
3
5
21/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
PACKAGE MECHANICAL
Table 17. SO-8 Mechanical Data
millimeters
Typ
Symbol
Min
Max
1.75
0.25
1.65
0.85
0.48
0.25
0.5
A
a1
a2
a3
b
0.1
0.65
0.35
0.19
0.25
b1
C
c1
D
45 (typ.)
4.8
5.8
5
E
6.2
e
1.27
3.81
e3
F
3.8
0.4
4
L
1.27
0.6
M
S
8 (max.)
L1
0.8
1.2
Figure 41. SO-8 Package Dimensions
22/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
PACKAGE MECHANICAL
Table 18. PENTAWATT (VERTICAL) Mechanical Data
millimeters
Typ
Symbol
Min
Max
4.8
A
C
1.37
2.8
D
D1
E
2.4
1.2
0.35
0.8
1
1.35
0.55
1.05
1.4
F
F1
G
3.2
6.6
3.4
6.8
3.6
G1
H2
H3
L
7
10.4
10.4
10.05
17.85
15.75
21.4
L1
L2
L3
L5
L6
L7
M
22.5
2.6
15.1
6
3
15.8
6.6
4.5
4
M1
Diam.
3.65
3.85
Figure 42. PENTAWATT (VERTICAL) Package Dimensions
23/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
PACKAGE MECHANICAL
2
Table 19. P PAK Mechanical Data
millimeters
Typ
Symbol
Min
Max
4.80
2.80
0.23
1.05
0.60
1.37
9.35
A
4.30
2.40
0.03
0.80
0.45
1.17
8.95
A1
A2
b
c
c2
D
D2
8.00
8.50
E
10.00
10.40
E1
e
3.20
6.60
13.70
1.25
0.90
1.55
3.60
7.00
14.50
1.40
1.70
2.40
e1
L
L2
L3
L5
R
V2
0.40
0º
8º
Package Weight
1.40 Gr (typ)
2
Figure 43. P PAK Package Dimensions
P010R
24/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
PACKAGE MECHANICAL
Table 20. PPAK Mechanical Data
Symbol
millimeters
Min
2.20
0.90
0.03
0.40
5.20
0.45
0.48
Typ
Max
2.40
1.10
0.23
0.60
5.40
0.60
0.60
A
A1
A2
B
B2
C
C2
D1
5.1
D
6.00
6.40
6.20
6.60
E
E1
4.7
e
1.27
G
4.90
2.38
9.35
5.25
2.70
10.10
1.00
1.00
G1
H
L2
0.8
0.2
L4
0.60
0º
R
V2
8º
Package Weight
Gr. 0.3
Figure 44. PPAK Package Dimensions
P032T1
25/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 45. SO-8 TUBE SHIPMENT (no suffix)
B
Base Q.ty
100
2000
532
3.2
6
C
Bulk Q.ty
Tube length (± 0.5)
A
A
B
C (± 0.1)
0.6
All dimensions are in mm.
Figure 46. SO-8 TAPE AND REEL SHIPMENT (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
P0 (± 0.1)
P
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
8
D (± 0.1/-0) 1.5
Hole Diameter
D1 (min)
F (± 0.05)
K (max)
1.5
5.5
4.5
2
Hole Position
Compartment Depth
Hole Spacing
P1 (± 0.1)
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
26/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 47. PENTAWAT TUBE SHIPMENT (no suffix)
Base Q.ty
50
1000
532
18
Bulk Q.ty
B
Tube length (± 0.5)
A
B
33.1
1
C (± 0.1)
C
All dimensions are in mm.
A
27/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
2
Figure 48. P PAK TUBE SHIPMENT (no suffix)
Base Q.ty
50
1000
532
18
Bulk Q.ty
B
Tube length (± 0.5)
A
B
33.1
1
C
C (± 0.1)
All dimensions are in mm.
A
2
Figure 49. P PAK TAPE AND REEL SHIPMENT (suffix “TR”)
REEL DIMENSIONS
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
1000
330
1.5
13
20.2
24.4
60
G (+ 2 / -0)
N (min)
T (max)
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (± 0.1)
P
16
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
1.5
1.5
11.5
6.5
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
28/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
Figure 50. PPAK SUGGESTED PAD LAYOUT and TUBE SHIPMENT (no suffix)
A
C
Base Q.ty
75
3000
532
6
Bulk Q.ty
Tube length (± 0.5)
A
B
B
21.3
0.6
C (± 0.1)
3
1.8
6.7
All dimensions are in mm.
Figure 51. PPAK TAPE AND REEL SHIPMENT (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
2500
2500
330
1.5
13
20.2
16.4
60
G (+ 2 / -0)
N (min)
T (max)
22.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
16
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (± 0.1)
P
8
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
1.5
1.5
7.5
2.75
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
29/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
REVISION HISTORY
Table 21. Revision History
Date
Revision
Description of Changes
Oct. 2004
1
- First Issue.
30/31
VN750-E / VN750S-E / VN750PT-E / VN750B5-E
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