VN750PSTR-E [STMICROELECTRONICS]
High-side driver; 高侧驱动器
| 型号： | VN750PSTR-E |
| 厂家： | 
ST |
| 描述： | High-side driver |
| 文件： | 总27页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VN750PS-E
High-side driver
Features
Type
RDS(on)
IOUT
VCC
VN750PS-E
60 mΩ
6 A
36 V
®
■ ECOPACK : lead free and RoHS compliant
SO-8
■ Automotive Grade: compliance with AEC
guidelines
■ CMOS compatible input
■ On-state open-load detection
■ Off-state open-load detection
■ Shorted load protection
Description
The VN750PS-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0-3
Technology intended for driving any kind of load
with one side connected to ground.
■ Undervoltage and overvoltage shutdown
■ Protection against loss of ground
■ Very low standby current
Active V pin voltage clamp protects the device
CC
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart help protect the device against overload.
■ Reverse battery protection
The device detects open load condition in on and
off-state. Output shorted to V is detected in the
CC
off-state. Device automatically turns off in case of
ground pin disconnection.
Table 1.
Package
Device summary
Order codes
Tube
Tape and reel
SO-8
VN750PS-E
VN750PSTR-E
October 2010
Doc ID 16782 Rev 2
1/27
www.st.com
1
Contents
VN750PS-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SO-8 maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . 19
3
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
4.2
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
Doc ID 16782 Rev 2
VN750PS-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical transient requirements on V pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Electrical transient requirements on V pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Electrical transient requirements on V pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CC
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 16782 Rev 2
3/27
List of figures
VN750PS-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. On-state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
case
Figure 14. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Figure 15. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
lim
case
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. SO-8 maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29. SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Thermal fitting model of a single channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31. SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/27
Doc ID 16782 Rev 2
VN750PS-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
V
CC
OVERVOLTAGE
DETECTION
V
CC
CLAMP
UNDERVOLTAGE
DETECTION
GND
Power CLAMP
DRIVER
OUTPUT
LOGIC
INPUT
CURRENT LIMITER
ON-STATE OPEN-LOAD
DETECTION
STATUS
OVER TEMPERATURE
DETECTION
OFF-STATE OPEN-LOAD
AND OUTPUT SHORTED TO V
DETECTION
CC
Figure 2.
Configuration diagram (top view)
5
4
V
N.C.
CC
OUTPUT
OUTPUT
STATUS
INPUT
GND
8
1
V
CC
SO-8
Table 2.
Suggested connections for unused and not connected pins
Connection/pin
Status
N.C.
Output
Input
Floating
X
X
X
X
X
To ground
Through 10 KΩ resistor
Doc ID 16782 Rev 2
5/27
Electrical specifications
VN750PS-E
2
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VF
IIN
V
CC
INPUT
ISTAT
IOUT
STATUS
VCC
OUTPUT
GND
VIN
VOUT
VSTAT
IGND
2.1
Absolute maximum ratings
Stress values that exceed those listed in the “Absolute maximum ratings” table can cause
permanent damage to the device. These are stress ratings only and operation of the device
at these or any other conditions greater than those indicated in the operating sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Refer also to the STMicroelectronics sure program and
other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
-VCC
-Ignd
IOUT
-IOUT
IIN
DC supply voltage
41
- 0.3
V
V
Reverse DC supply voltage
DC reverse ground pin current
DC output current
- 200
mA
A
Internally limited
- 6
Reverse DC output current
DC input current
A
+/-10
mA
mA
ISTAT
DC status current
+/- 10
Electrostatic discharge
(human body model: R = 1.5 KΩ; C = 100 pF)
- Input
- Status
- Output
- VCC
VESD
4000
4000
5000
5000
V
V
V
V
6/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
Table 3.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
Maximum switching energy
EMAX
100
mJ
(L = 1.8 mH; RL = 0 Ω; Vbat = 13.5 V;
Tjstart = 150 °C; IL = 9 A)
Ptot
Tj
Power dissipation TC = 25 °C
Junction operating temperature
Case operating temperature
Storage temperature
4.2
W
°C
°C
°C
Internally limited
- 40 to 150
Tc
Tstg
- 55 to 150
2.2
Thermal data
Table 4.
Symbol
Rthj-lead
Thermal data
Parameter
Max. value
Unit
Thermal resistance junction-lead
30
°C/W
°C/W
°C/W
93(1)
82(2)
Rthj-amb
Thermal resistance junction-ambient
1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 2 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
Doc ID 16782 Rev 2
7/27
Electrical specifications
VN750PS-E
2.3
Electrical characteristics
Values specified in this section are for 8 V < V < 36 V; -40 °C < Tj < 150 °C, unless
CC
otherwise stated.
Table 5.
Electrical characteristics
Parameter
Symbol
Test conditions
Min.
Typ.
Max.
Unit
Power
VCC
Operating supply voltage
Undervoltage shutdown
5.5
3
13
4
36
V
V
VUSD
VUSDhyst
VOV
5.5
Undervoltage shutdown
hysteresis
0.5
V
V
Overvoltage shutdown
36
IOUT = 2 A; Tj = 25 °C;
VCC > 8 V
60
120
25
mΩ
mΩ
µA
RON
On-state resistance
IOUT = 2 A; VCC>8 V
Off-state; VCC = 13 V;
VIN = VOUT = 0 V
10
10
2
Off-state; VCC = 13 V;
VIN = VOUT = 0 V; Tj = 25 °C
IS
Supply current
20
µA
On-state; VCC = 13 V;
VIN = 5 V; IOUT = 0 A
3.5
mA
IL(off1)
IL(off2)
Off-state output current
Off-state output current
VIN = VOUT = 0 V
0
50
0
µA
µA
VIN = 0 V; VOUT = 3.5 V
-75
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
IL(off3)
IL(off4)
Off-state output current
Off-state output current
5
3
µA
µA
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
Switching (VCC = 13V)
td(on) Turn-on delay time
td(off) Turn-off delay time
RL = 6.5 Ω from VIN rising
40
µs
µs
edge to VOUT = 1.3 V
RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V
30
RL = 6.5 Ω from VOUT = 1.3 V
dVOUT/dt(on) Turn-on voltage slope
See Figure 21
See Figure 22
V/µs
V/µs
to VOUT = 10.4 V
RL = 6.5 ΩfromVOUT = 11.7 V
to VOUT = 1.3 V
dVOUT/dt(off) Turn-off voltage slope
Input pin
VIL
IIL
Input low level
1.25
V
µA
V
Low level input current
Input high level
VIN = 1.25 V
1
VIH
3.25
8/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
Table 5.
Symbol
Electrical characteristics (continued)
Parameter
Test conditions
VIN = 3.25 V
Min.
Typ.
Max.
Unit
IIH
High level input current
Input hysteresis voltage
10
µA
V
Vhyst
0.5
6
I
IN = 1 mA
6.8
8
V
VICL
Input clamp voltage
IIN = -1 mA
-0.7
V
VCC output diode
VF
Forward on voltage
-IOUT = 1.3 A; Tj = 150 °C
0.6
V
Status pin
VSTAT
ILSTAT
CSTAT
Status low output voltage
Status leakage current
ISTAT = 1.6 mA
0.5
10
100
8
V
µA
pF
V
Normal operation; VSTAT = 5 V
Status pin input capacitance Normal operation; VSTAT = 5 V
I
I
STAT = 1 mA
STAT = -1 mA
6
6.8
VSCL
Status clamp voltage
-0.7
V
Protections(1)
TTSD
TR
Shutdown temperature
Reset temperature
Thermal hysteresis
150
135
7
175
15
200
°C
°C
°C
Thyst
Status delay in overload
condition
tSDL
Tj>Tjsh
20
ms
9 V<VCC<36 V
5 V<VCC<36 V
6
9
15
15
A
A
Ilim
Current limitation
Turn-off output clamp
voltage
IOUT = 2 A; VIN = 0 V;
L = 6 mH
Vdemag
VCC-41 VCC-48 VCC-55
V
Open-load detection
Open-load on-state
detection threshold
IOL
V
IN = 5 V
50
200
200
3.5
mA
µs
V
Open-load on-state
detection delay
tDOL(on)
VOL
IOUT = 0 A
VIN = 0 V
Open-load off-state voltage
detection threshold
1.5
Open-load detection delay at
turn-off
tDOL(off)
1000
µs
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device operates under abnormal conditions this software must
limit the duration and number of activation cycles.
Doc ID 16782 Rev 2
9/27
Electrical specifications
Figure 4.
VN750PS-E
Status timings
OPEN-LOAD STATUS TIMING (with external pull-up)
IOUT< IOL
OVERTEMP STATUS TIMING
VOUT > VOL
Tj > Tjsh
VIN
VIN
VSTAT
VSTAT
tDOL(off)
tDOL(on)
tSDL
tSDL
Figure 5.
Switching time waveforms
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VIN
td(on)
td(off)
t
Table 6.
Truth table
Conditions
Input
Output
Status
L
L
H
H
Normal operation
H
H
L
H
H
L
X
X
H
Current limitation
(Tj < TTSD) H
(Tj > TTSD) L
L
L
L
H
L
Over temperature
Undervoltage
Overvoltage
H
L
L
L
X
X
H
L
L
L
H
H
H
10/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
Status
Table 6.
Truth table (continued)
Conditions
Input
Output
L
H
H
L
Output voltage > VOL
H
H
L
L
H
L
Output current < IOL
H
H
Table 7.
Electrical transient requirements on V pin (part 1/3)
CC
Test levels
ISO T/R 7637/1
test pulse
Delays and
impedance
I
II
III
IV
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
Table 8.
Electrical transient requirements on V pin (part 2/3)
CC
Test levels results
ISO T/R 7637/1
test pulse
I
II
III
IV
1
2
C
C
C
C
C
C
C
C
C
C
C
E
C
C
C
C
C
E
C
C
C
C
C
E
3a
3b
4
5
Table 9.
Class
Electrical transient requirements on V pin (part 3/3)
CC
Contents
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 16782 Rev 2
11/27
Electrical specifications
Figure 6.
VN750PS-E
Waveforms
NORMAL OPERATION
UNDERVOLTAGE
INPUT
LOAD VOLTAGE
STATUS
V
V
CC
USDhyst
V
USD
INPUT
LOAD VOLTAGE
STATUS
undefined
OVERVOLTAGE
V <V
CC OV
V >V
CC OV
V
CC
INPUT
LOAD VOLTAGE
STATUS
OPEN LOAD with external pull-up
INPUT
V
>V
OUT OL
LOAD VOLTAGE
STATUS
V
OL
OPEN LOAD without external pull-up
INPUT
LOAD VOLTAGE
STATUS
OVER TEMPERATURE
T
TSD
T
j
T
R
INPUT
LOAD CURRENT
STATUS
12/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
2.4
Electrical characteristics curves
Figure 7.
Off-state output current
Figure 8.
High level input current
Iih (uA)
7
IL(off1) (uA)
3
2.5
2
6
5
4
3
2
1
0
Vin=3.25V
Off state
Vcc=36V
Vin=Vout=0V
1.5
1
0.5
0
-0.5
-1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100 125 150 175
Tc (ºC)
Tc (ºC)
Figure 9.
Input clamp voltage
Figure 10. Status leakage current
Ilstat (uA)
0.05
Vicl (V)
8
7.8
7.6
7.4
7.2
7
Iin=1mA
0.04
Vstat=5V
0.03
6.8
6.6
6.4
6.2
6
0.02
0.01
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100 125 150
175
Tc (°C)
Tc (°C)
Figure 11. Status low output voltage
Figure 12. Status clamp voltage
Vscl (V)
8
Vstat (V)
0.6
7.8
Istat=1mA
0.5
7.6
Istat=1.6mA
7.4
7.2
7
0.4
0.3
0.2
0.1
0
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
Doc ID 16782 Rev 2
13/27
Electrical specifications
VN750PS-E
Figure 13. On-state resistance vs T
Figure 14. On-state resistance vs V
CC
case
Ron (mOhm)
140
Ron (mOhm)
120
110
100
90
80
70
60
50
40
30
20
120
Iout=2A
Iout=2A
Vcc=8V; 13V; 36V
Tc= 150°C
Tc= 125°C
100
80
60
40
20
0
Tc= 25°C
Tc= - 40°C
-50
-25
0
25
50
75
100 125
150
175
5
10
15
20
25
30
35
40
Tc (ºC)
Vcc (V)
Figure 15. Open-load on-state detection Figure 16. Input high level
threshold
Iol (mA)
220
Vih (V)
3.6
200
180
160
140
120
100
80
3.4
3.2
3
Vcc=13V
Vin=5V
2.8
2.6
2.4
2.2
60
40
20
0
2
-50
-25
0
25
50
75
100 125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Figure 17. Input low level
Figure 18. Input hysteresis voltage
Vil (V)
2.8
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
14/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
Figure 19. Overvoltage shutdown
Figure 20. Open-load off-state voltage
detection threshold
Vol (V)
5
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
4.5
Vin=0V
4
3.5
3
2.5
2
1.5
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
Figure 21. Turn-on voltage slope
Figure 22. Turn-off voltage slope
dVout/dt/(on) (V/ms)
1000
dVout/dt(off) (V/ms)
500
900
450
Vcc=13V
Vcc=13V
Rl=6.5Ohm
800
400
Rl=6.5Ohm
700
350
600
500
400
300
200
100
0
300
250
200
150
100
50
0
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100 125
150
175
Tc (ºC)
Tc (ºC)
Figure 23. I vs T
lim
case
Ilim (A)
20
18
Vcc=13V
16
14
12
10
8
6
4
2
0
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Doc ID 16782 Rev 2
15/27
Electrical specifications
VN750PS-E
Figure 24. Application schematic
+5V
+5V
V
R
CC
prot
STATUS
INPUT
D
ld
R
μC
prot
OUTPUT
GND
R
GND
V
D
GND
GND
2.5
GND protection network against reverse battery
Solution 1: resistor in the ground line (R
only). This can be used with any type of load.
GND
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤ 600 mV / (I
).
S(on)max
GND
GND
≥ (−V ) / (−I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power dissipation in R
(when V < 0: during reverse battery situations) is:
CC
GND
2
P = (−V ) /R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
produces a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift varies depending on how many devices are on in the case of several high
side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize solution 2 (see below).
Solution 2: diode (D
) in the ground line A resistor (R
=1 kΩ) should be inserted in
GND
GND
parallel to D
if the device drives an inductive load.
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
16/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in input and status lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused input and status pin is to leave them unconnected.
2.6
2.7
Load dump protection
D is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
µ
CCpeak latchup
prot
OH C IH GND IHmax
Calculation example:
For V
= - 100 V and I
≥ 20 mA; V
≥ 4.5 V
µ
OH C
CCpeak
latchup
5 kΩ ≤ R
≤ 65 kΩ.
prot
Recommended values: R
= 10 kΩ.
prot
2.8
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (R ) connected between
PU
output pin and a positive supply voltage (V ) like the +5V line used to supply the
PU
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open-load indication when load is connected: in this case we have to avoid
V
to be higher than V
; this results in the following condition
OUT
Olmin
V
= (V / (R + R ))R < V
.
OUT
PU
L
PU
L
Olmin
2. no misdetection when load is disconnected: in this case the V
has to be higher than
OUT
V
; this results in the following condition R < (V – V
) / I
.
OLmax
PU
PU
OLmax
L(off2)
Because I
may significantly increase if V is pulled high (up to several mA), the pull-
out
s(OFF)
up resistor R should be connected to a supply that is switched off when the module is in
PU
standby.
The values of V
section.
, V
and I
are available in the electrical characteristics
OLmin OLmax
L(off2)
Doc ID 16782 Rev 2
17/27
Electrical specifications
VN750PS-E
Figure 25. Open-load detection in off-state
V batt.
V
PU
VCC
R
PU
DRIVER
+
IL(off2)
INPUT
LOGIC
OUT
+
-
R
STATUS
V
OL
R
L
GROUND
18/27
Doc ID 16782 Rev 2
VN750PS-E
Electrical specifications
2.9
SO-8 maximum demagnetization energy (VCC = 13.5 V)
Figure 26. SO-8 maximum turn-off current versus inductance
LMAX (A)
I
100
10
A
B
C
1
0.1
1
10
100
L(mH)
A: Tjstart = 150 °C single pulse
B: Tjstart = 100 °C repetitive pulse
C: Tjstart = 125 °C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R =0 Ω.In case of repetitive pulses, T
must not exceed the temperature specified above for curves A and B.
(at beginning of each demagnetization) of every pulse
L
jstart
Doc ID 16782 Rev 2
19/27
Package and PCB thermal data
VN750PS-E
3
Package and PCB thermal data
3.1
SO-8 thermal data
Figure 27. PC board
.
Note:
Layout condition of R and Z measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu
th
th
2
2
2
thickness=35 µm, Copper areas: 0.14 cm , 0.8 cm , 2 cm ).
Figure 28. R
vs PCB copper area in open box free air condition
thj-amb
SO-8 at 2 pins connected to TAB
RTHj_am b (ºC/W)
110
105
100
95
90
85
80
75
70
0
0.5
1
1.5
2
2.5
PCBCu heatsink area (cm^2)
20/27
Doc ID 16782 Rev 2
VN750PS-E
Package and PCB thermal data
Figure 29. SO-8 thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
2
0.5 cm
100
10
2
2 cm
1
0.1
0.01
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
Figure 30. Thermal fitting model of a single channel
Doc ID 16782 Rev 2
21/27
Package and PCB thermal data
VN750PS-E
Table 10. Thermal parameter
Area/island (cm2)
0.5
2
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W·s/°C)
C2 (W·s/°C)
C3 (W·s/°C)
C4 (W·s/°C)
C5 (W·s/°C)
C6 (W·s/°C)
0.05
0.8
3.5
21
16
58
28
0.006
0.0026
0.0075
0.045
0.35
1.05
2
22/27
Doc ID 16782 Rev 2
VN750PS-E
Package and packing information
4
Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
4.1
SO-8 package information
Figure 31. SO-8 package dimensions
0016023 D
Doc ID 16782 Rev 2
23/27
Package and packing information
VN750PS-E
Table 11.
Dim.
SO-8 mechanical data
mm
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.25
0.10
1.25
0.28
0.17
4.80
5.80
3.80
0.48
0.23
5.00
6.20
4.00
c
D(1)
4.90
6.00
3.90
1.27
E
E1(2)
e
h
0.25
0.40
0.50
1.27
L
L1
k
1.04
0°
8°
ccc
0.10
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both side).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
24/27
Doc ID 16782 Rev 2
VN750PS-E
Package and packing information
4.2
SO-8 packing information
The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1).
Figure 32. SO-8 tube shipment (no suffix)
Base Q.ty
100
2000
532
3.2
6
B
C
A
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
0.6
All dimensions are in mm.
Figure 33. SO-8 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
2500
2500
330
1.5
13
20.2
12.4
60
G (+ 2 / -0)
N (min)
T (max)
18.4
All dimensions are in mm.
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
12
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (± 0.1)
P
8
D (+0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
1.5
1.5
5.5
4.5
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
Doc ID 16782 Rev 2
25/27
Revision history
VN750PS-E
5
Revision history
Table 12. Document revision history
Date
Revision
Changes
23-Nov-2009
1
Initial release.
Updated Table 4: Thermal data
Updated following figure titles:
– Figure 21: Turn-on voltage slope
– Figure 22: Turn-off voltage slope
15-Oct-2010
2
26/27
Doc ID 16782 Rev 2
VN750PS-E
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