VN5010AK-E [STMICROELECTRONICS]
High side driver with analog current sense for automotive applications; 模拟电流检测用于汽车应用的高侧驱动器
| 型号： | VN5010AK-E |
| 厂家： | 
ST |
| 描述： | High side driver with analog current sense for automotive applications |
| 文件： | 总31页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VN5010AK-E
High side driver with analog current sense
for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
Max On-State resistance
Current limitation (typ)
Off state supply current (typ)
VCC 4.5 to 36V
TM
PowerSSO-24
RON
ILIMH
IS
10 mΩ
65A
– Electrostatic discharge protection
2 µA
Application
■ Main features
■ All types of resistive, inductive and capacitive
– Inrush current active management by
power limitation
loads
– Very low stand-by current
Description
– 3.0v CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
The VN5010AK-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
■ Diagnostic functions
ground. Active V pin voltage clamp protects the
CC
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
device against low energy spikes (see ISO7637
transient compatibility table). This device
integrates an analog current sense which delivers
a current proportional to the load current
(according to a known ratio) when CS_DIS is
driven low or left open. When CS_DIS is driven
high, the CURRENT SENSE pin is in a high
impedance condition. Output current limitation
protects the device in overload condition. In case
of long overload duration, the device limits the
dissipated power to safe level up to thermal shut-
down intervention. Thermal shut-down with
automatic restart allows the device to recover
normal operation as soon as fault condition
disappears.
■ Protections
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Thermal shut down
– Reverse battery protection (see Application
schematic )
Table 1.
Device summary
Package
Order codes
Tube
Tape and Reel
PowerSSO-24TM
VN5010AK-E
VN5010AKTR-E
February 2008
Rev 4
1/31
www.st.com
31
Contents
VN5010AK-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1
3.1.2
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 21
Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 22
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum demagnetization energy (VCC=13.5V) . . . . . . . . . . . . . . . . . . . 23
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
PowerSSO-24TM thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
5.2
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VN5010AK-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC=13V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VN5010AK-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Delay response time between rising edge of ouput current and rising edge of Current Sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6.
Figure 7.
Figure 8.
Figure 9.
I
vs. I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT/ISENSE
OUT
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off State output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On state resistance vs. T
Figure 18. On state resistance vs. V
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21.
I
vs. T
LIMH case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn Off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TM
Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 24
TM
Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25
TM
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TM
Figure 33. PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TM
Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
VN5010AK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
V
CC
V
CC
UNDERVOLTAGE
PwCLAMP
CLAMP
DRIVER
OUTPUT
GND
I
LIM
V
DSLIM
LOGIC
Pwr
LIM
INPUT
OVERTEMP.
I
OUT
CURRENT
SENSE
K
CS_DIS
Table 2.
Pin function
Name
VCC
Function
Battery connection.
Power output.
OUTPUT
Ground connection. Must be reverse battery protected by an external
diode/resistor network.
GND
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
INPUT
CURRENT
SENSE
Analog current sense pin, delivers a current proportional to the load current.
Active high CMOS compatible pin, to disable the current sense pin.
CS_DIS
5/31
Block diagram and pin description
Figure 2. Connection diagram (top view)
VN5010AK-E
VCC
1
2
3
4
5
6
24
23
22
21
20
19
NC
NC
NC
OUTPUT
OUTPUT
OUTPUT
GND
NC
NC
INPUT
NC
7
8
9
10
11
12
18
17
16
15
14
13
OUTPUT
OUTPUT
OUTPUT
NC
NC
NC
CURRENT SENSE
NC
CS_DIS
NC
NC
VCC
TAB = Vcc
Table 3.
Suggested connections for unused and N.C. pins
Connection / Pin
Current Sense
N.C.
Output
Input
CS_DIS
Floating
N.R.(1)
X
X
X
X
Through 10kΩ
Through 10kΩ
To Ground
Through 1kΩ resistor
X
N.R.
resistor
resistor
1. Not recommended.
6/31
VN5010AK-E
Electrical specifications
2
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
IOUT
ICSD
CS_DIS
INPUT
OUTPUT
VOUT
VCSD
IIN
ISENSE
CURRENT SENSE
GND
VSENSE
VIN
IGND
Note:
V
= V
- V during reverse battery condition.
Fn
OUT CC
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
41
Unit
V
VCC
DC supply voltage
-VCC
Reverse DC supply voltage
0.3
V
- IGND DC reverse ground pin current
IOUT DC output current
- IOUT Reverse DC output current
200
mA
Internally
limited
A
30
A
IIN
DC input current
-1 to 10
-1 to 10
200
mA
mA
mA
ICSD
DC Current Sense disable input current
-ICSENSE DC reverse CS pin current
7/31
Electrical specifications
VN5010AK-E
Table 4.
Symbol
Absolute maximum ratings (continued)
Parameter
Value
Unit
VCC-41
+VCC
V
V
VCSENSE Current Sense maximum voltage
Maximum switching energy (single pulse)
EMAX
VESD
VESD
Tj
609
mJ
V
(L=1.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
Electrostatic discharge (Human Body Model: R=1.5KΩ; C=100pF)
- INPUT
4000
2000
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
750
V
-40 to 150
-55 to 150
°C
°C
Tstg
Table 5.
Symbol
Thermal data
Parameter
Max value
0.3
See Figure 29.
Unit
Rthj-case Thermal resistance junction-case (MAX)
Rthj-amb Thermal resistance junction-ambient (MAX)
°C/W
°C/W
8/31
VN5010AK-E
Electrical specifications
2.2
Electrical characteristics
Values specified in this section are for 8V< V < 36V; -40°C< T < 150°C, unless otherwise
CC
j
stated (for each channel).
Table 6.
Symbol
Power section
Parameter
Test conditions
Min. Typ. Max. Unit
Operating supply
voltage
VCC
VUSD
VUSDhyst
4.5
13
3.5
0.5
36
V
V
V
Undervoltage
shutdown
4.5
Undervoltage
shutdown hysteresis
I
OUT= 6A; Tj= 25°C
10
20
mΩ
mΩ
RON
On state resistance
IOUT= 6A; Tj= 150°C
Vclamp Clamp voltage
ICC= 20 mA
41
46
52
V
Off State; VCC= 13V; Tj= 25°C;
VIN=VOUT=VSENSE=VCSD=0V
IS
IL(off)
VF
Supply current
2(1)
5(1)
µA
µA
VIN=VOUT=0V; VCC= 13V; Tj= 25°C
VIN=VOUT=0V; VCC= 13V; Tj= 125°C
0
0
0.01
3
5
Off state output
current
Output - VCC diode
voltage
-IOUT= 10A; Tj= 150°C
0.7
V
1. PowerMOS leakage included.
.
Table 7.
Symbol
Switching (V =13V)
CC
Parameter
Test conditions
RL= 2.6Ω (see Figure 8.)
RL= 2.6Ω (see Figure 8.)
Min.
Typ.
Max. Unit
td(on)
td(off)
Turn-On delay time
Turn-Off delay time
35
65
µs
µs
Turn-On voltage
slope
See
Figure 20
(dVOUT/dt)on
(dVOUT/dt)off
WON
RL= 2.6Ω
V/ µs
V/ µs
mJ
Turn-Off voltage
slope
See
Figure 22
RL= 2.6Ω
Switching energy
losses during twon
RL= 2.6Ω (see Figure 8.)
RL= 2.6Ω (see Figure 8.)
1.5
0.8
Switching energy
losses during twoff
WOFF
mJ
9/31
Electrical specifications
VN5010AK-E
Table 8.
Symbol
Logic input
Parameter
Test conditions
Min. Typ. Max. Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
0.9
V
µA
V
VIN= 0.9V
VIN= 2.1V
1
VIH
IIH
2.1
10
µA
V
VI(hyst) Input hysteresis voltage
VICL Input clamp voltage
0.25
5.5
IIN= 1mA
IIN= -1mA
7
V
V
-0.7
VCSDL CS_DIS low level voltage
ICSDL Low level CS_DIS current
VCSDH CS_DIS high level voltage
ICSDH High level CS_DIS current
0.9
V
µA
V
VCSD= 0.9V
VCSD= 2.1V
1
2.1
10
7
µA
V
VCSD(hyst) CS_DIS hysteresis voltage
0.25
5.5
I
CSD= 1mA
V
V
VCSCL CS_DIS clamp voltage
ICSD= -1mA
-0.7
(1)
Table 9.
Symbol
Protections and diagnostics
Parameter
Test conditions
Min.
Typ.
Max. Unit
V
CC= 13V
46
65
91
91
A
A
IlimH
Short circuit current
5V<VCC<36V
VCC= 13V;
Short circuit current during
thermal cycling
IlimL
24
A
TR<Tj<TTSD
TTSD Shutdown temperature
150
175
200
°C
°C
°C
°C
TR
Reset temperature
TRS+1 TRS+5
TRS
Thermal reset of STATUS
135
THYST Thermal hysteresis (TTSD-TR)
VDEMAG Turn-Off output voltage clamp IOUT=2A; VIN=0; L=6mH
7
VCC
-41
VCC
-46
VCC
-52
V
Output voltage drop
limitation
IOUT=0.5A (see Figure 9.);
VON
25
mV
Tj= -40°C...+150°C
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/31
VN5010AK-E
Electrical specifications
Table 10. Current sense (8V<V <16V)
CC
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
IOUT= 0.25A;
VSENSE=0.5V;VCSD=0V;
K0
IOUT SENSE
/I
2770 5490 8220
Tj= -40°C...150°C
IOUT= 6A; VSENSE=0.5V; VCSD=0V;
Tj= -40°C...150°C
3610 4580 5630
3930 4580 5230
K1
IOUT/ISENSE
IOUT= 6A; VSENSE=0.5V; VCSD=0V;
Tj= 25°C...150°C
IOUT= 6A; VSENSE= 0.5V;
VCSD= 0V;
Current sense ratio
drift
(1)
dK1/K1
-8
+8
%
%
%
TJ= -40 °C to 150 °C
IOUT= 10A; VSENSE=4V; VCSD=0V;
Tj=-40°C...150°C
4000 4570 5220
4180 4570 4960
K2
IOUT/ISENSE
IOUT= 10A; VSENSE=4V; VCSD=0V;
Tj=25°C...150°C
IOUT= 10A; VSENSE= 4V;
VCSD=0V;
Current sense ratio
drift
(1)
dK2/K2
-5
+5
TJ= -40 °C to 150 °C
IOUT= 25A; VSENSE=4V; VCSD=0V;
Tj= -40°C...150°C
4480 4660 4980
4500 4660 4820
K3
IOUT/ISENSE
IOUT= 25A; VSENSE=4V; VCSD=0V;
Tj= 25°C...150°C
IOUT= 25A; VSENSE= 4V;
VCSD=0V;
Current sense ratio
drift
(1)
dK3/K3
-3
+3
TJ= -40 °C to 150 °C
IOUT= 0A; VSENSE=0V;
VCSD= 5V; VIN=0V; Tj= -40°C...150°C
VCSD= 0V; VIN=5V; Tj= -40°C...150°C
0
0
1
2
µA
µA
Analog sense
leakage current
ISENSE0
IOUT= 2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj= -40°C...150°C
0
1
µA
Openload On state
current detection
threshold
IOL
VIN = 5V, ISENSE= 5 µA
IOUT=15A; VCSD=0V;
10
45
mA
Max analog sense
output voltage
VSENSE
5
V
V
Analog sense output
voltage in
overtemperature
condition
VSENSEH
VCC= 13V; RSENSE= 3.9KΩ
9
8
Analog sense output
current in
overtemperature
condition
ISENSEH
VCC= 13V; VSENSE= 5V
mA
11/31
Electrical specifications
Table 10. Current sense (8V<V <16V) (continued)
VN5010AK-E
CC
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSENSE<4V, 1.5A<Iout<25A
Delay response time
tDSENSE1H from falling edge of
CS_DIS pin
50
5
100
20
µs
µs
µs
ISENSE= 90% of ISENSE max
(see Figure 4.)
VSENSE<4V, 1.5A<Iout<25A
Delay response time
tDSENSE1L from rising edge of
CS_DIS pin
ISENSE= 10% of ISENSE max
(see Figure 4.)
VSENSE<4V, 1.5A<Iout<25A
Delay response time
tDSENSE2H from rising edge of
INPUT pin
270 500
ISENSE= 90% of ISENSE max
(see Figure 4.)
Delay response time
between rising edge
of output current and
rising edge of current
sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=15A (see Figure 5)
∆
t
310
µs
µs
DSENSE2H
VSENSE<4V, 1.5A<Iout<25A
Delay response time
tDSENSE2L from falling edge of
INPUT pin
100 250
ISENSE=10% of ISENSE max
(see Figure 4.)
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H tDSENSE1L
tDSENSE1H
tDSENSE2L
12/31
VN5010AK-E
Figure 5.
Electrical specifications
Delay response time between rising edge of ouput current and rising
edge of Current Sense (CS enabled)
V
IN
∆t
DSENSE2H
t
t
t
I
OUT
I
OUTMAX
90% I
OUTMAX
I
SENSE
I
SENSEMAX
90% I
SENSEMAX
13/31
Electrical specifications
Figure 6.
VN5010AK-E
I
/I
vs. I
(see Table 10. for details)
OUT SENSE
OUT
I
/I
OUT SENSE
6000
5500
5000
max Tj = -40°C to 150°C
max Tj= 25°C to 150°C
min Tj= 25°C to 150°C
typical value
4500
4000
3500
3000
min Tj= -40°C to 150°C
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
I
(A)
OUT
Figure 7.
Maximum current sense ratio drift vs load current
dk/k(%)
15
10
5
0
-5
-10
-15
5
10
15
20
25
IOUT (A)
Note:
Parameter guaranteed by design; it is not tested.
14/31
VN5010AK-E
Electrical specifications
Sense (VCSD=0V) (1)
Table 11. Truth table
Conditions
Input
Output
L
L
0
Normal operation
H
H
Nominal
L
L
L
0
Overtemperature
Undervoltage
H
VSENSEH
L
L
L
0
0
H
L
H
H
L
L
L
0
Short circuit to GND
0 if Tj < TTSD
(Rsc ≤10 mΩ)
VSENSEH if Tj > TTSD
L
H
H
0
Short circuit to VCC
H
< Nominal
Negative output voltage clamp
L
L
0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 8.
Switching characteristics
V
OUT
t
tWon
80%
Woff
90%
dV
/dt
dV
/dt
OUT (off)
OUT (on)
10%
t
t
f
r
t
INPUT
t
t
d(on)
d(off)
t
Figure 9.
Output voltage drop limitation
Vcc-Vout
o
o
Tj=150 C
Tj=25 C
o
Tj=-40 C
Von
Iout
Von/Ron(T)
15/31
Electrical specifications
Table 12. Electrical transient requirements
VN5010AK-E
Test levels (1)
ISO 7637-2:
2004(E)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
Test pulse
1
-75V
+37V
-100V
+75V
-6V
-100V
+50V
-150V
+100V
-7V
5000 pulses
5000 pulses
1h
0.5 s
0.2 s
5 s
2 ms, 10 Ω
50 µs, 2 Ω
2a
3a
5 s
90 ms
90 ms
100 ms
100 ms
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01Ω
400 ms, 2 Ω
3b
1h
4
1 pulse
1 pulse
5b (2)
+65V
+87V
Test level results(1)
ISO 7637-2:
2004(E)
III
C
C
C
C
C
C
IV
C
C
C
C
C
C
Test pulse
1
2a
3a
3b
4
5b (2)
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
16/31
VN5010AK-E
Figure 10. Waveforms
Electrical specifications
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
V
USDhyst
V
CC
V
USD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO V
CC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
T
TSD
T
T
R
j
T
RS
INPUT
CS_DIS
I
LIMH
LIML
I
LOAD CURRENT
SENSE CURRENT
V
SENSEH
thermal cycling
SHORTED LOAD
current
limitation
power
limitation
NORMAL LOAD
17/31
Electrical specifications
VN5010AK-E
2.3
Electrical characteristics curves
Figure 11. Off State output current
Figure 12. High level input current
Iloff (uA)
0.7
Iih (uA)
5
4.5
0.6
Vin=2.1V
4
Off state
0.5
0.4
0.3
0.2
0.1
0
Vcc=13V
Vin=Vout=0V
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
125
125
150
150
150
175
175
175
-50
-25
0
25
50
75
100
125
150
150
150
175
175
175
Tc (°C )
Tc (°C )
Figure 13. Input clamp voltage
Figure 14. Input low level
Vicl (V)
7
Vil (V)
2
6.8
1.8
1.6
1.4
1.2
1
Iin=1mA
6.6
6.4
6.2
6
5.8
5.6
5.4
5.2
5
0.8
0.6
0.4
0.2
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
Figure 15. Input high level
Figure 16. Input hysteresis voltage
Vih (V)
4
Vihyst (V)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
18/31
VN5010AK-E
Electrical specifications
Figure 17. On state resistance vs. T
Figure 18. On state resistance vs. V
CC
case
Ron (mOhm)
20
Ron (mOhm)
50
18
16
14
12
10
8
45
Io ut=6A
Vcc=13V
40
Tc=150°C
35
Tc=125°C
30
25
20
15
10
5
Tc=25°C
Tc=-40°C
6
4
2
0
0
0
5
10
15
20
25
30
35
40
175
175
-50
-25
0
25
50
75
100
125
150
175
175
175
Vcc (V)
Tc (°C )
Figure 19. Undervoltage shutdown
Figure 20. Turn-On voltage slope
Vusd (V)
16
dVout/dt(on) (V/ms)
1000
900
14
12
10
8
Vcc=13V
RI=2.6Ohm
800
700
600
500
400
300
200
100
0
6
4
2
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tc (°C )
Tc (°C )
Figure 21. I
vs. T
Figure 22. Turn-Off voltage slope
LIMH
case
Ilimh (A)
80
dVout/dt(off) (V/ms)
1000
900
75
70
65
60
55
50
45
40
Vcc=13V
RI=2.6Ohm
Vcc=13V
800
700
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Tc (°C )
Tc (°C )
19/31
Electrical specifications
VN5010AK-E
Figure 23. CS_DIS high level voltage
Figure 24. CS_DIS clamp voltage
Vcsdh (V)
4
Vcsdcl (V)
8
3.5
3
7.5
Ic s d =1mA
7
2.5
2
6.5
6
1.5
1
5.5
5
0.5
0
4.5
4
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 25. CS_DIS low level voltage
Vcsdl (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
20/31
VN5010AK-E
Application information
3
Application information
Figure 26. Application schematic
+5V
V
CC
R
prot
CS_DIS
D
ld
R
mC
IINPUT
prot
OUTPUT
R
CURRENT SENSE
prot
GND
R
R
GND
SENSE
V
D
GND
GND
C
ext
3.1
GND protection network against reverse battery
3.1.1
Solution 1 : resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤600mV / (I
).
GND
GND
S(on)max
≥ (−V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power Dissipation in R
(when V <0: during reverse battery situations) is:
CC
GND
2
P = (-V ) / R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
will produce a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
21/31
Application information
VN5010AK-E
3.1.2
Solution 2 : diode (D
) in the ground line
GND
A resistor (R
inductive load.
=1kΩ) should be inserted in parallel to D if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if m.ore than one HSD shares the same diode/resistor
network.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to
prot
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-V
/I
≤R
≤(V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND IHmax
Calculation example:
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤R
≤180kΩ
prot
Recommended values: R
=10kΩ, C
=10nF.
EXT
prot
22/31
VN5010AK-E
Application information
3.4
Maximum demagnetization energy (VCC=13.5V)
Figure 27. Maximum turn Off current versus load inductance
100
A
B
C
10
1
0,1
1
L (mH)
10
100
A: T
= 150°C single pulse
jstart
B: T
C: T
= 100°C repetitive pulse
= 125°C repetitive pulse
jstart
jstart
V , I
IN
L
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R =0 Ω.
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse
jstart
must not exceed the temperature specified above for curves B and C.
23/31
Package and PCB thermal data
VN5010AK-E
4
Package and PCB thermal data
4.1
PowerSSO-24TM thermal data
Figure 28. PowerSSO-24TM PC board
Note:
Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4
th th
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
2
Copper areas: from minimum pad lay-out to 8cm ).
Figure 29. R
Vs. PCB copper area in open box free air condition
thj-amb
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
24/31
VN5010AK-E
Package and PCB thermal data
Figure 30. PowerSSO-24TM thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
Footprint
100
10
2
2 cm
2
8 cm
1
0,1
0,01
1E-04 0,001 0,01
0,1
1
10
100 1000
Time (s)
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THδ
TH
THtp
where δ = t /T
P
TM(a)
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PCB thermal data
VN5010AK-E
8
Table 13. Thermal parameters
Area/island (cm2)
Footprint
0.08
0.16
6
2
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.002
0.002
0.025
0.75
1
4
5
9
2.2
17
26/31
VN5010AK-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 32. PowerSSO-24™ package dimensions
27/31
Package and packing information
VN5010AK-E
Table 14. PowerSSO-24™ mechanical data
Millimeters
Typ.
Symbol
Min.
2.15
2.15
0
Max.
2.47
2.40
0.075
0.51
0.32
10.50
7.6
A
A2
a1
b
0.33
0.23
10.10
7.4
c
D
E
e
0.8
8.8
e3
G
G1
H
h
0.1
0.06
10.5
0.4
10.1
0.55
L
0.85
10deg
4.7
N
X
4.1
6.5
Y
7.1
28/31
VN5010AK-E
Package and packing information
5.2
Packing information
Figure 33. PowerSSO-24TM tube shipment (no suffix)
Base Q.ty
Bulk Q.ty
Tube length ( 0.5)
A
49
1225
532
3.5
C
B
B
13.8
0.6
C ( 0.1)
All dimensions are in mm.
A
Figure 34. PowerSSO-24TM tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
1000
1000
330
1.5
Bulk Q.ty
A (max)
B (min)
C ( 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
P0 ( 0.1)
P
12
D ( 0.05)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
1.55
1.5
11.5
2.85
2
Compartment Depth
Hole Spacing
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
29/31
Revision history
VN5010AK-E
6
Revision history
Table 15. Document revision history
Date
Revision
Changes
24-Jan-2006
1
Initial release.
Reformatted and restructured.
09-Feb-2007
2
Added Contents, List of tables and List of figures.
Added Section 3.4: Maximum demagnetization energy (VCC=13.5V).
Document reformatted and restructured.
Table 4: Absolute maximum ratings : corrected EMAX value from 506
to 609 mJ.
Updated Table 10: Current sense (8V<VCC<16V) :
– changed tDSENSE2H max value from 600 to 500 µs.
– added dk1/k1, dk2/k2, dk3/k3, ∆tDSEN 2H, IOL parameters.
SE
Added Figure 5: Delay response time between rising edge of ouput
current and rising edge of Current Sense (CS enabled).
13-Dec-2007
3
Updated Figure 6: IOUT/ISENSE vs. IOUT (see Table 10. for
details).
Added Figure 7: Maximum current sense ratio drift vs load current.
Table 12: Electrical transient requirements : updated test level values
III and IV for test pulse 5b and notes.
Figure 31: Thermal fitting model of a double channel HSD in
PowerSSO-24TM: added note.
Corrected typing error in Table 10: Current sense (8V<VCC<16V) :
12-Feb-2008
4
changed IOL test condition from VIN = 0V to VIN = 5V.
30/31
VN5010AK-E
Please Read Carefully:
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
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31/31
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