STW3100 [STMICROELECTRONICS]

TRANSCEIVER MODULE; 收发器模块
STW3100
型号: STW3100
厂家: ST    ST
描述:

TRANSCEIVER MODULE
收发器模块

文件: 总7页 (文件大小:457K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
STW3100  
TRANSCEIVER MODULE  
REV. 1.0 - PRODUCT PREVIEW  
1
FEATURES  
Triple-band (EGSM900 / DCS1800 / PCS1900).  
Supports data transfer applications in multi-  
slots GPRS class-12  
EDGE Receive capability  
Integrates:  
– BiCMOS6G RF transceiver  
– 3 Receive Band Pass filters  
LFBGA104 (7x7x1.4mm)  
ORDERING NUMBER: STW3100  
– 3 Receive Matching Network between filters  
output & LNA input  
– PLL loop filter  
– Decoupling / DC blocking capacitors  
Insures compatibility with different Power  
2 kV Human Body Model  
Modules  
Control interfaces:  
– STW3102 Power Module  
– Power Module coming from the competition  
RF interfaces:  
– Towards Baseband: 3-wire serial interface  
with a Clock (Clk), enable (En) and a data line  
(Data).  
– Single-ended 50 ohms acceses  
– 3 in Rx  
– Towards Front-End functions 3 control pins  
– 2 in Tx  
2
DESCRIPTION  
Noise Figure in  
In a 1.4 x 7 x 7mm low-profile Ball Grid Array pack-  
age, the new modules integrate all of the key func-  
tions, requiring only a 26MHz crystal and a power  
amplifier module (PA+antenna switch functions) to  
build a complete triple-band solution from antenna  
to base band interface. Two versions are offered:  
type STw3100 addresses the European  
EGSM900, DCS1800, and PCS1900 bands while  
the STw3101 targets the US GSM850, DCS1800,  
and PCS1900 bands. The transceiver modules  
are compatible with the STMicroelectronics  
STw3102 power-amplifier module and most of the  
standard power amplifiers available on the market.  
– Low band : 5.5 dB typ  
– Hign bands : 6 dB typ  
Transmit output level:  
– EGSM band : 1 or 5 dBm typ  
– DCS & PCS bands : 1 or 5 dBm typ  
Standard Rx / Tx differential I/Q analogue  
interface  
Supply voltage range: 2.7V min / 3.3V max  
Embedded voltage regulators to supply on chip  
RF functions  
Package:  
– Full lead-free  
– 104 -BGA 7 x 7 pack  
Temperature range:  
– Case operating temperature range:  
-20°/ +70°C (fulfil specification)  
ESD handling:  
February 2004  
1/7  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  
STW3100  
3
ELECTRICAL CHARACTERISTICS  
3.1 DC SECTION  
Limiting value  
Symbol  
Parameter  
Test Condition  
Min.  
Typ.  
25  
Max.  
Unit  
Absolute Maximum Ratings  
VCC  
Tstg  
Maximum voltage supply  
Storage Temperature  
3.6  
125  
500  
V
-55  
°C  
Pdiss  
Maximum Power dissipation  
mW  
Operating Functionality range  
Top  
Operating Temperature  
-40  
2.7  
25  
85  
°C  
V
VCC  
Supply voltage on Vcc_SYN and  
Vcc_RX/TX pins  
3.3  
Operating Specified range  
Top  
Operating Temperature  
-20  
2.7  
25  
70  
°C  
V
VCC  
Supply voltage on Vcc_SYN and  
Vcc_RX/TX pins  
3.3  
DC characteristics  
VCC = 2.7V;  
Symbol  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Pin Vcc_syn  
Icc  
Icc  
Icc  
Supply current in power off mode  
Supply current in REF mode  
Supply in Syn mode  
10  
3
µA  
mA  
mA  
35  
Pin Vcc_RX/TX  
Icc  
Icc  
Icc  
Supply current in power off mode  
10  
35  
88  
µA  
mA  
mA  
Supply current in RX mode  
Supply current in TX mode GSM  
bands  
Icc  
Supply current in TX mode DCS  
or PCS bands  
88  
mA  
Pin Vccreg_RFVCO  
Vccreg Internal regulated supply voltage  
Pin Vccreg_TXVCO  
2
2
V
V
V
Vccreg Internal regulated supply voltage  
Pin Vccreg_Digital  
Vccreg Internal regulated supply voltage  
1.8  
2/7  
STW3100  
3.2 Receive Section  
Vcc = 2.7V;  
Symbol  
Parameter  
Input Frequency  
Test Condition  
EGSM900  
Min.  
925  
Typ.  
Max.  
Unit  
fRX2  
fRX3  
fRX4  
Zin  
960  
1880  
1990  
MHz  
GSM1800  
1805  
1930  
GSM1900  
Input impedance  
Single-Ended  
50  
1.8  
1
VSWR_in Input VSWR into 50 ohm  
2.3  
2
Ripple  
Gain Flatness over the Frf  
band  
dB  
dB  
Gmax  
Total max gain  
in 2Vpp Mode  
in 4Vpp Mode  
74  
80  
79  
85  
G  
Gain range  
66  
3
dB  
AGC gain step  
AGC linearity  
Noise figure DSB  
-
-
-1  
+1  
dB  
dB  
NF  
ICP-1dB  
IIP3  
Low Band  
5.5  
6
High Band  
1dB Input Compression Point  
@ Low gain, 0kHz offset  
Low Band  
-23  
-26  
-14  
-14  
+44  
-20  
-23  
-10  
-12  
dBm  
dBm  
High Band  
Third Order Input Intercept  
Point @ High Front-end gain  
Low Band  
High Band  
nd  
IIP2  
C/N  
High Front-end gain  
dBm  
dB  
2
Order Input Intercept Point  
Out-of-band Blocking (a, b, c, d) Pwanted= -100 dBm,  
9
in Low-Band & (a , d) in High-  
Band  
P
interf= -1 dBm  
(1 dB Insertion Losses for  
antenna switch)  
C/N  
C/N  
Out-of-band Blocking (c, b) in  
High-Band  
P
P
wanted= -100 dBm,  
interf= -13 dBm  
9
9
dB  
dB  
In-Band Blocking @  
|F-Fo|> 3 MHz  
Pwanted= -100 dBm,  
P
P
interf= -24 dBm (LB)  
interf= -27 dBm (HB)  
C/N  
C/N  
In-Band Blocking @  
1.6 MHz < |F-Fo| < 3 MHz  
Pwanted= -100 dBm,  
interf= -34 dBm  
9
9
dB  
dB  
P
In-Band Blocking @  
600 kHz < |F-Fo| < 1.6 MHz  
Pwanted= -100 dBm,  
interf= -44 dBm  
P
BW_GMSK 3 dB Channel bandwidth  
BW_EDGE  
after calibration  
90  
110  
110  
140  
kHz  
dB  
Att GMSK Channel response attenuation  
Mode  
@ 200 kHz  
@ 400 kHz  
@ 600 kHz  
15  
50  
58  
18  
51  
62  
Att EDGE Channel response attenuation  
dB  
Mode  
@ 200 kHz  
@ 400 kHz  
@ 600 kHz  
4
45  
52  
7
48  
55  
Tdelay  
Spurs  
Group delay variation  
Between 0 & 67.7 kHz  
1.8  
2.5  
us  
Spurious emission @ RF input  
@ 9 kHz 1 GHz  
@ 1 GHz 12 75 GHz  
dBm  
-57  
-47  
3/7  
STW3100  
3.2 Receive Section (continued)  
Vcc = 2.7V;  
Symbol  
GIQ  
Parameter  
Test Condition  
Min.  
-1  
Typ.  
Max.  
+1  
Unit  
dB  
I & Q Gain mismatch  
∆Φ IQ  
VCm  
I & Q quadrature mismatch  
Output Common mode voltage  
-5  
+5  
deg  
V
1.2  
1.35  
20  
1.5  
VSwing  
Maximum single ended Output 4Vpp mode  
Voltage  
0.75  
0.375  
Vpk  
2Vpp mode  
Voffset  
Toffset  
Differential Output  
OffsetVoltage  
after calibration  
-150  
+150  
200  
mV  
us  
Offset voltage calibration  
settling time (during the locking  
time phase)  
3.3 Transmit Section  
Vcc = 2.7V;  
Symbol  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Pins ITX(+), ITX(-), QTX(+) and QTX(-)  
Fmod  
Modulation frequency range  
3dB low pass  
cut-off frequency  
1
-
-
MHz  
VDC mod  
Vmod  
Input Common mode voltage  
Modulation level  
0.8  
0.8  
1
1
1.4  
1.2  
V
Single ended;  
Vpp  
peak to peak value  
VDC offset  
RIN  
Input DC offset permissible  
Dynamic input resistance  
Dynamic input capacitance  
Differential  
10  
-
mV  
kΩ  
pF  
Single ended  
Single ended  
differential  
10  
-
-
-
CIN  
20  
56  
RF Tx performances  
fTX2  
fTX3  
fTX4  
Zout  
Output frequency  
EGSM900  
GSM1800  
GSM1900  
Single-Ended  
880  
1710  
1850  
915  
1785  
1910  
MHz  
Output impedance  
50  
1.5  
+1  
VSWR_out Output VSWR into 50 ohm  
2
POUTGMSK Output power into 50 ohm load  
Set to Pout _0  
Set to Pout _1  
Low Band  
dBm  
+5  
ACPR400  
N20MHz  
ACPR @ 400 kHz offset  
(BW = 30 kHz)  
-65  
-63  
-164  
-156  
1.2  
-62  
-61  
dBc/  
BW  
High Band  
Low Band  
Output Phase Noise @ 20 MHz  
offset  
-159  
-152  
2.5  
dBc/  
Hz  
High Band  
RMS  
RMS phase error  
deg  
dBc  
nd  
H2LB  
-20  
2
3
Harmonic level  
Harmonic level  
rd  
H3LB  
-20  
dBc  
IMout  
Crej  
Unwanted sideband suppression  
Carrier rejection  
-45  
-40  
-35  
-32  
dBc  
dBc  
4/7  
STW3100  
3.4 Frequency generation Section  
Vcc = 2.7V;  
Symbol  
Parameter  
Test Condition  
φpeak < 20°  
Min.  
Typ.  
Max.  
Unit  
RF synthesizer  
Tlock_time  
Settling Time  
150  
200  
us  
EGSM900 Frequency Range  
DCS1800 Frequency Range  
DCS1900 Frequency Range  
Channel spacing  
880.2  
1710.2  
1850.2  
959.8  
1879.8  
1989.8  
MHz  
MHz  
MHz  
kHz  
ppm  
Fchannnel  
Fstep  
200  
Synthesizer frequency step  
(Fract-N PLL)  
0.0022  
DCXO  
Fref  
Reference Frequency (quartz  
input)  
26  
1
MHz  
Frange crystal Capacitor bank frequency range  
Fstep crystal Capacitor bank step  
-30  
-
+30  
-
ppm  
ppm  
5/7  
STW3100  
mm  
inch  
OUTLINE AND  
MECHANICAL DATA  
DIM.  
MIN.  
TYP. MAX. MIN.  
TYP. MAX.  
A
A1  
A2  
b
1.21  
0.15  
0.048  
0.006  
1.02  
0.040  
0.25  
6.85  
0.30  
7.00  
5.50  
7.00  
5.50  
0.50  
0.75  
0.35 0.010 0.012 0.014  
D
7.15 0.270 0.275 0.281  
D1  
E
0.216  
6.85  
7.15 0.270 0.275 0.281  
E1  
e
0.216  
0.020  
0.029  
Body: 7 x 7 x 1.4mm  
F
ddd  
eee  
fff  
0.08  
0.15  
0.05  
0.003  
0.006  
0.002  
LFBGA104  
Low Fine Ball Grid Array  
7578709 A  
6/7  
STW3100  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2004 STMicroelectronics - All rights reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States  
www.st.com  
7/7  

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