STV9212 [STMICROELECTRONICS]
Video Processor for CRT Monitors with PictureBooST; 视频处理器的CRT显示器与PictureBooST
| 型号： | STV9212 |
| 厂家： | 
ST |
| 描述： | Video Processor for CRT Monitors with PictureBooST |
| 文件： | 总34页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
STV9212
Video Processor for CRT Monitors with PictureBooST
Main Features
■ General
● I²C-Bus Controlled
● Supports AC- and DC-coupled applications
● 5V to 8V Power Supply
● Matches to virtually any video amplifier
■ PictureBooST
DIP24S:(Plastic Package)
● PictureBooST insertion input
● Full-screen PictureBooST via I²C-bus
● Context-sensitive Picture Enhancement
■ Video Clamping
ORDER CODE: STV9212
General Description
The STV9212 is an I²C-bus controlled color video
processor designed for standard CRT monitor
applications. It can drive systems where cathodes
are either AC- or DC-coupled to the amplifier
outputs. The three video channels provide contrast
and white balance separate gain adjustments as
well as one-per-channel DC cut-off control and
common DC offset control functions. On top of
these usual controls, it features context-sensitive
picture enhancement circuitry to support the
PictureBooST function that enhances the
appearance of still pictures and moving video.
● Input and Output Video Clamp
● Sync Pulse Polarity Auto-rectification
● Clamp Pulse Generation timed either by sync
or video blanking pulse
■ Video Processing
● Contrast Adjustment with excellent channel
matching
● Gain stages for control of white
● Two DC-mode cut-off ranges
● Output DC offset control
In AC coupling applications, the device can pilot
three cathode DC restore channels dedicated to set
CRT cut-off bias voltages and to control brightness
through cathodes.
● Automatic Beam Limiter (ABL)
● Video Insertion Pulse (VIP), 2 levels
● Amplifier Control (Blanking and Stand-by)
■ OSD Insertion with Contrast Control
■ Control Output
The RGB video outputs have a class A architecture
and directly drive the amplifier channels without
unnecessarily consuming current. Bandwidth
limitation I²C-bus adjustments can contribute to
keeping the application EMI under control.
● Amplifier Standby and Blanking Control
● 3 DAC for control of DC Restore Amplifier or
OSD (On-Screen Display) graphics are inserted by
means of a Fast Blanking signal. Independent OSD
contrast control facilitates adaptation to various
OSD generators and provides system flexibility.
Brightness in DC-coupled system
The STV9212 is perfectly compatible with other ST
components for CRT video boards, such as video
amplifiers and OSD generators.
October 2003
1/34
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
STV9212
Table of Contents
Chapter 1
STV9212 Pin Allocation and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pinout ..................................................................................................................................4
Pin Descriptions ..................................................................................................................4
1.1
1.2
Chapter 2
2.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Video RGB Input Clamp .......................................................................................................6
Video Blanking .....................................................................................................................8
Contrast Control Stage and Automatic Beam Limiter ..........................................................9
PictureBooST .....................................................................................................................10
OSD Insertion .....................................................................................................................11
Drive Stage ........................................................................................................................11
Video Insertion Pulse .........................................................................................................12
Output Stage ......................................................................................................................12
Output Infra-black Level, Cut-off and Brightness ...............................................................15
Signal Waveforms ..............................................................................................................18
Miscellaneous ....................................................................................................................18
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
Chapter 3
I²C-Bus Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.1
I²C-bus Register Descriptions ............................................................................................21
Chapter 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Absolute Maximum Ratings ...............................................................................................24
Thermal Data .....................................................................................................................24
Static Electrical Characteristics ..........................................................................................24
Dynamic Electrical Characteristics .....................................................................................25
I²C-Bus Electrical Characteristics .......................................................................................27
I²C-Bus Interface Timing Requirements ...........................................................................27
4.1
4.2
4.3
4.4
4.5
4.6
Chapter 5
Chapter 6
Chapter 7
Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Input/Output Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2/34
STV9212
Chapter 8
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3/34
STV9212 Pin Allocation and Description
STV9212
1
STV9212 Pin Allocation and Description
1.1
Pinout
Figure 1: STV9212 Pinout
IN1
HS
BLK
24
23
22
21
20
19
18
17
16
15
14
13
1
AMPCTL
OUT1
VCCP
OUT2
GNDP
OUT3
CO1
2
IN2
3
ABL
4
IN3
5
GNDA
VCCA
PB
6
7
8
OSD1
OSD2
OSD3
FBLK
CO2
9
CO3
10
11
12
SDA
SCL
1.2
Pin Descriptions
Table 1: STV9212 Pin Descriptions
Pin
Name
Function
Pin
Name
Function
I²C-bus Clock Input
I²C-bus Data Input/Output
1
2
IN1
HS
Video Input, Channel 1
13
14
15
16
17
18
19
20
21
22
23
24
SCL
SDA
Video Clamp Sync Input
Video Input, Channel 2
Automatic Beam Limiter Input
Video Input, Channel 3
Analog Ground
3
IN2
CO3
Cut-off / Brightness DAC 3 Output
Cut-off DAC 2 Output
4
ABL
CO2
5
IN3
CO1
Cut-off DAC 1 Output
6
GNDA
VCCA
PB
OUT3
GNDP
OUT2
VCCP
OUT1
AMPCTL
BLK
Video Output, Channel 3
Output Stage Ground
7
Analog Supply
8
Picture Boost Input
Video Output, Channel 2
Output Stage Supply
9
OSD1
OSD2
OSD3
FBLK
OSD Input, Channel 1
OSD Input, Channel 2
OSD Input, Channel 3
OSD Insertion Control Input
10
11
12
Video Output, Channel 1
Output for Amplifier Control
Blanking and Video Clamp Sync Input
4/34
STV9212
Functional Description
2
Functional Description
The functional blocks are described in the order they act on the signal.
Figure 2: STV9212 Block Diagram
5/34
Functional Description
STV9212
2.1
Video RGB Input Clamp
The three RGB inputs have to be supplied with a video signal through coupling capacitors playing
the role of analog memories for internal video clamps. The input clamping level is approximately 0V.
The clamp is gated by the Input Clamp Pulse (ICP) that is internally generated from a signal on
either the HS or BLK pin. The selection is done via register 8 of the I²C-bus. For more information,
refer to Figure 3: ICP, OCP and BLKI Generation and Table 2: ICP Timing.
Provided with an automatic polarity rectification function, the HS input accepts horizontal
synchronization signals of either polarity. The device can select either the leading or trailing edge of
this signal to trigger the ICP generator.
The BLK input is followed by an inverter stage that can be enabled or by-passed via the I²C-bus.
This allows the use of a signal of either polarity, the control software taking care of the inverter
position according to the signal applied. The BLKI signal found behind this inverter stage also drives
the video blanking circuitry which requires a positive BLKI polarity for correct operation. Once bit
BLKPOL has correctly been uploaded to ensure a positive BLKI polarity, the ICP triggering edge
can be selected via control bit BCEDGE. A horizontal flyback pulse is generally expected to be
applied on the BLK input. As the edges of horizontal flyback pulse can fall into the active video
content (outside the video signal line blanking portion), the application must ensure that such an
edge is never selected for triggering the ICP.
The width of the internally generated ICP is controlled via the I²C-bus. The HS input can be used to
pass a clamping pulse, if available in the application, directly to clamping stages, without any
additional processing. In this case, the appropriate polarity (positive) is required. See Table 2: ICP
Timing. The ICP timings triggered by the trailing edge of the BLK signal are not presented.
The Output Clamp Pulse (OCP) is described in Section 2.8: Output Stage.
Figure 3: ICP, OCP and BLKI Generation
ICP trig/pulse mode
BCSC1
(Sad08/b4)
ICP width
BCWDTH
(Sad08/b2,b3)
BCSC0
(Sad08/b0)
BCEDGE
(Sad08/b1)
ICP
(Internal)
0
1
0
1
0
1
Pulse
Generation
on
Automatic
Polarity
HS
2
-1
OCP
(Internal)
1
0
1
0
-1
Pulse
Generation
on
BLKI
BLK
24
BLKPOL
(Sad09/b0)
OCPSC
(Sad08/b7)
BLKI
(Internal)
Video blanking
I²C-bus field
Note: The I²C-bus switches are displayed in their default positions
6/34
STV9212
Functional Description
Table 2: ICP Timing
Trigger
Source
Trigger
Event
BCSC1
BCSC0 BCEDGE BLKPOL
Timing Diagram
negative
or
positive
HS
Trailing
edge
Don’t
care
0
0
0
ICP
0.33µs...1.33µs
negative
or
positive
HS
HS pin
BLK
0V
Leading
edge
Don’t
care
0
1
0
1
ICP
0.33µs...1.33µs
(must be positive!)
HS
Don’t
care
Don’t
care
Don’t
care
Pulse
ICP
BLK
0
1
0
1
0
1
1
0
Rising
edge
0
0
1
1
ICP
0.33µs...1.33µs
BLK
Falling
edge
ICP
0.33µs...1.33µs
Figure 4: Video Input Clamp
V
= Internal reference voltage (fixed)
Ref
Input video
V
Ref
0V
IN1
High
Impedance
stage
To further
processing
DC signal from
graphics card
(can vary)
1
ICP
0V
clamped to GND
Note: Identical for IN2 and IN3 inputs
7/34
Functional Description
STV9212
2.2
Video Blanking
The three video channels are simultaneously blanked with the high level of either BLKI or FBLK
signals. BLKI is an internal signal drawn from the signal applied on the BLK pin (H-flyback) as
shown in Figure 3. The blanking consists in forcing a “black” level to the internal clamped video
signal.
BLK Input
The BLK input receives an H-flyback pulse that drives:
● the video blanking circuitry during scan line retrace,
● the output clamping stage.
A clipping circuit at the input allows the direct use of a high-voltage H-flyback pulse applied through
a serial resistor as shown in Figure 5. A logic-level signal is also accepted but the serial resistor
remains mandatory. In all cases, the value of this resistor must be such that the sinking and
sourcing currents are limited to 1mA and 100µA, respectively.
Figure 5: BLK Input Pin
Typical
H-Flyback signal
40 to
100V
R
(*)
lim
GND
0 to -10V
BLK
24
Signal at BLK pin
(Pin 24)
~3V
GND
(*) R is necessary to limit currents flowing through BLK pin (-100uA, +1mA max.)
lim
Permanent Blanking
The entire TV screen can be blanked for an unlimited amount of time using the software blanking
feature. Both bits SWBLK and TST1 must be set to 1. The three video outputs are forced to their
infra-black levels as shown in Figure 6. Infra-black levels are defined in Section 2.9.
Figure 6: Software Blanking
Video output
channels 1,2,3
Normal operation
SWBLK=0, TST1=0
Black level
Software blanking in operation
SWBLK=1, TST1=1
Infra-black level
8/34
STV9212
Functional Description
The screen can also be blanked by permanently keeping the On-Screen Display FBLK input signal
at high level. In this case, only the video contents of the three video channels are replaced by “black
level” OSD content insertion (signals on pins OSD1 through OSD3 permanently at low level). Refer
to Section 2.5: OSD Insertion on page 11.
2.3
Contrast Control Stage and Automatic Beam Limiter
The contrast stages are simultaneously controlled on all three RGB channels with high attenuation
matching precision. Refer to electrical specifications for values. See Figure 7: Contrast Control and
Table 4: I²C-Bus Register Map.
Figure 7: Contrast Control
Before contrast stage
Video Black Level
V
V
Ref
CRST=max
CRST=mid
CRST=min
After contrast stage
Video Black Level
Ref
Note: CRST I²C-bus field acts equally on all 3 video channels
The Automatic Beam Limiter (ABL) is an attenuator controlled through the ABL input, independent
of contrast stage attenuation. The operating range is about 2 V (from 3 V to 1 V). A typical
characteristic is shown in Figure 8. Refer to Section 4: Electrical Specifications for specific values.
When not used, the ABL pin is to be connected to VCCA.
Figure 8: ABL Characteristics
Attenuation (dB)
0
-2
-4
-6
-8
-10
-12
-14
-16
0
1
2
3
4
5
V
(V)
ABL
9/34
Functional Description
STV9212
2.4
PictureBooST
The PictureBooST function provides a picture enhancement effect for images with photographic
or moving video contents.
The function is activated whenever the level on pin PB is high (TTL) or the bit PBINS is at 1, if the
general PictureBooST enable bit PBGEN is at 1. By means of PB input signal toggling, the
function can take effect in a part of the screen, e.g. a window, or on the whole screen.
The picture enhancement is achieved through combination of three actions, as shown in Figure 9:
● a content-sensitive peaking with slow restore (vivacity),
● a contrast addition,
● a brightness addition.
The vivacity amplitude depends on the slope height and steepness and on the status of bits
PBVIVAM[1:0]. The return to stabilized state is exponential with a time constant adjustable via bits
PBVIVTC[2:0]. Any undershoot below the video black level is clipped to a level close to black.
The PictureBooST brightness is a DC offset superimposed on the video signal in the boosted
zone. Its value is selected by bits PBBRIG[1:0]. The vivacity and PictureBooST brightness are
both enabled by bit PBVIVEN.
The PictureBooST contrast component evenly increases the video amplitude in the boosted zone.
Its value is controlled by bits PBCRST[1:0].
Refer to Section 4: Electrical Specifications for values.
Figure 9: PictureBooST Action
H-sync
Video before
PictureBooST
A
stage
PB input
V
viv
PB
contrast
τviv
Video after
PictureBooST
stage
A
PB brightness
clipping
10/34
STV9212
Functional Description
2.5
OSD Insertion
The On-Screen Display (OSD) is inserted with a high level on the FBLK input (TTL). The device
acts as follows:
● The three RGB video input signals (IN1, IN2, IN3) are internally blanked, i.e. put at the black
level.
● Binary levels (TTL) on inputs OSD1, OSD2 and OSD3, after processing in the OSD contrast
stage, are added to the corresponding blanked video channels.
In this way, the OSD contents replace the video contents where the FBLK input is high. See
Figure 2 and Figure 10.
The OSD is inserted after the PictureBooST block and before the Drive block. As a consequence,
OSD insertion overlaps all video contents, including the PictureBooST -ed zones. Color
temperature adjustments by means of the I²C-bus Drive registers act in the OSD insets.
The OSD contrast stage allows the adjustment of the level of OSD insets simultaneously on the
three OSD channels and independently of the video contrast adjustment. Refer to
Section 4: Electrical Specifications for values.
Figure 10: OSD Insertion
Video before
OSD insertion
Video Black Level
V
Ref
FBLK
OSD1(2,3)
max
mid
V
OSD
Video after
OSD insertion
Video Black Level
V
Ref
min.
OSDCRST
Note: The OSDCRST I²C-bus field acts equally on all 3 OSD channels.
2.6
Drive Stage
The Drive stage is a set of three attenuators separately controlled via three I²C-bus registers,
DRIVE1, DRIVE2 and DRIVE3. It affects all signals, ordinary video, PictureBooST processed
video and OSD insets. It is designed to compensate for differences in gain of the three CRT
cathodes. See Figure 11 and for values, refer to Section 4: Electrical Specifications.
11/34
Functional Description
STV9212
Figure 11: Drive Control
Before Drive Stage
Video Black Level
V
Ref
One I²C-bus register DRIVEx (x=1, 2 or 3)
DRIVEx=max
DRIVEx=mid
DRIVEx=min
per video channel
After Drive Stage
Video Black Level
V
Ref
2.7
Video Insertion Pulse
The Video Insertion Pulse (VIP) creates an indent on the three video signals, timed with the positive
part of the BLKI signal. (See Section 2.2: Video Blanking on page 8). As its level is below the video
black level, it introduces a video “infra-black” level. The video infra-black level position versus
ground is then controlled in subsequent stages. In the absence of the blanking pulse on pin BLK,
the VIP is not inserted and the subsequent stages control the position of video black level.
Figure 12 shows the signal before and after insertion of the VIP. Two different VIP values are
programmable by bit VIP. Refer to Section 4: Electrical Specifications for values.
Figure 12: VIP Insertion
Video before
VIP insertion
Video Black Level
V
Ref
BLKI signal
Video after
VIP insertion
Video Black Level
V
V
+V
VIP
Ref
Ref
V
VIP
Video Infra-black Level
Note: Identical for video channels 1, 2 and 3.
2.8
Output Stage
The output stage consists of an output clamp and a buffer. If a reduced output video amplitude and/
or a reduced infra-black level range is sufficient in the application, the VCCP can be lowered to 5V.
12/34
STV9212
Functional Description
Even at 8V of VCCP, care must be taken at device application level to ensure operation without
signal top limitation.
2.8.1 Output Clamp
The DC position of video infra-black and video black levels at the video outputs must be fixed
regardless of video or OSD inset contents, especially in applications where the device’s output
infra-black level determines directly the infra-black level on the CRT cathodes (DC-coupled
applications). This fixing is achieved by means of a fully-integrated output clamp that brings the
output video infra-black level (video black level, in absence of the BLK pulse) to the level of a
variable reference (Vib) as shown in Figure 13. The Vib is described in detail in Section 2.9 on
page 15. The clamp circuit is driven by the Output Clamp Pulse (OCP). For correct operation, this
pulse must entirely fall into the VIP pulse if this is present (clamp of infra-black level) or onto the
video black part (clamp of black level). In the former case, the OCP generator is to be triggered with
the leading edge of the BLK pulse, in the latter case it must copy the ICP pulse. Refer to Figure 3 for
the OCP generation block diagram. Table 3 shows possible OCP timings. Although possible, the
OCP timings, triggered by the BLK trailing edge, are not shown as they have no practical use.
2.8.2 Bandwidth Control
Controlled via bits BW[3:0], the output stage can limit the rise and fall time of the output signal. The
optimum choice for this adjustment is highly application dependent. Refer to Section 4: Electrical
Specifications for values and to Section 6: Application Hints for practical advice.
2.8.3 Output Buffer
The output buffer provides enough current so that external buffers are not required and the power
amplifier can interface directly to the device’s outputs.
Figure 13: Output Stage
OCP
15
22
VCCP
OUT1
BLKI
OCP
Video before
output stage
-
V
+
ib
V
Ref
GND
Clamp & Buffer
V
ib
Output
Infra-black Level
Note: Identical for video channels 2 and 3.
13/34
Functional Description
STV9212
Table 3: OCP Timing
OCPSC BLKPOL
Trigger
Source
Timing Diagram
Event
ICP
ICP
Pulse
1
Don’t care
OCP
BLK
Rising
edge
0
1
OCP
BLK
0
BLK
Falling
edge
OCP
14/34
STV9212
Functional Description
2.9
Output Infra-black Level, Cut-off and Brightness
The schematic diagram of these functions is shown in Figure 14.
Figure 14: Cut-off and Brightness Control Block Diagram
I²C-bus field
OUT1
OUT2
OUT3
V
V
ib
Ref
Output stage
V
1 for 3 channels
Video DC level
ib
V
ibmin
IBOF
DC
V
V
COmax
iblDC
MOD=1 MOD=0
IBLRG
range
range
1 per channel
DC:0
AC:1
MOD
IBL3
IBL2
IBL1
Cut-off
V
iblAC
V
briDC
V
CO
~40kΩ
V
iblAC
~0V*
AC:1
DC:0
CO1
CO2
CO3
BRIGRG
V
briAC
V
briAC
V
CO
1 for 3 channels
Brightness
V
V
briDC
COmin
range
V
COmin
BRIG
GND
Ch3 Ch1
Ch2
DC
Channel 3
Only
Note: Identical for CO1, CO2 and CO3 outputs except for “brightness” (V
The switches are drawn in their default positions.
* ~0V when the output is left open
) that is only output at CO3 while MOD=0.
briDC
2.9.1 Output Infra-black Level
The infra-black level of the video signal at the video outputs OUT1, OUT2 and OUT3 is positioned
to the Vib reference by the output clamp circuit, thus defining the Output infra-black level. If the
output clamp circuit is furnished with a correctly timed OCP (see corresponding sections), the
output infra-black level equals Vib. Vib is composed of a fixed DC voltage (Vibmin), a variable DC
voltage (Vibof) applied on all three channels and a per-channel variable DC voltage (Vibl (1,2,3)) as
shown in Figure 15. In AC-coupling mode (bit MOD = 1), the Vibl part is suppressed and the Vib is
therefore equal on all three channels, only varying with bits IBOF[5:0] acting on Vibof. This can be
used to match the device’s outputs to the input of the video amplifier used (biasing). In DC-coupling
mode (bit MOD = 0), Vibl (1,2,3) are separately set via bits IBL1[7:0], IBL2[7:0] and IBL3[7:0],
respectively. This serves to adjust the cut-off points of the three CRT cathodes. In this case, Vibof
can serve to pre-position the cut-off ranges in the factory adjustment procedure or/and to provide a
rough brightness control.
15/34
Functional Description
STV9212
Figure 15: Output Infra-black Level
19
22
20
18
GNDP
OUT1
OUT2
OUT3
black
infra-black
DC: differential cut-off
V (3)
AC: V (1,2,3) = 0V
ibl
ibl
V (1)
ibl
I²C: IBL1, IBL2, IBL3
V (3)
V (2)
ib
ibl
V (1)
ib
DC: common cut-off/brightness
AC: video amp. biasing
I²C: IBOF
V
V
V
ibof
V (2)
ibof
ibof
ib
fixed DC
V
V
V
ibmin
ibmin
ibmin
Channel 1
Channel 2
Channel 3
2.9.2 Cut-off and Brightness Control Outputs
Outputs CO1, CO2 and CO3 provide a DC voltage controlled via bits BRIG[7:0], IBLx[7:0],
IBLRG[7:0], BRIGRG[1:0] and MOD[7:0]. The principal of operation is shown in Figure 14.
When bit MOD is in position AC (= 1), the output voltage is a sum of the “brightness” VbriAC, “cut-off”
ViblAC and a fixed VCOmin providing a bottom limitation. The brightness adjustment is equally
applied to all three CO1, CO2 and CO3 outputs. It varies depending on bits BRIG[7:0] and
BRIGRG[1:0], with bits BRIGRG[1:0] controlling the range of BRIG adjustment. The cut-off
adjustment is separate for each channel, having one I²C-bus field per channel: IBL1, IBL2 and IBL3.
The ratio between the brightness and cut-off ranges depends on the brightness range selection.
See Figure 16.
Figure 16: CO1, CO2 and CO3 Outputs while MOD = 1
17
16
15
19
GNDP
CO1
CO2
CO3
V
(3)
cut-off
iblAC
V
V
(1)
iblAC
I²C: IBL1, IBL2, IBL3
V
(3)
V
(2)
CO
iblAC
V
(1)
CO
brightness through cathods
V
V
briAC
V
(2)
briAC
briAC
CO
I²C: BRIG
fixed DC
V
V
V
COmin
COmin
COmin
Channel 1
Channel 2
Channel 3
When bit MOD is in position DC (= 0), the output voltage on CO3 output is a sum of the “brightness”
VbriDC and a fixed VCOmin providing a pedestal. Outputs CO1 and CO2 are floating with internal
16/34
STV9212
Functional Description
resistors of approximately 40 kΩ to ground. The VbriDC varies with bits BRIG[7:0] and does not
depend on bits BRIGRG[1:0]. See Figure 17.
Figure 17: CO1, CO2 and CO3 Outputs while MOD = 0
19
17
16
15
GNDP
CO1
CO2
CO3
brightness through G1
V
(3)
V
CO
briDC
I²C: BRIG
fixed DC
V
COmin
Channel 1
Channel 2
Channel 3
Note: Channels 1 and 2 shown with CO1 and CO2 outputs left open
17/34
Functional Description
STV9212
2.10 Signal Waveforms
Figure 18 gives a summary of main signals waveforms.
Figure 18: Signal Waveforms
BLKI
HS
ICP
OCP
Video input
IN1 (2,3)
FBLK
OSD input
OSD1 (2,3)
Black-level
Video output
OUT1 (2,3)
Infra-black
level
2.11 Miscellaneous
2.11.1 Stand-by Mode
The device is set in Stand-by mode either by means of bit PASTBY or by lowering the VCCP supply
voltage below the VCCPS threshold. Once in Stand-by mode, the device does not process the video
signal and its power consumption is significantly reduced. The I²C-bus interface remains
operational. A low level is forced on the AMPCTL output. Refer to Section 4: Electrical
Specifications for values.
2.11.2 AMPCTL Output
The AMPCTL is designed to control a video power amplifier. It provides a three-level logical signal
that depends on bits ASTBY and ABLEN, as well as on the operating mode (stand-by / normal) of
the device. Figure 19 gives all possible states of the AMPCTL output. Refer to Section 4: Electrical
Specifications for electrical parameter values. Pin AMPCTL is of push-pull type. It must not directly
18/34
STV9212
Functional Description
be grounded in the application and it can be left floating. Only video amplifiers provided with an
appropriate control input can take advantage of the signal on the AMPCTL output.
Figure 19: AMPCTL Output States
BLKI signal
V
AMPHI
AMPCTL pin
signal
V
AMPBL
V
AMPSB
GND
ASTBY
PASTBY
ABLEN
X
1
1
X
X
0
0
1
0
0
0
X
X
X
I²C-bus
bits
X
V
>V
>V
>V
<V
STBTH
CCP
STBTH
STBTH
STBTH
Note: X stands for “don’t care” value
19/34
I²C-Bus Interface Specifications
STV9212
3
I²C-Bus Interface Specifications
The device is compatible to general I²C-bus specification. Its slave write address is DCh.
Subaddress (Sad) auto-incrementing is not available. Only Write mode is supported. The control
register map is given in Table 4.
Bold weight denotes default values assumed at power-on reset. The power-on reset is effected
every time that the supply voltage on VCCA pin drops below VPORTH threshold (Refer to electrical
specifications).
In order to ensure compatibility with future devices, all “Reserved” bits are to be set to 0 once
uploaded by the control software.
Table 4: I²C-Bus Register Map
Sad
01
b7
b6
b5
b4
b3
b2
b1
b0
CRST
Reserved
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BRIG
02
03
04
05
06
07
0
0
DRIVE1
Reserved
0
0
DRIVE2
Reserved
0
DRIVE3
0
0
Reserved
0
Reserved
BRIGRG
0
1
Reserved
OSDCRST
0
0
0
1
OCPTG
TST1
TST0
BCSC1
BCWDTH
BCEDGE
BCSC0
08
09
0:BLK
1:ICP
ASTBY
0:Normal
1:Test
0:Normal
1:Test
0:Trig mode
1:HS pulse
0:Rising
1:Falling
0:HS trig
1:BLK trig
0
1
ABLEN
Reserved
TST2
Reserved
MOD
SWBLK
BLKPOL
0:Normal
1:Standby
0:Bl. disable
1:Bl. enable
0:Test
1:Normal
0:DC
1:AC
0:Disable
1:Enable
0:Non-inv.
1:Inverted
0
0
IBL1
0A
0B
0C
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IBL2
IBL3
1
0
0
0
PASTBY
Reserved
TST4
TST3
BW
0D
0E
0F
10
0:Normal
1:Standby
0:Normal
1:Test
0:Normal
1:Test
0
1
0
0
0
0
0
0
0
VIP
IBOF
IBLRG
0:0.2V
1:0.4V
0:Wide
1:Narrow
1
0
Reserved
0
0
0
1
1
PBGEN
PBINS
PBCRST
Reserved
PBBRIG
0:Disable
1:Enable
0:PB Pin
1:Perman.
0
0
PBVIVTC
0
1
Reserved
0
PBVIVEN
PBVIVAM
Reserved
0:Disable
1:Enable
0
1
0
20/34
STV9212
I²C-Bus Interface Specifications
3.1
I²C-bus Register Descriptions
Sad01
Bit 0 = Reserved
Read/Write
Reset Value: 1000 0000 (80h)
Sad05
7
0
Read/Write
Reset Value: 1000 0000 (80h)
CRST[6:0]
Values 00 and 7Fh in field CRST[6:0] are
prohibited.
Bits[7:1] = Contrast Adjustment (CRST)
Bit 0 = Reserved
7
0
DRIVE3[6:0]
Values 00 and 7Fh in field DRIVE3[6:0] are
prohibited.
Bits[7:1] = Gain Adjustment on Channel 3
(DRIVE3)
Sad02
Bit 0 = Reserved.
Read/Write
Reset Value: 1000 0000 (80h)
Sad06
7
0
BRIG[7:0]
Read/Write
Reset Value: 0000 0001 (01h)
Bits[7:0] = Brightness Adjustment (BRIG)
In AC mode, this value is added to infra-
black levels and output on pins CO1, CO2
and CO3.
7
0
BRIGRG
[1:0]
In DC mode, it is output all alone on pin
CO3.
Bits[7:2] = Reserved.
Bits[1:0]= Brightness Adjustment Range (BRIGRG)
Four positions. See Section 4.4: Dynamic
Electrical Characteristics.
Sad03
Read/Write
Reset Value: 1000 0000 (80h)
Sad07
7
0
Read/Write
DRIVE1[6:0]
Reset Value: 0000 1001 (09h)
Values 00 and 7Fh in field DRIVE1[6:0] are
prohibited.
7
0
OSDCRST[3:0]
Bits[7:1] = Gain Adjustment on Channel 1
(DRIVE1)
Bit 0 = Reserved
Bits[7:4] = Reserved.
Bits[3:0]= OSD Contrast Adjustment
Sad08
Sad04
Read/Write
Read/Write
Reset Value: 0000 0100 (04h)
Reset Value: 1000 0000 (80h)
7
0
7
0
OCPT
G
BCSC
1
BCED BCSC
DRIVE2[6:0]
TST[1:0]
BCWDTH[1:0]
GE
0
Values 00 and 7Fh in field DRIVE2[6:0] are
prohibited.
Bits[7:1] = Gain Adjustment on Channel 2
(DRIVE2)
Bit 7 = Output clamping pulse selection
0: Pulse triggered by BLK input (default)
1: Internal ICP pulse
21/34
I²C-Bus Interface Specifications
STV9212
Bits[6:5] = Test mode activation for device testing in
fabrication. When performing software
blanking through SWBLK bit, TST1 bit
must be set to 1.
0: Test mode
1: Normal operation mode (Default)
Bit 3 = Reserved.
Bit 2 = Application mode selection.
0: Application with DC-coupled cathodes.
0: Normal operation mode (Default)
1: Test mode
(Default)
Bits[4,0] = Blanking and clamping pulse source.
1: Application with AC-coupled cathodes.
Bit 1 = Permanent blanking of video channels
through software.
BCSC1
BCSC0
Selected Source
0
0
1
0
1
HS pin trigger (Default)
BLK pin trigger
0: Disable, blanking gated with signal on
BLK pin. (Default)
1: Permanent blanking. Bit TST1 must
also be set to 1.
Don’t care
HS pin pulse
Bits[3:2] = Width of ICP pulse when bit BCSC1 is 0.
Bit 0 = Blanking signal (H-fly back) polarity
inversion. For correct operation, the
internal BLKI pulse after this controlled
inversion must be positive.
BCWDTH
BCPC Width
0
0
1
0
1
0.33 µs
0.66 µs (Default)
1 µs
0
1
1
0: Non Inverted, good for positive blanking
pulse (Default)
1.33 µs
1: Inverted, good for negative blanking
pulse
Bit 1 = When HS pin is selected to trigger the ICP
pulse generator.
0: Trailing edge of HS pulse (Default)
1: Leading edge of HS pulse
Sad0A, Sad0B and Sad0C
When BLK pin is selected to trigger the ICP pulse
generator:
Read/Write
Reset Value: 1000 0000 (80h)
BCEDGE BLKPOL
Trigger on BLK
7
0
0
0
1
1
0
1
0
1
Rising edge (default)
Falling edge
IBL1[7:0]
IBL2[7:0]
IBL3[7:0]
Falling edge
Rising edge
Bits[7:0] = Infra-black (Cut-off) Level Control,
Channels 1 to 3 (IBLx)
Refer to BLKPOL bit description.
In DC-coupling mode, the register controls
the pedestal of corresponding video
channel signal.
In AC-coupling mode, the register controls
the level on outputs CO1, CO2 or CO3,
respectively.
Sad09
Read/Write
Reset Value: 0001 0000 (10h)
7
0
ASTB ABLE
TST2
SWBL BLKP
MOD
Sad0D
Y
N
K
OL
Read/Write
Reset Value: 0000 1000 (08h)
Bit 7 = Amplifier standby selection.
0: Normal (default)
1: Standby
7
0
Bit 6 = Amplifier blanking enable. The bit is “don’t
care” whenever bit ASTBY is in Standby
position.
0: Blanking pulse not generated (default)
1: Blanking pulse generated
Bit 5 = Reserved.
PAST
TST[4:3]
BY
BW[3:0]
Bit 7 = Preamplifier and Amplifier STandBY
selection
0: Normal (default)
1: Standby
Bit 6 = Reserved.
Bit 4 = Test mode activation for device testing in
fabrication.
22/34
STV9212
I²C-Bus Interface Specifications
Bits[5:4] = Test mode activation bits for device
testing in fabrication.
0: Normal operation mode (Default)
1: Test mode
Bits[3:0] = Internal band width limitation control.
Refer to electrical characteristics.
Bit 7 = PictureBooST General Enable. (PBGEN)
0: Disable, function inhibited (Default)
1: Enable, function active
Bit 6 = PictureBooST Insertion Control. (PBINS)
0: PB pin insertion (Default)
1: Permanent insertion regardless of
signal on PB pin
Bit 5 = Reserved.
Bits[4:3] = PictureBooST Contrast Control
(PBCRST)
Bit 2 = Reserved.
Bits[1:0] = PictureBooST Brightness Control
(PBBRIG)
Sad0E
Read/Write
Reset Value: 1100 0001 (C1h)
7
0
IBLR
G
VIP
IBOF[5:0]
Sad10
Bit 7 = Video Insertion Pulse depth.
0: 0.2V
Read/Write
Reset Value: 0010 1000 (28h)
1: 0.4V (default)
Bits[6:1] = Infra-black level offset control
simultaneously on all three video
channels.
7
0
PBVIV
EN
PBVIVAM[1:0]
PBVIVTC[2:0]
Bit 0 = Control range of infra-black level
adjustments via IBL1, IBL2 and IBL3
registers. Acts either on video signal
Bit 7 = PictureBooST vivacity and brightness
enable.
channels or CO1, CO2, CO3 outputs.
Refer to electrical characteristics.
0: Wide
0: Disable (default)
1: Enable
Bits[6:5] = PictureBooST Vivacity Amplitude
Control.
1: Narrow (default)
Bit 4 = Reserved.
Bits[3:1] = PictureBooST Vivacity Time Constant
Control.
Sad0F
Bit 0 = Reserved.
Read/Write
Reset Value: 0000 1001 (09h)
7
0
PBGE PBIN
PBCRST[1:0]
PBBRIG[1:0]
N
S
23/34
Electrical Specifications
STV9212
4
Electrical Specifications
4.1
Absolute Maximum Ratings
All voltages refer to the GNDA pin.
Symbol
Parameter
Supply voltage on VCCA (Pin 7)
Min.
Max.
Units
V
V
TBD
TBD
TBD
TBD
5.5
8.8
5.5
1.4
V
V
V
V
CCA
CCP
Supply voltage on VCCP (Pin 21)
V
Voltage at any pin except video inputs and supply pins
Voltage at video inputs (Pins 1,3 and 5)
IN
V
I
ESD susceptibility
Human Body Model (100 pF discharge through 1.5 kΩ)
V
TBD
±2
kV
ESD
STG
T
Storage Temperature
-40
-40
+150
+150
°C
°C
T
Operating Junction Temperature
OPER
4.2
4.3
Thermal Data
Symbol
Parameter
Min.
Typ.
Max.
Units
R
Junction-to-Ambient Thermal Resistance
Operating Ambient Temperature
60
°C/W
°C/W
thJA
T
0
70
AMB
Static Electrical Characteristics
TAMB = 25°C, VCCA = 5V, and VCCP = 8V, unless otherwise specified. All voltages refer to the GNDA
pin.
Symbol
Supply
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
V
Supply Voltage
Pin 7
4.5
4.5
5
8
5.5
8.8
V
V
CCA
CCP
Power Stage Supply Voltage
Pin 21
Pin 21
Power Supply Voltage Stand-by
Threshold
V
2.5
3.0
3.5
V
CCPS
V
V
= 5V (PBGEN Disable)
65
85
mA
mA
CCA
CCA
I
VCCA Supply Current
CCA
CCP
= 5V (PBGEN Enable)
I
V
= 8V
VCCP Supply Current
50
mA
mA
CCP
I
Total Supply Current in Stand-by Mode
Pin 21 and pin 7
6
1
S
Inputs and Outputs
V
Video Input voltage amplitude
Output voltage swing
0.7
V
V
I
V
CCP
1
( )
V
O
IL
0.5
-0.5V
V
V
Low level input voltage (TTL)
High level input voltage (TTL)
BLK input current
OSD, FBLK, PB, HS,BLK
OSD, FBLK, PB, HS,BLK
BLK
0.8
V
V
2.4
IH
IL
I
I
-0.1
-1
+1.0
1
mA
µA
Input current
OSD, FBLK, PB
IN
24/34
STV9212
Electrical Specifications
Symbol
Parameter
Input resistance
Test Conditions
Min.
Typ.
Max.
Units
R
HS
I²C-bus bit ASTBY = 1 or/and
40
kΩ
HS
Output voltage at AMPCTL pin, standby
(Figure 18)
V
V
< V
80
1.6
3.1
200
mV
V
AMPSB
CCP CCPS
Sink current 200µA
I²C-bus bit ASTBY = 1
I²C-bus bit ABLEN = 1
Sink current 0µA
Output voltage at AMPCTL pin,
blanking (Figure 18)
V
TBD
TBD
AMPBL
BLKI at high level
I²C-bus bit ASTBY = 0 and
Output voltage at AMPCTL pin, no
standby, no blanking (Figure 18)
V
V
> V
V
AMPHI
CCP CCPS
Sink current 0µA
4.4
Dynamic Electrical Characteristics
TAMB = 25°C, VCCA = 5 V, VCCP = 8 V, Vi = 0.7 VPP, CLOAD = 5 pF, RS = 100 Ω serial resistor
between output pin and CLOAD, unless otherwise specified. “x” denotes channel number and can
assume values of 1, 2 and/or 3. All voltages refer to the GNDA pin.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Video Output Signal (Pins 18, 20 and 22) - Contrast and Drive
I²C-bus fields CRST = 7Eh,
DRIVEx = 7Eh
PBGEN = 0
Maximum total gain for video path
with PictureBooST off
G
12
dB
I²C-bus fields CRST = 7Eh,
DRIVEx = 7Eh
PBGEN = 0
2
( )
V
OM
ON
Maximum video output voltage
2.8
4.0
V
V
PBGEN = 1
I²C-bus fields CRST = 40h,
DRIVEx = 40h (POR state)
V
Nominal video output voltage
Contrast control range
Drive control range
TBD
28
V
Max. to min. contrast (CRST = 7Eh
to CRST = 01h)
CAR
DAR
GM
dB
dB
dB
Max. to min. drive (DRIVEx = 7Eh to
DRIVEx = 01h)
13
I²C-bus fields CRST = 40h,
DRIVEx = 40h (POR state)
3
( )
±0.1
Gain matching
Video Output Signal - OSD
referenced to output black level
DRIVEx = 7Eh
OSDCRST = 0Fh
V
OSD insertion output level
OSD
4.9
0
V
V
OSDCRST = 0h
Video Output Signal - VIP
From Infrablack level to black level
VIP = 1
V
Video Insertion Pulse level
0.4
0.2
Vpp
Vpp
VIP
4
( )
VIP = 0
Video Output Signal - Infra Black Level (Figure 15)
V
Infra black level pedestal
0.4
V
ibmin
IBOF = 3Fh
IBOF = 0h
2.1
0
V
V
V
Infra black offset component
ibof
IBLx = 0h or MOD = 1 (AC mode)
IBLx = FFh, MOD = 0 (DC mode)
IBLRG = 1
0
V
V [x]
Infra black level component
ibl
1.3
1.8
V
V
IBLRG = 0
25/34
Electrical Specifications
STV9212
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Cut-off Output (Pins CO1, CO2 and CO3)
V
Pedestal level on COx outputs
Upper limitation on COx outputs
0.5
V
V
COmin
Sum of V
+V
or V
V
CCA
briAC
iblAC
briDC
V
COmax
exceeding the limit
-0.5V
MOD = 1 (AC mode)
BRIG = 0h
0
V
BRIG = FFh:
Brightness component in AC mode
(Figure 16)
V
BRIGRG = 00b
BRIGRG = 01b
BRIGRG = 10b
BRIGRG = 11b
0.4
0.8
1.25
1.9
V
V
V
V
briAC
briDC
MOD = 0 (DC mode)
BRIG = 0h
BRIG = FFh
Brightness component in DC mode
V
0
4
V
V
6
( )
on CO3 pin
(Figure 17)
MOD = 0 (DC mode)
MOD = 1 (AC mode)
IBLx = 0h
0
0
V
V
V
(x)
Cut-off component
iblAC
IBLx = FFh:
IBLRG = 0
IBLRG = 1
3.7
1.85
V
V
PictureBooST Block (Figure 9)
PBGEN = 1
PBCRST = 00b
PBCRST = 01b
PBCRST = 10b
PBCRST = 11b
0.8
1.6
2.3
3
dB
dB
dB
dB
G
Maximum gain
PB
PBGEN = 1 and PBVIVEN = 1
PBBRIG = 00b
PBBRIG = 01b
PBBRIG = 10b
PBBRIG = 11b
64
48
32
16
mV
mV
mV
mV
PictureBooST brightness expressed
in equivalent input level
V
BriPB
PBGEN = 1 and PBVIVEN = 1
PBVIVAM = 00b
PBVIVAM = 01b
PBVIVAM = 10b
PBVIVAM = 11b
Vivacity amplitude as percentage of
its host square pulse level before
PictureBooST(“A” in Figure 9)
12.5
25
37.5
50
%
%
%
%
V
/A
viv
PBGEN = 1 and PBVIVEN = 1
PBVIVTC = 000b
PBVIVTC = 001b
0
35
245
ns
ns
ns
τviv
Vivacity time constant
PBVIVTC = 111b
ABL (Figure 9)
V
>3.2 V
= 1 V
0
-15
dB
dB
ABL
G
ABL gain
ABL
V
ABL
V
ABL threshold voltage
ABL input current
3
V
ThABL
V
= 3.2V
= 1V
0
-2
µA
µA
ABL
I
ABL
V
ABL
Video Output Signal - Dynamic Performances (Figure 15)
= 2V (VIP exclusive)
V
OUT
PP
5
( )
t , t
3.5
7
ns
ns
BW = 0Fh
BW = 00h
r
f
Rise Time, Fall Time
V
= 2V , sinus wave, -3dB
PP
OUT
BW
Large signal bandwidth
TBD
TBD
MHz
MHz
BW = 0Fh
BW = 00h
26/34
STV9212
Symbol
CT
Electrical Specifications
Parameter
Test Conditions
= 2V
Min.
Typ.
Max.
Units
V
OUT
PP
Crosstalk between Video Outputs
TBD
TBD
dB
dB
f = 10 MHz
f = 50 MHz
4.5
I²C-Bus Electrical Characteristics
Tamb = 25° C, VCCA = 5 V, VCCP = 8 V, Vi = 0.7 VPP, CLOAD = 5 pF
Unit
s
Symbol
Parameter
Test Conditions
On Pins SDA, SCL
Min.
Typ.
Max.
V
V
Low Level Input Voltage
1.5
V
V
IL
High Level Input Voltage
3
IH
IN
I
0.4 V < V < 4.5 V
Input Current (Pins SDA, SCL)
SCL Maximum Clock Frequency
-10
+10
µA
kHz
IN
f
200
SCL(Max.)
SDA pin when ACK Sink Current =
6 mA
V
Low Level Output Voltage
0.6
V
OL
4.6
I²C-Bus Interface Timing Requirements
Symbol
Parameter
Min.
Typ.
Max.
Units
t
t
Time the bus must be free between two accesses
Hold Time for Start Condition
Set-up Time for Stop Condition
The Low Period of Clock
1300
600
ns
ns
ns
ns
ns
ns
ns
µs
ns
BUF
HDS
t
600
SUP
t
1300
600
LOW
t
t
The High Period of Clock
HIGH
Hold Time Data
300
HDAT
t
Set-up Time Data
250
SUDAT
t
Rise Time of both SDA and SCL
Fall Time of both SDA and SCL
1
r
t
300
f
Figure 20: I²C-Bus Timing Diagram
t
BUF
t
HDAT
SDA
SCL
t
t
t
SUP
HDS
SUDAT
t
LOW
t
HIGH
Notes on Electrical Characteristics
Note 1. The video on the preamplifier output must remain above 0.5V even for high frequency signals.
2. Assuming that the video output signal remains inside the linear area of the preamplifier output
(between 0.5V and VCCP - 0.5V).
27/34
Electrical Specifications
STV9212
3. Matching measured between the different outputs.
4. When the Blanking signal is present on the BLK input, the VIP insertion pulse is always generated.
Only its amplitude changes (see Figure 12).
5. tR, tF are simulated values, assuming an ideal input signal with rise/fall time = 0.1 ns. Measured
between 10% and 90% of the pulse height.
6. When MOD = 0, the CO1 and CO2 are internally grounded through resistors.
28/34
STV9212
Soldering Information
5
Soldering Information
The device can be soldered by wave, dipping or manually. Wave soldering is the preferred method
for mounting through-hole mount IC packages on a printed-circuit board.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not
be in contact with the joints for more than 5 seconds.The total contact time of successive solder
waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the
temperature of the plastic body must not exceed the specified maximum storage temperature
(TSTG[max]). If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane
or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may
remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact
may last up to 5 seconds.
29/34
Package Mechanical Data
STV9212
6
Package Mechanical Data
Figure 21: 24-Pin Plastic Dual In-Line Package, Shrink 300-mil Width
E
E1
A2
A1
A
L
Stand-off
0.015 in.
b
b2
e
eA
eB
c
D
E
24
1
13
12
0.015 in.
0.38 mm.
Gage Plane
E1
eC
eB
Table 5: Package Dimensions
Millimeters
Typ.
Inches
Dim.
Min.
Max.
Min.
Typ.
Max.
A
A1
A2
b
5.08
0.200
0.51
3.05
0.38
0.89
0.23
22.35
7.62
6.10
0.020
0.120
0.015
0.035
0.009
0.880
0.300
0.240
3.30
0.46
1.02
0.25
22.61
4.57
0.56
1.14
0.38
22.86
8.64
6.86
0.130
0.018
0.040
0.010
0.890
0.180
0.022
0.045
0.015
0.900
0.340
0.270
b2
c
D
E
E1
e
6.40
1.78
7.62
0.252
0.070
0.300
eA
eB
eC
L
10.92
1.52
3.81
0.430
0.060
0.150
0.00
2.54
0.000
0.100
3.30
0.130
Number of Pins
24
N
30/34
STV9212
Input/Output Diagrams
7
Input/Output Diagrams
Figure 22: Video Inputs
Figure 25: Hsync Input
V
V
CCA
CCA
30k
2
HIGH
IMPEDANCE
IN1
1
GNDA
GNDA
GNDL
Idem for pads IN2 (3) and IN3 (5)
Figure 23: ABL Input
Figure 26: PictureBooST and OSD Inputs
V
CCA
V
CCA
OSD1
9
1k
4
ABL
GNDA
GNDL
GNDA
Idem for pads OSD2 (10), OSD3 (11)
PB (8), FBLK (12)
Figure 24: Amplifier Control Output
Figure 27: Analog Supplies
V
CCA
7
V
CCA
(8V)
LOGIC
PART
100
23
AMPCTL
GNDA
GNDA
6
31/34
Input/Output Diagrams
STV9212
Figure 28: I²C-Bus
Figure 31: Output Stage Ground
(8V)
30kΩ
SCL
SDA
13
14
V
CCA
4pF
GNDL
GNDL
GNDA
19
GNDP
30kΩ
GNDA
4pF
GNDA
Figure 29: Output Stage Supply and Video Outputs
Figure 32: Cut-off DAC Output Pins
V
CCA
V
CCP 19
(20V)
22
OUT1
17
CO1
GNDA
GNDA
Idem for pads CO2 (16) and CO3 (15)
GNDP
Idem for pads OUT2 (20) and OUT3 (18)
Figure 30: Blanking / Video Clamping Sync Inputs
V
CCA
24
BLK
GNDL
GNDA
32/34
STV9212
Revision History
8
Revision History
Table 6: Summary of Modifications
Description
Version
Date
1.0
1.1
14 Nov 2002
03 Jul 2003
First Issue
Minor modifications.
33/34
STV9212
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces
all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
34/34
相关型号：
STV9302
VERTICAL DEFLECTION OUTPUT FOR MONITOR / TV 2 App / 60 V WITH FLYBACK GENERATOR
STMICROELECTR
STV9302A
VERTICAL DEFLECTION OUTPUT FOR MONITOR / TV 2 App / 60 V WITH FLYBACK GENERATOR
STMICROELECTR
STV9306
BUS CONTROLLED VERTICAL DEFLECTION SYSTEM WITH EAST/WEST CORRECTION OUTPUT CIRCUIT
STMICROELECTR
STV9306A
Bus-Controlled Vertical Deflection System with East/West Correction Output Circuit
STMICROELECTR
STV9306B
Bus-Controlled Vertical Deflection System with East/West Correction Output Circuit
STMICROELECTR
STV9325
Vertical Deflection Booster for 2.5-APPTV/Monitor Applications with 70-V Flyback Generator
STMICROELECTR
STV9326
Vertical Deflection Booster for 3-APPTV/Monitor Applications with 60-V Flyback Generator
STMICROELECTR
©2020 ICPDF网 联系我们和版权申明