STM32F038K6_技术文档

STM32F038x6

ARM^®-based 32-bit MCU with 32 Kbyte Flash, 9 timers,

ADC and communication interfaces, 1.8 V

Datasheet - production data

Features

®

• Core: ARM 32-bit Cortex -M0 CPU,

frequency up to 48 MHz

LQFP48 7x7 mm UFQFPN32 5x5 mm WLCSP25

TSSOP20

• Memories

2.1x2.1 mm 6.5x4.4 mm

UFQFPN28 4x4 mm

– 32 Kbytes of Flash memory

– 1 x 16-bit timer with 1 IC/OC

– 4 Kbytes of SRAM with HW parity

– Independent and system watchdog timers

– SysTick timer: 24-bit downcounter

• CRC calculation unit

• Power management

• Calendar RTC with alarm and periodic wakeup

– Digital and I/Os supply: V = 1.8 V ±8%

from Stop

DD

– Analog supply: V

= from V to 3.6 V

DDA

DD

• Communication interfaces

2

– Low power modes: Sleep, Stop

– V supply for RTC and backup registers

– 1 x I C interface, supporting Fast Mode

Plus (1 Mbit/s) with extra current sink,

SMBus/PMBus, and wakeup from Stop

mode

BAT

• Clock management

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x6 PLL option

– Internal 40 kHz RC oscillator

– 1 x USART supporting master synchronous

SPI and modem control, ISO7816

interface, LIN, IrDA capability, auto baud

rate detection and wakeup feature

• Up to 38 fast I/Os

– 1 x SPI (18 Mbit/s) with 4 to 16

2

programmable bit frames, with I S interface

– All mappable on external interrupt vectors

multiplexed

– Up to 25 I/Os with 5 V tolerant capability

• Serial wire debug (SWD)

• 96-bit unique ID

• 5-channel DMA controller

• 1 × 12-bit, 1.0 µs ADC (up to 10 channels)

• Extended temperature range: -40 to +105°C

– Conversion range: 0 to 3.6V

®

– Separate analog supply from 2.4 up to

3.6 V

• All packages ECOPACK 2

Table 1. Device summary

• Up to 9 timers

– 1 x 16-bit 7-channel advanced-control timer

for 6 channels PWM output, with deadtime

generation and emergency stop

Reference

Part number

STM32F038C6, STM32F038E6,

STM32F038x6 STM32F038F6, STM32F038G6,

STM32F038K6

– 1 x 32-bit and 1 x 16-bit timer, with up to 4

IC/OC, usable for IR control decoding

– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,

deadtime generation and emergency stop

– 1 x 16-bit timer, with IC/OC and OCN,

deadtime generation, emergency stop and

modulator gate for IR control

May 2017

DocID026079 Rev 5

1/102

This is information on a product in full production.

www.st.com

Contents

STM32F038x6

Contents

1

2

3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

3.2

3.3

3.4

3.5

ARM^®-Cortex^®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 12

Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.5.1

3.5.2

3.5.3

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6

3.7

3.8

3.9

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 14

Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.9.1

3.9.2

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15

Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 15

3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.10.2 Internal voltage reference (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REFINT

3.10.3

V

battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

BAT

3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.11.1

3.11.2

3.11.3

3.11.4

3.11.5

Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

General-purpose timers (TIM2, 3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . 17

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.12 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19

3.13 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.14 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 20

3.15 Serial peripheral interface (SPI) / Inter-integrated sound interface (I²S) . 21

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Contents

3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4

5

6

6.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2

6.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 41

Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3.14 NRST and NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3.17

V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

BAT

6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3.19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

DocID026079 Rev 5

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4

Contents

STM32F038x6

7

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.1

7.2

7.3

7.4

7.5

7.6

LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.6.1

7.6.2

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 96

8

9

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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STM32F038x6

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

STM32F038x6 family device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . 9

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2

Comparison of I C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2

STM32F038x6 I C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

STM32F038x6 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STM32F038x6 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 31

Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 32

Peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Typical and maximum current consumption from V supply at VDD = 1.8 V . . . . . . . . . 44

DD

Typical and maximum current consumption from the V

supply . . . . . . . . . . . . . . . . . 45

DDA

Typical and maximum consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Typical and maximum current consumption from the V supply. . . . . . . . . . . . . . . . . . . 46

BAT

Typical current consumption, code executing from Flash memory,

running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

LSE oscillator characteristics (f

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

LSE

HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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6

List of tables

STM32F038x6

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

R

max for f

= 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

AIN

ADC

ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

V

monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

BAT

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2

I C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2

I S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

WLCSP25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

WLCSP25 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

TSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6/102

DocID026079 Rev 5

STM32F038x6

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

LQFP48 package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

UFQFPN32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

UFQFPN28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

WLCSP25 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TSSOP20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

STM32F038x6 memory map

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 11. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 13. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 14. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 15. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 17. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 57

Figure 18. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 19. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 20. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 21. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 23. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 25. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 26. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 27. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2

Figure 28. I S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2

Figure 29. I S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 30. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 31. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 32. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 33. UFQFPN32 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 34. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 35. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 36. UFQFPN28 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 37. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 38. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 39. WLCSP25 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 40. Recommended footprint for WLCSP25 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 41. WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 42. TSSOP20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 43. Recommended footprint for TSSOP20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 44. TSSOP20 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

DocID026079 Rev 5

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7

Introduction

STM32F038x6

1

Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F038x6 microcontrollers.

This document should be read in conjunction with the STM32F0xxxx reference manual

(RM0091). The reference manual is available from the STMicroelectronics website

www.st.com.

®

For information on the ARM Cortex -M0 core, please refer to the Cortex -M0 Technical

Reference Manual, available from the www.arm.com website.

8/102

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STM32F038x6

Description

2

Description

®

The STM32F038x6 microcontrollers incorporate the high-performance ARM Cortex -M0

32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories

(32 Kbytes of Flash memory and 4 Kbytes of SRAM), and an extensive range of enhanced

2

peripherals and I/Os. All devices offer standard communication interfaces (one I C, one

2

SPI/ I S and one USART), one 12-bit ADC, five 16-bit timers, one 32-bit timer and an

advanced-control PWM timer.

The STM32F038x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C

temperature ranges at a 1.8 V ± 8% power supply. A comprehensive set of power-saving

modes allows the design of low-power applications.

The STM32F038x6 microcontrollers include devices in five different packages ranging from

20 pins to 48 pins with a die form also available upon request. Depending on the device

chosen, different sets of peripherals are included.

These features make the STM32F038x6 microcontrollers suitable for a wide range of

applications such as application control and user interfaces, hand-held equipment, A/V

receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,

PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.

Table 2. STM32F038x6 family device features and peripheral counts

Peripheral

STM32F038Fx STM32F038Ex STM32F038Gx

STM32F038Kx

STM32F038Cx

Flash memory (Kbyte)

SRAM (Kbyte)

Advanced

32

4

1 (16-bit)

control

Timers

4 (16-bit)

1 (32-bit)

General

purpose

SPI [I²S]⁽¹⁾

Comm.

I²C

1 [1]

1

interfaces

USART

1

12-bit ADC

1

(number of channels)

GPIOs

(8 ext. + 3 int.)

(9 ext. + 3 int.)

(10 ext. + 3 int.)

14

19

22

48 MHz

V_DD= 1.8 V ± 8%, V_DDA= from V_DDto 3.6 V

26

38

Max. CPU frequency

Operating voltage

Ambient operating temperature: -40°C to 85°C / -40°C to 105°C

Junction temperature: -40°C to 105°C / -40°C to 125°C

Operating temperature

Packages

TSSOP20

WLCSP25

UFQFPN28

UFQFPN32

LQFP48

1. The SPI interface can be used either in SPI mode or in I²S audio mode.

DocID026079 Rev 5

9/102

22

Description

STM32F038x6

Figure 1. Block diagram

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10/102

DocID026079 Rev 5

STM32F038x6

Functional overview

3

Functional overview

Figure 1 shows the general block diagram of the STM32F038x6 devices.

3.1

ARM^®-Cortex^®-M0 core

®

The ARM Cortex -M0 is a generation of ARM 32-bit RISC processors for embedded

systems. It has been developed to provide a low-cost platform that meets the needs of MCU

implementation, with a reduced pin count and low-power consumption, while delivering

outstanding computational performance and an advanced system response to interrupts.

®

The ARM Cortex -M0 processors feature exceptional code-efficiency, delivering the high

performance expected from an ARM core, with memory sizes usually associated with 8- and

16-bit devices.

The STM32F038x6 devices embed ARM core and are compatible with all ARM tools and

software.

3.2

Memories

The device has the following features:

•

4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states and featuring embedded parity checking with exception generation for fail-critical

applications.

•

The non-volatile memory is divided into two arrays:

–

32 Kbytes of embedded Flash memory for programs and data

Option bytes

The option bytes are used to write-protect the memory (with 4 KB granularity) and/or

readout-protect the whole memory with the following options:

–

Level 0: no readout protection

Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

®

–

Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and

boot in RAM selection disabled

3.3

Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

•

boot from User Flash memory

boot from System Memory

boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART on pins PA14/PA15 or PA9/PA10.

DocID026079 Rev 5

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22

Functional overview

STM32F038x6

3.4

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a CRC-32 (Ethernet) polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.5

Power management

3.5.1

Power supply schemes

•

V

= V

= 1.8 V ± 8%: external power supply for I/Os (V

) and digital logic. It

DD

DDIO1

is provided externally through VDD pins.

•

V

= from V to 3.6 V: external analog power supply for ADC, RCs and PLL

DDA

DD

(minimum voltage to be applied to V

externally through VDDA pin. The V

is 2.4 V when the ADC is used). It is provided

voltage level must be always greater or equal

DDA

to the V voltage level and must be established first.

DD

•

V

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

BAT

backup registers (through power switch) when V is not present.

DD

For more details on how to connect power pins, refer to Figure 11: Power supply scheme.

3.5.2

3.5.3

Power-on reset

To guarantee a proper power-on reset, the NPOR pin must be held low until V is stable.

DD

When V is stable, the reset state can be exited either by:

DD

•

putting the NPOR pin in high impedance (NPOR pin has an internal pull-up), or by

forcing the pin to high level by connecting it to V

DDA

Low-power modes

The STM32F038x6 microcontrollers support two low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

•

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

•

Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM

and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line

source can be one of the 16 external lines, RTC, I2C1 or USART1.

USART1 and I2C1 peripherals can be configured to enable the HSI RC oscillator so as

to get clock for processing incoming data.

12/102

DocID026079 Rev 5

STM32F038x6

Functional overview

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

mode.

3.6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB

domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

DocID026079 Rev 5

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22

Functional overview

STM32F038x6

Figure 2. Clock tree

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3.7

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to

avoid spurious writing to the I/Os registers.

14/102

DocID026079 Rev 5

STM32F038x6

Functional overview

3.8

Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory

and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers

(except TIM14) and ADC.

3.9

Interrupts and events

3.9.1

Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

®

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4

priority levels.

•

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.9.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 24 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 38

GPIOs can be connected to the 16 external interrupt lines.

3.10

Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 10 external and 3 internal (temperature

sensor, voltage reference, VBAT voltage measurement) channels and performs conversions

in single-shot or scan modes. In scan mode, automatic conversion is performed on a

selected group of analog inputs.

The ADC can be served by the DMA controller.

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Functional overview

STM32F038x6

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

3.10.1

Temperature sensor

The temperature sensor (TS) generates a voltage V

temperature.

that varies linearly with

SENSE

The temperature sensor is internally connected to the ADC_IN16 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

Table 3. Temperature sensor calibration values

Calibration value name

Description

Memory address

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

V_DDA= 3.3 V (± 10 mV)

TS_CAL1

0x1FFF F7B8 - 0x1FFF F7B9

TS ADC raw data acquired at a

temperature of 110 °C (± 5 °C),

TS_CAL2

0x1FFF F7C2 - 0x1FFF F7C3

V_DDA= 3.3 V (± 10 mV)

3.10.2

Internal voltage reference (V

)

REFINT

The internal voltage reference (V

) provides a stable (bandgap) voltage output for the

REFINT

ADC. V

is internally connected to the ADC_IN17 input channel. The precise voltage

REFINT

of V

is individually measured for each part by ST during production test and stored in

REFINT

the system memory area. It is accessible in read-only mode.

Table 4. Internal voltage reference calibration values

Calibration value name

Description

Memory address

Raw data acquired at a

VREFINT_CAL

temperature of 30 °C (± 5 °C),

0x1FFF F7BA - 0x1FFF F7BB

V_DDA= 3.3 V (± 10 mV)

3.10.3

V

battery voltage monitoring

BAT

This embedded hardware feature allows the application to measure the V

battery voltage

BAT

using the internal ADC channel ADC_IN18. As the V

voltage may be higher than V

,

BAT

DDA

and thus outside the ADC input range, the V

pin is internally connected to a bridge

BAT

divider by 2. As a consequence, the converted digital value is half the V

voltage.

BAT

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Functional overview

3.11

Timers and watchdogs

The STM32F038x6 devices include up to five general-purpose timers and an advanced

control timer.

Table 5 compares the features of the different timers.

Table 5. Timer feature comparison

DMA

Timer

type

Counter

resolution

Counter

type

Prescaler

factor

Capture/compare Complementary

Timer

request

generation

channels

outputs

Advanced

control

Up, down, integer from

up/down 1 to 65536

TIM1

TIM2

TIM3

TIM14

16-bit

32-bit

16-bit

Yes

No

4

1

3

-

Up, down, integer from

up/down 1 to 65536

Up, down, integer from

-

up/down

1 to 65536

General

purpose

integer from

1 to 65536

Up

-

TIM16

TIM17

integer from

1 to 65536

Up

Yes

1

3.11.1

Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six

channels. It has complementary PWM outputs with programmable inserted dead times. It

can also be seen as a complete general-purpose timer. The four independent channels can

be used for:

•

input capture

output compare

PWM generation (edge or center-aligned modes)

one-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

The counter can be frozen in debug mode.

Many features are shared with those of the standard timers which have the same

architecture. The advanced control timer can therefore work together with the other timers

via the Timer Link feature for synchronization or event chaining.

3.11.2

General-purpose timers (TIM2, 3, 14, 16, 17)

There are five synchronizable general-purpose timers embedded in the STM32F038x6

devices (see Table 5 for differences). Each general-purpose timer can be used to generate

PWM outputs, or as simple time base.

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Functional overview

STM32F038x6

TIM2, TIM3

STM32F038x6 devices feature two synchronizable 4-channel general-purpose timers. TIM2

is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a

16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent

channels each for input capture/output compare, PWM or one-pulse mode output. This

gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-

control timer via the Timer Link feature for synchronization or event chaining.

TIM2 and TIM3 both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse

mode output.

Its counter can be frozen in debug mode.

TIM16 and TIM17

Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

They each have a single channel for input capture/output compare, PWM or one-pulse

mode output.

TIM16 and TIM17 have a complementary output with dead-time generation and

independent DMA request generation.

Their counters can be frozen in debug mode.

3.11.3

3.11.4

Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with

user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it

operates independently from the main clock, it can operate in Stop mode. It can be used

either as a watchdog to reset the device when a problem occurs, or as a free running timer

for application timeout management. It is hardware or software configurable through the

option bytes. The counter can be frozen in debug mode.

System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free

running. It can be used as a watchdog to reset the device when a problem occurs. It is

clocked from the APB clock (PCLK). It has an early warning interrupt capability and the

counter can be frozen in debug mode.

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Functional overview

3.11.5

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

•

a 24-bit down counter

autoreload capability

maskable system interrupt generation when the counter reaches 0

programmable clock source (HCLK or HCLK/8)

3.12

Real-time clock (RTC) and backup registers

The RTC and the five backup registers are supplied through a switch that takes power either

on V supply when present or through the V

pin. The backup registers are five 32-bit

DD

BAT

registers used to store 20 bytes of user application data when V power is not present.

DD

They are not reset by a system or power reset.

The RTC is an independent BCD timer/counter. Its main features are the following:

•

calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,

month, year, in BCD (binary-coded decimal) format

•

automatic correction for 28, 29 (leap year), 30, and 31 day of the month

programmable alarm with wake up from Stop mode capability

on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to

synchronize the RTC with a master clock

•

digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal

inaccuracy

two anti-tamper detection pins with programmable filter. The MCU can be woken up

from Stop mode on tamper event detection

timestamp feature which can be used to save the calendar content. This function can

be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be

woken up from Stop mode on timestamp event detection

•

reference clock detection: a more precise second source clock (50 or 60 Hz) can be

used to enhance the calendar precision

The RTC clock sources can be:

•

a 32.768 kHz external crystal

a resonator or oscillator

the internal low-power RC oscillator (typical frequency of 40 kHz)

the high-speed external clock divided by 32

3.13

Inter-integrated circuit interface (I²C)

2

The I C interface (I2C1) can operate in multimaster or slave modes. It can support Standard

mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)

with extra output drive.

It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two

addresses, one with configurable mask). It also includes programmable analog and digital

noise filters.

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Functional overview

STM32F038x6

2

Table 6. Comparison of I C analog and digital filters

Aspect

Analog filter

Digital filter

Pulse width of

suppressed spikes

Programmable length from 1 to 15

I2Cx peripheral clocks

≥ 50 ns

–Extra filtering capability vs.

standard requirements

Benefits

Available in Stop mode

–Stable length

Wakeup from Stop on address

match is not available when digital

filter is enabled.

Variations depending on

temperature, voltage, process

Drawbacks

In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP

capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts

verifications and ALERT protocol management. I2C1 also has a clock domain independent

from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address

match.

The I2C peripheral can be served by the DMA controller.

2

Table 7. STM32F038x6 I C implementation

I²C features⁽¹⁾

I2C1

7-bit addressing mode

X

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with extra output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

3.14

Universal synchronous/asynchronous receiver/transmitter

(USART)

The device embeds one universal synchronous/asynchronous receiver/transmitter

(USART1) which communicates at speeds of up to 6 Mbit/s.

It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor

communication mode, master synchronous communication and single-wire half-duplex

communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA

SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock

domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.

The USART interface can be served by the DMA controller.

20/102

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Functional overview

USART1

Table 8. STM32F038x6 USART implementation

USART modes/features⁽¹⁾

Hardware flow control for modem

X

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X = supported.

3.15

Serial peripheral interface (SPI) / Inter-integrated sound

interface (I²S)

The SPI is able to communicate up to 18 Mbit/s in slave and master modes in full-duplex

and half-duplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame size is configurable from 4 bits to 16 bits.

2

One standard I S interface (multiplexed with SPI1) supporting four different audio standards

can operate as master or slave at half-duplex communication mode. It can be configured to

transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a

specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit

programmable linear prescaler. When operating in master mode, it can output a clock for an

external audio component at 256 times the sampling frequency.

2

Table 9. STM32F038x6 SPI/I S implementation

SPI features⁽¹⁾

SPI

Hardware CRC calculation

Rx/Tx FIFO

X

NSS pulse mode

I²S mode

TI mode

1. X = supported.

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Functional overview

STM32F038x6

3.16

Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected

to the MCU.

22/102

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Pinouts and pin description

4

Pinouts and pin description

Figure 3. LQFP48 package pinout

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32

Pinouts and pin description

STM32F038x6

Figure 5. UFQFPN28 package pinout

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24/102

DocID026079 Rev 5

STM32F038x6

Pinouts and pin description

Figure 7. TSSOP20 package pinout

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DocID026079 Rev 5

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32

Pinouts and pin description

STM32F038x6

Table 10. Legend/abbreviations used in the pinout table

Abbreviation Definition

Name

Unless otherwise specified in brackets below the pin name, the pin function

during and after reset is the same as the actual pin name

Pin name

S

I

Supply pin

Input-only pin

Pin type

I/O

FT

FTf

TTa

Input / output pin

5 V-tolerant I/O

5 V-tolerant I/O, FM+ capable

3.3 V-tolerant I/O directly connected to ADC

External power on reset pin with embedded weak pull-up

resistor, powered from V_DDA

I/O structure

POR

TC

B

Standard 3.3V I/O

Dedicated BOOT0 pin

RST

Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during

and after reset

Notes

Alternate

Functions selected through GPIOx_AFR registers

functions

Additional

functions

Functions directly selected/enabled through peripheral registers

Table 11. Pin definitions

Pin functions

Pin number

Pin name

Notes

Additional

functions

(function upon reset)

Alternate functions

1

2

-

VBAT

PC13

S

-

Backup power supply

RTC_TAMP1,

RTC_TS,

(1)(2)

I/O TC

-

RTC_OUT,

WKUP2

PC14-OSC32_IN

(PC14)

(1)(2)

3

4

-

I/O TC

-

OSC32_IN

PC15-OSC32_OUT

(PC15)

OSC32_OUT

26/102

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Pinouts and pin description

Table 11. Pin definitions (continued)

Pin number

Pin functions

Additional

Pin name

Notes

(function upon reset)

Alternate functions

functions

PF0-OSC_IN

(PF0)

5

6

7

2

A5

2

3

4

I/O

FT

-

OSC_IN

PF1-OSC_OUT

(PF1)

3

B5

C5

OSC_OUT

Device reset input / internal reset output

(active low)

4

NRST

I/O RST

0

16 E1 15

8

9

VSSA

VDDA

S

-

Analog ground

(3)

5

6

5

D5

5

Analog power supply

ADC_IN0,

TIM2_CH1_ETR,

RTC_TAMP2,

10

11

6

7

B4

C4

6

7

PA0

PA1

I/O TTa

-

USART1_CTS

WKUP1

TIM2_CH2,

7

EVENTOUT,

ADC_IN1

USART1_RTS

TIM2_CH3,

12

13

8

9

8

9

D4

E5

8

9

PA2

PA3

I/O TTa

-

ADC_IN2

ADC_IN3

USART1_TX

TIM2_CH4,

USART1_RX

SPI1_NSS,

I2S1_WS,

14 10 10 B3 10

PA4

PA5

I/O TTa

-

ADC_IN4

ADC_IN5

TIM14_CH1,

USART1_CK

SPI1_SCK,

I2S1_CK,

15 11 11 C3 11

TIM2_CH1_ETR

SPI1_MISO,

I2S1_MCK,

TIM3_CH1,

TIM1_BKIN,

TIM16_CH1,

EVENTOUT

16 12 12 D3 12

PA6

I/O TTa

-

ADC_IN6

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32

Pinouts and pin description

Pin number

STM32F038x6

Table 11. Pin definitions (continued)

Pin functions

Pin name

Notes

Additional

functions

(function upon reset)

Alternate functions

SPI1_MOSI,

I2S1_SD,

TIM3_CH2,

TIM14_CH1,

TIM1_CH1N,

TIM17_CH1,

EVENTOUT

17 13 13 E4 13

PA7

I/O TTa

-

ADC_IN7

TIM3_CH3,

TIM1_CH2N,

EVENTOUT

18 14 14 E3

-

PB0

PB1

I/O TTa

ADC_IN8

ADC_IN9

TIM3_CH4,

TIM14_CH1,

TIM1_CH3N

19 15

-

(4)

-

20 16 15 E2 14

NPOR

PB10

I

POR

Device power-on reset input

TIM2_CH3,

-

21

-

I/O FTf

I2C1_SCL

TIM2_CH4,

22

23

-

PB11

-

EVENTOUT,

I2C1_SDA

-

0

16 E1 15

VSS

VDD

S

-

Ground

Digital power supply

TIM1_BKIN,

24 17 17 D1 16

25

-

PB12

I/O

FT

-

EVENTOUT,

SPI1_NSS

TIM1_CH1N,

SPI1_SCK

26

27

28

-

PB13

PB14

PB15

I/O

FT

-

TIM1_CH2N,

SPI1_MISO

-

TIM1_CH3N,

SPI1_MOSI

RTC_REFIN

USART1_CK,

TIM1_CH1,

EVENTOUT,

MCO

29 18 18 D2

-

PA8

I/O

FT

-

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Pinouts and pin description

Table 11. Pin definitions (continued)

Pin number

Pin functions

Additional

Pin name

Notes

(function upon reset)

Alternate functions

functions

USART1_TX,

30 19 19 C1 17

PA9

I/O FTf

-

TIM1_CH2,

I2C1_SCL

-

USART1_RX,

TIM1_CH3,

TIM17_BKIN,

I2C1_SDA

31 20 20 B1 18

PA10

USART1_CTS,

TIM1_CH4,

32 21

33 22

-

PA11

PA12

I/O

FT

EVENTOUT

USART1_RTS,

TIM1_ETR,

I/O

FT

-

EVENTOUT

PA13

IR_OUT,

SWDIO

(5)

34 23 21 A1 19

(SWDIO)

35

36

-

PF6

PF7

I/O FTf

-

I2C1_SCL

I2C1_SDA

-

PA14

USART1_TX,

SWCLK

(5)

37 24 22 A2 20

I/O

FT

-

(SWCLK)

SPI1_NSS,

I2S1_WS,

(6)

38 25 23

-

PA15

I/O

FT

TIM2_CH_ETR,

EVENTOUT,

USART1_RX

-

SPI1_SCK,

I2S1_CK,

(6)

39 26 24

-

PB3

PB4

I/O

FT

-

TIM2_CH2,

EVENTOUT

SPI1_MISO,

I2S1_MCK,

TIM3_CH1,

EVENTOUT

40 27 25

DocID026079 Rev 5

29/102

32

Pinouts and pin description

Pin number

STM32F038x6

Table 11. Pin definitions (continued)

Pin functions

Pin name

Notes

Additional

functions

(function upon reset)

Alternate functions

SPI1_MOSI,

I2S1_SD,

41 28 26 C2

-

PB5

I/O

FT

-

I2C1_SMBA,

TIM16_BKIN,

TIM3_CH2

-

I2C1_SCL,

USART1_TX,

TIM16_CH1N

42 29 27 B2

43 30 28 A3

-

PB6

PB7

I/O FTf

-

I2C1_SDA,

USART1_RX,

TIM17_CH1N

44 31

45 32

1

-

A4

-

1

-

BOOT0

PB8

I

B

-

Boot memory selection

I2C1_SCL,

I/O FTf

-

TIM16_CH1

I2C1_SDA,

IR_OUT,

46

-

PB9

I/O FTf

-

TIM17_CH1,

EVENTOUT

47

48

0

1

-

E1

-

VSS

VDD

S

-

Ground

Digital power supply

1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the

content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to

the RTC domain and RTC register descriptions in the reference manual.

3. VSSA pin is not in package pinout. VSSA pad of the die is connected to VSS pin.

4. These pins are powered by V_DDA

.

5. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO

pin and the internal pull-down on the SWCLK pin are activated.

6. On the WLCSP25 package, PB3, PB4 and PA15 must be set to defined levels by software, as their corresponding pads on

the silicon die are left unconnected. Apply same recommendations as for unconnected pins.

30/102

DocID026079 Rev 5

STM32F038x6

Memory mapping

5

Memory mapping

Figure 8. STM32F038x6 memory map

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CONFIGURATION

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DocID026079 Rev 5

33/102

35

Memory mapping

Bus

STM32F038x6

Table 14. Peripheral register boundary addresses

Boundary address

Size

Peripheral

0x4800 1800 - 0x5FFF FFFF

0x4800 1400 - 0x4800 17FF

0x4800 0C00 - 0x4800 13FF

0x4800 0800 - 0x4800 0BFF

0x4800 0400 - 0x4800 07FF

0x4800 0000 - 0x4800 03FF

0x4002 4400 - 0x47FF FFFF

0x4002 3400 - 0x4002 3FFF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1400 - 0x4002 1FFF

0x4002 1000 - 0x4002 13FF

0x4002 0400 - 0x4002 0FFF

0x4002 0000 - 0x4002 03FF

0x4001 8000 - 0x4001 FFFF

0x4001 5C00 - 0x4001 7FFF

0x4001 5800 - 0x4001 5BFF

0x4001 4C00 - 0x4001 57FF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 3C00 - 0x4001 43FF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 0800 - 0x4001 23FF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 8000 - 0x4000 FFFF

~384 MB

1KB

Reserved

GPIOF

2KB

Reserved

GPIOC

AHB2

1KB

GPIOB

1KB

GPIOA

~128 MB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

3 KB

1 KB

32 KB

9KB

Reserved

CRC

Reserved

Flash memory interface

Reserved

RCC

AHB1

Reserved

DMA

Reserved

DBGMCU

Reserved

TIM17

1KB

3KB

1KB

TIM16

2KB

Reserved

USART1

Reserved

SPI1/I2S1

TIM1

1KB

APB

1KB

Reserved

ADC

1KB

7KB

Reserved

EXTI

1KB

SYSCFG

Reserved

32 KB

34/102

DocID026079 Rev 5

STM32F038x6

Bus

Memory mapping

Peripheral

Table 14. Peripheral register boundary addresses (continued)

Boundary address

Size

0x4000 7400 - 0x4000 7FFF

0x4000 7000 - 0x4000 73FF

0x4000 5800 - 0x4000 6FFF

0x4000 5400 - 0x4000 57FF

0x4000 3400 - 0x4000 53FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 0800 - 0x4000 1FFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

3KB

1KB

6KB

1KB

8KB

1KB

6KB

1KB

Reserved

PWR

Reserved

I2C1

Reserved

IWDG

APB

WWDG

RTC

Reserved

TIM14

Reserved

TIM3

TIM2

DocID026079 Rev 5

35/102

35

Electrical characteristics

STM32F038x6

6

Electrical characteristics

6.1

Parameter conditions

Unless otherwise specified, all voltages are referenced to V

.

SS

6.1.1

Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T = 25 °C and T = T max (given by

A

the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics

are indicated in the table footnotes and are not tested in production. Based on

characterization, the minimum and maximum values refer to sample tests and represent the

mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2

6.1.3

Typical values

Unless otherwise specified, typical data are based on T = 25 °C, V = 1.8 V and V

3.3 V. They are given only as design guidelines and are not tested.

=

A

DD

DDA

Typical ADC accuracy values are determined by characterization of a batch of samples from

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ±2σ).

Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

6.1.4

6.1.5

Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions

Figure 10. Pin input voltage

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36/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

6.1.6

Power supply scheme

Figure 11. Power supply scheme

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Caution:

Each power supply pair (V /V , V

/V

etc.) must be decoupled with filtering ceramic

DD SS DDA SSA

capacitors as shown above. These capacitors must be placed as close as possible to, or

below, the appropriate pins on the underside of the PCB to ensure the good functionality of

the device.

DocID026079 Rev 5

37/102

79

Electrical characteristics

STM32F038x6

6.1.7

Current consumption measurement

Figure 12. Current consumption measurement scheme

,

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38/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

6.2

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics,

Table 16: Current characteristics and Table 17: Thermal characteristics may cause

permanent damage to the device. These are stress ratings only and functional operation of

the device at these conditions is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

(1)

Table 15. Voltage characteristics

Symbol

Ratings

Min

Max

Unit

V

_DD–V_SSExternal main supply voltage

−0.3

- 0.3

1.95

V

V_DDA–V_SSExternal analog supply voltage

4.0

V_DD–V_DDAAllowed voltage difference for V_DD> V_DDA

-

0.4

V

V_BAT–V_SSExternal backup supply voltage

- 0.3

4.0

V

Input voltage on FT and FTf pins

V_SS−0.3

0

V_DDIOx+ 4.0 ⁽³⁾

V

Input voltage on POR pins

4.0

9.0

4.0

50

V

(2)

V_IN

Input voltage on TTa pins

BOOT0

V

Input voltage on any other pin

Variations between different V_DDpower pins

V_SS−0.3

-

V

|∆V_DDx

|V_SSx- V_SS

V_ESD(HBM)

|

mV

Variations between all the different ground

pins

|

-

50

mV

-

Electrostatic discharge voltage

(human body model)

see Section 6.3.11: Electrical

sensitivity characteristics

1. All main power (V_DD, V_DDA) and ground (V_SS, V_SSA) pins must always be connected to the external power

supply, in the permitted range.

2. V_INmaximum must always be respected. Refer to Table 16: Current characteristicsfor the maximum

allowed injected current values.

3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is

enabled, the maximum limit is 4 V.

DocID026079 Rev 5

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79

Electrical characteristics

Symbol

STM32F038x6

Table 16. Current characteristics

Ratings

Max.

Unit

ΣI_VDD

ΣI_VSS

Total current into sum of all VDD power lines (source)⁽¹⁾

Total current out of sum of all VSS ground lines (sink)⁽¹⁾

Maximum current into each VDD power pin (source)⁽¹⁾

Maximum current out of each VSS ground pin (sink)⁽¹⁾

Output current sunk by any I/O and control pin

Output current source by any I/O and control pin

Total output current sunk by sum of all I/Os and control pins⁽²⁾

Total output current sourced by sum of all I/Os and control pins⁽²⁾

Injected current on POR, B, FT and FTf pins

120

-120

100

-100

25

I_VDD(PIN)

I_VSS(PIN)

I_IO(PIN)

-25

80

ΣI_IO(PIN)

-80

mA

-5/+0⁽⁴⁾

(3)

I_INJ(PIN)

Injected current on TC and RST pin

± 5

Injected current on TTa pins⁽⁵⁾

± 5

ΣI_INJ(PIN)

Total injected current (sum of all I/O and control pins)⁽⁶⁾

± 25

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the

permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be

sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

3. A positive injection is induced by V_IN> V_DDIOxwhile a negative injection is induced by V_IN< V_SS. I_INJ(PIN)must never be

exceeded. Refer to Table 15: Voltage characteristics for the maximum allowed input voltage values.

4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum

value.

5. On these I/Os, a positive injection is induced by V_IN> V_DDA. Negative injection disturbs the analog performance of the

device. See note ⁽²⁾below Table 51: ADC accuracy.

6. When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN)is the absolute sum of the positive and

negative injected currents (instantaneous values).

Table 17. Thermal characteristics

Symbol

Ratings

Storage temperature range

Maximum junction temperature

Value

Unit

T_STG

T_J

–65 to +150

150

°C

40/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

6.3

Operating conditions

6.3.1

General operating conditions

Table 18. General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

f_HCLK

f_PCLK

V_DD

Internal AHB clock frequency

Internal APB clock frequency

Standard operating voltage

-

0

48

MHz

V

1.65

1.95

Analog operating voltage

(ADC not used)

V_DD

2.4

3.6

Must have a potential equal

to or higher than V_DD

V_DDA

V

Analog operating voltage

(ADC used)

V_BAT

Backup operating voltage

-

1.65

–0.3

0

3.6

TC and RST I/O

TTa and POR I/O

FT and FTf I/O

BOOT0

V_DDIOx+0.3

V

_DDA+0.3⁽¹⁾

5.2⁽¹⁾

5.2

V_IN

I/O input voltage

V

LQFP48

-

364

UFQFPN32

-

526

Power dissipation at T_A= 85 °C

for suffix 6 or T_A= 105 °C for

suffix 7⁽²⁾

P_D

UFQFPN28

-

169

mW

WLCSP25

-

267

TSSOP20

-

182

Maximum power dissipation

Low power dissipation⁽³⁾

Maximum power dissipation

Low power dissipation⁽³⁾

Suffix 6 version

Suffix 7 version

–40

85

Ambient temperature for the

suffix 6 version

°C

105

TA

TJ

105

Ambient temperature for the

suffix 7 version

125

105

Junction temperature range

125

1. For operation with a voltage higher than V_DDIOx+ 0.3 V, the internal pull-up resistor must be disabled.

2. If T_Ais lower, higher P_Dvalues are allowed as long as T_Jdoes not exceed T_Jmax. See Section 7.6: Thermal characteristics.

3. In low power dissipation state, T_Acan be extended to this range as long as T_Jdoes not exceed T_Jmax(see Section 7.6:

Thermal characteristics).

6.3.2

Operating conditions at power-up / power-down

The parameters given in Table 19 are derived from tests performed under the ambient

temperature condition summarized in Table 18.

DocID026079 Rev 5

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79

Electrical characteristics

Symbol

STM32F038x6

Table 19. Operating conditions at power-up / power-down

Parameter

Conditions

Min

0

Max

∞

Unit

V_DDrise time rate

V_DDfall time rate

V_DDArise time rate

V_DDAfall time rate

t_VDD

-

20

0

∞

µs/V

∞

t_VDDA

-

20

∞

6.3.3

Embedded reference voltage

The parameters given in Table 20 are derived from tests performed under the ambient

temperature and supply voltage conditions summarized in Table 18: General operating

conditions.

Table 20. Embedded internal reference voltage

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Internal reference voltage –40 °C < T_A< +105 °C

1.2

1.23 1.25

V

REFINT

ADC_IN17 buffer startup

time

t_START

-

10⁽¹⁾

µs

ADC sampling time when

reading the internal

reference voltage

4⁽¹⁾

t_{S_vrefint}

-

Internal reference voltage

spread over the

10⁽¹⁾

∆V_REFINT

V_DDA= 3 V

-

mV

temperature range

- 100⁽¹⁾

1.5

100⁽¹⁾

4.5

T_Coeff

Temperature coefficient

-

ppm/°C

ms

T_{VREFINT_RDY}Internal reference voltage

2.5

(2)

temporization

1. Guaranteed by design, not tested in production.

2. Guaranteed by design, not tested in production. This parameter is the latency between the time when pin

NPOR is set to 1 by the application and the time when the VREFINTRDYF status bit is set to 1 by the

hardware.

6.3.4

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 12: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to CoreMark code.

42/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

Typical and maximum current consumption

The MCU is placed under the following conditions:

•

All I/O pins are in analog input mode

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted to the f

frequency:

HCLK

–

0 wait state and Prefetch OFF from 0 to 24 MHz

1 wait state and Prefetch ON above 24 MHz

= f

•

When the peripherals are enabled f

PCLK

HCLK

The parameters given in Table 21 to Table 25 are derived from tests performed under

ambient temperature and supply voltage conditions summarized in Table 18: General

operating conditions.

DocID026079 Rev 5

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79

Electrical characteristics

STM32F038x6

Table 21. Typical and maximum current consumption from V supply at V = 1.8 V

DD

All peripherals enabled

All peripherals disabled

(1)

Symbol Parameter Conditions f_HCLK

Max @ T_A

Unit

Typ

25 °C 85 °C 105 °C

48 MHz 18.2 19.7

32 MHz 12.4 13.1

20.1

13.4

10.6

3.8

20.3

13.6

10.7

3.8

11.2 11.7

12.1

8.3

6.7

2.5

0.7

12.4

8.7

6.8

2.6

11.1

7.4

5.7

2.0

0.3

11.2

7.6

5.7

2.1

2.7

1.8

1.4

0.5

0.2

2.7

1.9

1.5

0.5

12.4

8.6

6.8

2.6

0.7

12.8

9.0

6.9

2.6

11.4

7.6

5.7

2.1

0.3

11.6

7.8

5.8

2.1

2.8

1.9

1.5

0.5

0.2

2.8

2.0

1.5

0.6

7.6

6.1

2.2

0.5

8.2

6.6

2.4

0.6

External

clock (HSE 24 MHz 9.8 10.4

bypass)

Supply

current in

Run mode,

code

executing

from Flash

memory

8 MHz 3.3

1 MHz 0.7

3.7

0.8

0.9

1.0

48 MHz 18.5 20.0

32 MHz 12.7 13.4

24 MHz 10.0 10.6

20.4

13.6

10.8

3.9

20.6

14.0

10.9

4.0

11.6 12.1

7.9

6.2

2.3

8.5

6.7

2.5

Internal

clock (HSI)

8 MHz 3.4

3.8

48 MHz 17.2 18.7

32 MHz 11.4 12.2

19.1

12.4

9.6

19.3

12.7

9.7

10.2 10.6

6.7

5.1

1.7

0.2

7.2

5.5

2.0

0.3

External

clock (HSE 24 MHz 8.9

9.4

3.2

0.5

Supply

current in

Run mode,

code

bypass)

8 MHz 2.8

3.3

I_DD

1 MHz 0.3

0.5

mA

executing

from RAM

48 MHz 17.5 19.0

32 MHz 11.7 12.4

19.4

12.7

9.8

19.6

12.9

9.9

10.4 10.8

6.9

5.2

1.7

2.4

1.5

1.2

0.4

0.1

2.4

1.6

1.3

0.5

7.4

5.6

2.0

2.6

1.7

1.3

0.4

0.1

2.7

1.8

1.4

0.5

Internal

clock (HSI)

24 MHz 9.1

8 MHz 3.0

9.6

3.3

3.4

3.5

48 MHz 10.4 11.7

12.0

7.8

12.3

8.1

32 MHz 6.9

7.6

5.9

2.2

0.3

External

clock (HSE 24 MHz 5.4

6.1

6.2

bypass)

8 MHz 1.7

2.3

2.4

Supply

current in

Sleep

1 MHz 0.3

0.4

mode

48 MHz 10.6 11.8

12.1

8.1

12.4

8.3

32 MHz 7.2

24 MHz 5.5

8 MHz 1.9

7.9

6.1

2.4

Internal

clock (HSI)

6.3

6.4

2.5

2.6

1. Data based on characterization results, not tested in production unless otherwise specified.

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Electrical characteristics

Table 22. Typical and maximum current consumption from the V

supply

DDA

V

= 2.4 V

V

= 3.6 V

DDA

Conditions

(2)

Symbol Parameter

f_HCLK

Unit

Max @ T_A

25 °C 85 °C 105 °C

Max @ T_A

25 °C 85 °C 105 °C

(1)

Typ

48 MHz 147

32 MHz 101

24 MHz 79

170

121

97

180

127

101

3

184

129

103

3

160

109

86

183

129

104

3

195

137

110

3

199

140

112

4

HSE

bypass,

PLL on

Supply

current in

Run or

Sleep

mode,

HSE

bypass,

PLL off

8 MHz

1 MHz

1

3

2

3

I_DDA

µA

code

48 MHz 219

32 MHz 172

24 MHz 150

243

195

170

256

203

177

260

206

180

240

190

165

267

210

186

279

222

193

284

226

196

executing

from Flash

memory or

RAM

HSI clock,

PLL on

HSI clock,

PLL off

8 MHz

71

83

87

88

81

95

97

98

1. Current consumption from the V_DDAsupply is independent of whether the digital peripherals are enabled or disabled, being

in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, I_DDAis independent from

the frequency.

2. Data based on characterization results, not tested in production unless otherwise specified.

Table 23. Typical and maximum consumption in Stop mode

Typ. @ V_DD= 1.8 V

Max

Symbol Parameter

Conditions

Unit

I_DD

Supply

current in

Stop mode

0.4

2.3

1.5

14.9

2.6

35.6

3.4

All oscillators OFF

µA

I_DDA

0.8 0.8 0.8 0.9 0.9 1.0 1.1

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79

Electrical characteristics

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Table 24. Typical and maximum current consumption from the V

supply

BAT

Typ @ V_BAT

Max⁽¹⁾

Symbol Parameter

Conditions

Unit

T_A=

25 °C 85 °C 105 °C

LSE & RTC ON; “Xtal

mode”: lower driving

capability;

0.5 0.5 0.6 0.7 0.8 0.9

1.0

1.3

1.6

1.7

2.1

RTC

domain

supply

current

LSEDRV[1:0] = '00'

I_{DD VBAT}

_

µA

LSE & RTC ON; “Xtal

mode” higher driving

capability;

0.8 0.8 0.9 1.0 1.1 1.2

LSEDRV[1:0] = '11'

1. Data based on characterization results, not tested in production.

Typical current consumption

The MCU is placed under the following conditions:

•

V

= V

= 1.8 V

DDA

DD

All I/O pins are in analog input configuration

The Flash memory access time is adjusted to f

frequency:

HCLK

–

0 wait state and Prefetch OFF from 0 to 24 MHz

1 wait state and Prefetch ON above 24 MHz

= f

•

When the peripherals are enabled, f

PCLK

HCLK

PLL is used for frequencies greater than 8 MHz

AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and

500 kHz respectively

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Electrical characteristics

Table 25. Typical current consumption, code executing from Flash memory,

running from HSE 8 MHz crystal

Typical consumption in

Run mode

Typical consumption in

Sleep mode

Symbol Parameter

f_HCLK

Unit

Peripherals Peripherals Peripherals Peripherals

enabled

disabled

enabled

disabled

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

18.5

14.1

12.7

9.7

11.6

8.9

8.1

6.2

4.3

2.3

1.4

0.9

0.7

0.6

10.8

8.2

7.3

5.6

3.9

1.9

1.3

0.9

0.7

0.6

2.6

2.0

1.8

1.4

1.1

0.6

0.5

0.4

Current

consumption

from V_DD

supply

6.7

I_DD

mA

3.4

4 MHz

2.1

2 MHz

1.3

1 MHz

0.9

500 kHz

48 MHz

36 MHz

32 MHz

24 MHz

16 MHz

8 MHz

0.7

136

105

96

76

56

1

Current

consumption

from V_DDA

supply

I_DDA

μA

4 MHz

1

2 MHz

1

1 MHz

1

500 kHz

1

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up generate current consumption when the pin is

externally held low. The value of this current consumption can be simply computed by using

the pull-up/pull-down resistors values given in Table 44: I/O static characteristics.

For the output pins, any external pull-down or external load must also be considered to

estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate

voltage level is externally applied. This current consumption is caused by the input Schmitt

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79

Electrical characteristics

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trigger circuits used to discriminate the input value. Unless this specific configuration is

required by the application, this supply current consumption can be avoided by configuring

these I/Os in analog mode. This is notably the case of ADC input pins which should be

configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,

as a result of external electromagnetic noise. To avoid current consumption related to

floating pins, they must either be configured in analog mode, or forced internally to a definite

digital value. This can be done either by using pull-up/down resistors or by configuring the

pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see

Table 27: Peripheral current consumption), the I/Os used by an application also contribute

to the current consumption. When an I/O pin switches, it uses the current from the I/O

supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load

(internal or external) connected to the pin:

I_SW= V_DDIOx× f_SW× C

where

I

is the current sunk by a switching I/O to charge/discharge the capacitive load

SW

V

is the I/O supply voltage

DDIOx

f

is the I/O switching frequency

SW

C is the total capacitance seen by the I/O pin: C = C

+ C

EXT S

INT

C is the PCB board capacitance including the pad pin.

S

The test pin is configured in push-pull output mode and is toggled by software at a fixed

frequency.

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Electrical characteristics

Table 26. Switching output I/O current consumption

I/O toggling

frequency (f_SW

Symbol

Parameter

Conditions⁽¹⁾

Typ

Unit

)

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

48 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

48 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

2 MHz

4 MHz

8 MHz

18 MHz

36 MHz

2 MHz

4 MHz

8 MHz

18 MHz

0.09

0.17

0.34

0.79

1.50

2.06

0.13

0.26

0.50

1.18

2.27

3.03

0.18

0.36

0.69

1.60

3.27

0.23

0.45

0.87

2.0

V_DDIOx= 1.8 V

C_EXT= 0 pF

C = C_INT+ C_EXT+ C_S

V_DDIOx= 1.8 V

C_EXT= 10 pF

C = C_INT+ C_EXT+ C_S

I/O current

consumption

I_SW

mA

V_DDIOx= 1.8 V

C_EXT= 22 pF

C = C_INT+ C_EXT+ C_S

V_DDIOx= 1.8 V

C_EXT= 33 pF

C = C_INT+ C_EXT+ C_S

3.7

0.29

0.55

1.09

2.43

V_DDIOx= 1.8 V

C_EXT= 47 pF

C = C_INT+ C_EXT+ C_S

1. C_S= 5 pF (estimated value).

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Electrical characteristics

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On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed

under the following conditions:

•

All I/O pins are in analog mode

All peripherals are disabled unless otherwise mentioned

The given value is calculated by measuring the current consumption

–

with all peripherals clocked off

with only one peripheral clocked on

•

Ambient operating temperature and supply voltage conditions summarized in Table 15:

Voltage characteristics

The power consumption of the digital part of the on-chip peripherals is given in

Table 27. The power consumption of the analog part of the peripherals (where

applicable) is indicated in each related section of the datasheet.

Table 27. Peripheral current consumption

Peripheral

BusMatrix⁽¹⁾

Typical consumption at 25 °C

Unit

3.8

6.3

DMA1

SRAM

0.7

Flash memory interface

CRC

15.2

1.61

9.4

AHB

µA/MHz

GPIOA

GPIOB

11.6

1.9

GPIOC

GPIOF

0.8

All AHB peripherals

47.5

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Electrical characteristics

Table 27. Peripheral current consumption (continued)

Peripheral

Typical consumption at 25 °C

Unit

APB-Bridge ⁽²⁾

2.6

1.7

SYSCFG

ADC ⁽³⁾

4.2

TIM1

17.1

9.6

SPI1

USART1

17.4

8.2

TIM16

TIM17

8.0

APB

µA/MHz

DBG (MCU Debug Support)

0.5

TIM2

17.4

12.8

6.0

TIM3

TIM14

WWDG

1.5

I2C1

5.1

PWR

1.2

All APB peripherals

110.9

1. The BusMatrix automatically is active when at least one master is ON (CPU or DMA1).

2. The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus.

3. The power consumption of the analog part (I_DDA) of peripherals such as ADC is not included. Refer to the

tables of characteristics in the subsequent sections.

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79

Electrical characteristics

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6.3.5

Wakeup time from low-power mode

The wakeup times given in Table 28 are the latency between the event and the execution of

the first user instruction. The device goes in low-power mode after the WFE (Wait For

Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles

must be added to the following timings due to the interrupt latency in the Cortex M0

architecture.

The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.

During wakeup from Stop mode, SYSCLK takes the default setting: HSI 8 MHz.

The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.

All timings are derived from tests performed under the ambient temperature and supply

voltage conditions summarized in Table 18: General operating conditions..

Table 28. Low-power mode wakeup timings

Typ @ V_DDA

Symbol

Parameter

Max

Unit

= 1.8 V = 3.3 V

3.5 2.8

4 SYSCLK cycles

t_WUSTOP

Wakeup from Stop mode

Wakeup from Sleep mode

5.3

-

µs

t_WUSLEEP

6.3.6

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,

the recommended clock input waveform is shown in Figure 13: High-speed external clock

source AC timing diagram.

Table 29. High-speed external user clock characteristics

Symbol

Parameter⁽¹⁾

Min

Typ

Max

Unit

f_{HSE_ext}User external clock source frequency

V_HSEHOSC_IN input pin high level voltage

-

8

-

32

MHz

0.7 V_DDIOx

V_SS

V_DDIOx

V

V_HSEL

OSC_IN input pin low level voltage

OSC_IN high or low time

-

0.3 V_DDIOx

t_w(HSEH)

t_w(HSEL)

15

-

ns

t_r(HSE)

t_f(HSE)

OSC_IN rise or fall time

20

1. Guaranteed by design, not tested in production.

52/102

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Electrical characteristics

Figure 13. High-speed external clock source AC timing diagram

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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.

The external clock signal has to respect the I/O characteristics in Section 6.3.13. However,

the recommended clock input waveform is shown in Figure 14.

Table 30. Low-speed external user clock characteristics

Symbol

Parameter⁽¹⁾

Min

Typ

Max

Unit

f_{LSE_ext}User external clock source frequency

V_LSEHOSC32_IN input pin high level voltage

V_LSELOSC32_IN input pin low level voltage

-

32.768

1000

V_DDIOx

kHz

0.7 V_DDIOx

V_SS

-

V

0.3 V_DDIOx

t_w(LSEH)

OSC32_IN high or low time

t_w(LSEL)

450

-

ns

t_r(LSE)

OSC32_IN rise or fall time

t_f(LSE)

50

1. Guaranteed by design, not tested in production.

Figure 14. Low-speed external clock source AC timing diagram

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79

Electrical characteristics

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic

resonator oscillator. All the information given in this paragraph are based on design

simulation results obtained with typical external components specified in Table 31. In the

application, the resonator and the load capacitors have to be placed as close as possible to

the oscillator pins in order to minimize output distortion and startup stabilization time. Refer

to the crystal resonator manufacturer for more details on the resonator characteristics

(frequency, package, accuracy).

Table 31. HSE oscillator characteristics

Symbol

Parameter

Conditions⁽¹⁾

Min⁽²⁾Typ Max⁽²⁾Unit

f_{OSC_IN}Oscillator frequency

-

4

-

8

200

-

32

-

MHz

R_F

Feedback resistor

-

kΩ

During startup⁽³⁾

-

8.5

V_DD= 1.8 V,

Rm = 30 Ω,

CL = 10 pF@8 MHz

-

0.4

0.5

0.8

1

-

V_DD= 1.8 V,

Rm = 45 Ω,

CL = 10 pF@8 MHz

V_DD= 1.8 V,

I_DD

HSE current consumption

mA

Rm = 30 Ω,

CL = 5 pF@32 MHz

V_DD= 1.8 V,

Rm = 30 Ω,

CL = 10 pF@32 MHz

V_DD= 1.8 V,

Rm = 30 Ω,

1.5

CL = 20 pF@32 MHz

g_m

Oscillator transconductance

Startup time

Startup

10

-

mA/V

ms

(4)

t_SU(HSE)

V_DDis stabilized

2

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Guaranteed by design, not tested in production.

3. This consumption level occurs during the first 2/3 of the t_SU(HSE)startup time

4. t_SU(HSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly

with the crystal manufacturer

For C and C , it is recommended to use high-quality external ceramic capacitors in the

L1

L2

5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match

the requirements of the crystal or resonator (see Figure 15). C and C are usually the

L1

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the

series combination of C and C . PCB and MCU pin capacitance must be included (10 pF

L1

L2

can be used as a rough estimate of the combined pin and board capacitance) when sizing

and C .

C

L1

L2

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

54/102

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Electrical characteristics

Figure 15. Typical application with an 8 MHz crystal

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1. R_EXTvalue depends on the crystal characteristics.

Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator

oscillator. All the information given in this paragraph are based on design simulation results

obtained with typical external components specified in Table 32. In the application, the

resonator and the load capacitors have to be placed as close as possible to the oscillator

pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

resonator manufacturer for more details on the resonator characteristics (frequency,

package, accuracy).

Table 32. LSE oscillator characteristics (f_LSE= 32.768 kHz)

Symbol

Parameter

Conditions⁽¹⁾

Min⁽²⁾Typ Max⁽²⁾Unit

low drive capability

medium-low drive capability

medium-high drive capability

high drive capability

-

0.5

0.9

-

1

I_DD

LSE current consumption

µA

-

1.3

-

1.6

low drive capability

5

8

15

25

-

medium-low drive capability

medium-high drive capability

high drive capability

-

Oscillator

transconductance

g_m

µA/V

s

-

(3)

t_SU(LSE)

Startup time

V_DDIOxis stabilized

2

1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

2. Guaranteed by design, not tested in production.

3. t_SU(LSE)is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

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79

Electrical characteristics

STM32F038x6

Note:

For information on selecting the crystal, refer to the application note AN2867 “Oscillator

design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 16. Typical application with a 32.768 kHz crystal

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Note:

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden

to add one.

6.3.7

Internal clock source characteristics

The parameters given in Table 33 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 18: General operating

conditions. The provided curves are characterization results, not tested in production.

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Electrical characteristics

High-speed internal (HSI) RC oscillator

(1)

Table 33. HSI oscillator characteristics

Symbol

Parameter

Frequency

HSI user trimming step

Conditions

Min

Typ

Max

Unit

f_HSI

-

8

-

MHz

%

TRIM

-

1⁽²⁾

55⁽²⁾

3.8⁽³⁾

2.3⁽³⁾

2⁽³⁾

1

DuCy_(HSI)Duty cycle

-

45⁽²⁾

-2.8⁽³⁾

-1.9⁽³⁾

-1.3⁽³⁾

-1⁽³⁾

-1

%

T_A= -40 to 105°C

T_A= -10 to 85°C

T_A= 0 to 85°C

T_A= 0 to 70°C

T_A= 0 to 55°C

T_A= 25°C⁽⁴⁾

-

Accuracy of the HSI

oscillator

ACC_HSI

%

t_su(HSI)

HSI oscillator startup time

1⁽²⁾

2⁽²⁾

µs

HSI oscillator power

consumption

I_DDA(HSI)

-

80

100⁽²⁾

µA

1. V_DDA= 3.3 V, T_A= -40 to 105°C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

4. Factory calibrated, parts not soldered.

Figure 17. HSI oscillator accuracy characterization results for soldered parts

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Electrical characteristics

STM32F038x6

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)

(1)

Table 34. HSI14 oscillator characteristics

Symbol

Parameter

Frequency

HSI14 user-trimming step

Conditions

Min

Typ

Max

Unit

f_HSI14

TRIM

-

14

-

MHz

%

1⁽²⁾

DuCy_(HSI14)Duty cycle

45⁽²⁾

-

55⁽²⁾

5.1⁽³⁾

3.1⁽³⁾

2.3⁽³⁾

1

%

T_A= –40 to 105 °C –4.2⁽³⁾

T_A= –10 to 85 °C –3.2⁽³⁾

-

%

-

%

Accuracy of the HSI14

oscillator (factory calibrated)

ACC_HSI14

T_A= 0 to 70 °C

–2.5⁽³⁾

-

%

T_A= 25 °C

-

–1

-

%

t_su(HSI14)HSI14 oscillator startup time

1⁽²⁾

-

2⁽²⁾

µs

HSI14 oscillator power

I_DDA(HSI14)

-

100 150⁽²⁾

µA

consumption

1.

2. Guaranteed by design, not tested in production.

3. Data based on characterization results, not tested in production.

V_DDA= 3.3 V, T_A= –40 to 105 °C unless otherwise specified.

Figure 18. HSI14 oscillator accuracy characterization results

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Electrical characteristics

Low-speed internal (LSI) RC oscillator

(1)

Table 35. LSI oscillator characteristics

Symbol

Parameter

Min

Typ

Max

Unit

f_LSI

Frequency

30

-

40

-

50

85

kHz

µs

(2)

t_su(LSI)

LSI oscillator startup time

(2)

I_DDA(LSI)

LSI oscillator power consumption

-

0.75

1.2

µA

1.

V_DDA= 3.3 V, T_A= –40 to 105 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

6.3.8

PLL characteristics

The parameters given in Table 36 are derived from tests performed under ambient

temperature and supply voltage conditions summarized in Table 18: General operating

conditions.

Table 36. PLL characteristics

Value

Symbol

Parameter

Unit

Min

Typ

Max

PLL input clock⁽¹⁾

1⁽²⁾

40⁽²⁾

16⁽²⁾

-

8.0

24⁽²⁾

60⁽²⁾

48

MHz

%

f_{PLL_IN}

PLL input clock duty cycle

PLL multiplier output clock

PLL lock time

-

f_{PLL_OUT}

t_LOCK

MHz

µs

200⁽²⁾

300⁽²⁾

Jitter_PLL

Cycle-to-cycle jitter

-

ps

1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the

range defined by f_{PLL_OUT}

.

2. Guaranteed by design, not tested in production.

6.3.9

Memory characteristics

Flash memory

The characteristics are given at T = –40 to 105 °C unless otherwise specified.

A

Table 37. Flash memory characteristics

Symbol

Parameter

Conditions

Min

Typ

Max⁽¹⁾Unit

t_prog

16-bit programming time T_A= - 40 to +105 °C

40

20

-

53.5

60

40

10

12

µs

ms

mA

t_ERASEPage (1 KB) erase time T_A= - 40 to +105 °C

-

t_ME

Mass erase time

T_A= - 40 to +105 °C

Write mode

I_DD

Supply current

Erase mode

-

1. Guaranteed by design, not tested in production.

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Electrical characteristics

Symbol

STM32F038x6

Table 38. Flash memory endurance and data retention

Parameter

Conditions

Min⁽¹⁾

Unit

N_END

Endurance

T_A= –40 to +105 °C

kcycle

10

30

10

20

1 kcycle⁽²⁾at T_A= 85 °C

1 kcycle⁽²⁾at T_A= 105 °C

10 kcycle⁽²⁾at T_A= 55 °C

t_RET

Data retention

Year

1. Data based on characterization results, not tested in production.

2. Cycling performed over the whole temperature range.

6.3.10

EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).

the device is stressed by two electromagnetic events until a failure occurs. The failure is

indicated by the LEDs:

•

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

•

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and

DD

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 39. They are based on the EMS levels and classes

defined in application note AN1709.

Table 39. EMS characteristics

Level/

Class

Symbol

Parameter

Conditions

V_DD= 1.8 V, LQFP48, T_A= +25 °C,

f_HCLK= 48 MHz,

conforming to IEC 61000-4-2

Voltage limits to be applied on any I/O pin

to induce a functional disturbance

V_FESD

2B

4B

Fast transient voltage burst limits to be

V_DD= 1.8 V, LQFP48, T_A= +25°C,

V_EFTBapplied through 100 pF on V_DDand V_SSf_HCLK= 48 MHz,

pins to induce a functional disturbance

conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

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Software recommendations

The software flowchart must include the management of runaway conditions such as:

•

Corrupted program counter

Unexpected reset

Critical Data corruption (for example control registers)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1

second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpected behavior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is

executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Table 40. EMI characteristics

Max vs. [f_HSE/f_HCLK

8/48 MHz

]

Monitored

frequency band

Symbol Parameter

Conditions

Unit

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1 GHz

EMI Level

-1

21

27

4

V_DD= 1.8 V, T_A= 25 °C,

LQFP48 package

compliant with

dBµV

-

S_EMI

Peak level

IEC 61967-2

6.3.11

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

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Table 41. ESD absolute maximum ratings

Maximum

Unit

Symbol

Ratings

Conditions

Packages Class

value⁽¹⁾

Electrostatic discharge voltage T_A= +25 °C, conforming

V_ESD(HBM)

All

2

2000

250

V

(human body model)

to JESD22-A114

Electrostatic discharge voltage T_A= +25 °C, conforming

V_ESD(CDM)

C3

(charge device model)

to ANSI/ESD STM5.3.1

1. Data based on characterization results, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 42. Electrical sensitivities

Symbol

Parameter

Conditions

Class

II level A

LU

Static latch-up class

T_A= +105 °C conforming to JESD78A

6.3.12

I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V or

SS

above V

(for standard, 3.3 V-capable I/O pins) should be avoided during normal

DDIOx

product operation. However, in order to give an indication of the robustness of the

microcontroller in cases when abnormal injection accidentally happens, susceptibility tests

are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating input mode. While current is injected into

the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher

than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or

oscillator frequency deviation).

The characterization results are given in Table 43.

Negative induced leakage current is caused by negative injection and positive induced

leakage current is caused by positive injection.

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Table 43. I/O current injection susceptibility

Functional

susceptibility

Symbol

Description

Unit

Negative Positive

injection injection

Injected current on BOOT0

–0

–5

NA

+5

I_INJ

Injected current on all FT, FTf and POR pins

Injected current on all TTa, TC and RESET pins

mA

6.3.13

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 44 are derived from tests

performed under the conditions summarized in Table 18: General operating conditions. All

I/Os are designed as CMOS- and TTL-compliant (except BOOT0).

Table 44. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

TC and TTa I/O

FT and FTf I/O

BOOT0

-

0.3 V_DDIOx+0.07⁽¹⁾

0.475 V_DDIOx–0.2⁽¹⁾

0.3 V_DDIOx–0.3⁽¹⁾

Low level input

voltage

V_IL

V

All I/Os except

BOOT0 pin

-

0.3 V_DDIOx

TC and TTa I/O

FT and FTf I/O

BOOT0

0.445 V_DDIOx+0.398⁽¹⁾

0.5 V_DDIOx+0.2⁽¹⁾

-

High level input

voltage

0.2 V_DDIOx+0.95⁽¹⁾

V_IH

V

All I/Os except

BOOT0 pin

0.7 V_DDIOx

-

TC and TTa I/O

FT and FTf I/O

BOOT0

-

200⁽¹⁾

100⁽¹⁾

300⁽¹⁾

-

Schmitt trigger

hysteresis

V_hys

mV

TC, FT and FTf I/O

TTa in digital mode

V_SS≤ V_IN≤ V_DDIOx

-

± 0.1

TTa in digital mode

V_DDIOx≤ V_IN≤ V_DDA

-

1

Input leakage

current⁽²⁾

I_lkg

µA

TTa in analog mode

V_SS≤ V_IN≤ V_DDA

± 0.2

10

FT and FTf I/O

V_DDIOx≤ V_IN≤ 5 V

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Electrical characteristics

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Table 44. I/O static characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Weak pull-up

R_PU

equivalent resistor V_IN= V_SS

25

40

55

kΩ

(3)

Weak pull-down

R_PD

C_IO

equivalent

V_IN= - V_DDIOx

25

-

40

5

55

-

kΩ

resistor⁽³⁾

I/O pin capacitance

-

pF

1. Data based on design simulation only. Not tested in production.

2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 43:

I/O current injection susceptibility.

3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements is shown in Figure 19 for standard I/Os, and in Figure 20 for

5 V-tolerant I/Os. The following curves are design simulation results, not tested in

production.

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Figure 19. TC and TTa I/O input characteristics

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79

Electrical characteristics

STM32F038x6

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or

source up to +/- 20 mA (with a relaxed V /V ).

OL OH

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

•

The sum of the currents sourced by all the I/Os on V

, plus the maximum

DDIOx

consumption of the MCU sourced on V , cannot exceed the absolute maximum rating

DD

ΣI

(see Table 15: Voltage characteristics).

VDD

•

The sum of the currents sunk by all the I/Os on V , plus the maximum consumption of

SS

the MCU sunk on V , cannot exceed the absolute maximum rating ΣI

(see

SS

VSS

Table 15: Voltage characteristics).

Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 18: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or

TC unless otherwise specified).

(1)

Table 45. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

(2)

V_OL

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

-

0.4

-

V

|I_IO| = 4 mA

(2)

V_OH

V_DDIOx–0.4

Output low level voltage for an FTf I/O pin in

Fm+ mode

(3)

V_OLFm+

|I_IO| = 10 mA

-

0.4

V

1. The I_IOcurrent sourced or sunk by the device must always respect the absolute maximum rating specified in Table 15:

Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always

respect the absolute maximum ratings ΣI

.

IO

2. Data based on characterization results. Not tested in production.

3. Data based on design simulation only. Not tested in production.

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Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 21 and

Table 46, respectively. Unless otherwise specified, the parameters given are derived from

tests performed under the ambient temperature and supply voltage conditions summarized

in Table 18: General operating conditions.

(1)(2)

Table 46. I/O AC characteristics

OSPEEDRy

Symbol

Parameter

Conditions

Min

Max

Unit

MHz

ns

[1:0] value⁽¹⁾

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

-

1

125

4

x0

C_L= 50 pF

t_r(IO)outOutput rise time

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

MHz

ns

01

C_L= 50 pF

62.5

10

t_r(IO)outOutput rise time

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

MHz

ns

11

25

t_r(IO)outOutput rise time

f_max(IO)outMaximum frequency⁽³⁾

t_f(IO)outOutput fall time

25

0.5

16

MHz

ns

Fm+

configuration

CL = 50 pF

(4)

t_r(IO)outOutput rise time

44

Pulse width of external

t_EXTIpwsignals detected by the

EXTI controller

-

10

-

ns

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference

manual for a description of GPIO Port configuration register.

2. Guaranteed by design, not tested in production.

3. The maximum frequency is defined in Figure 21.

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference

manual RM0091 for a detailed description of Fm+ I/O configuration.

Figure 21. I/O AC characteristics definition

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79

Electrical characteristics

STM32F038x6

6.3.14

NRST and NPOR pin characteristics

NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-

up resistor, R

.

PU

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature and supply voltage conditions summarized in

Table 18: General operating conditions.

Table 47. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NRST)NRST input low level voltage

V_IH(NRST)NRST input high level voltage

-

0.3 V_DD+0.07⁽¹⁾

-

V

0.445 V_DD+0.398⁽¹⁾

NRST Schmitt trigger voltage

V_hys(NRST)

hysteresis

-

200

40

-

mV

Weak pull-up equivalent

R_PU

V_IN= V_SS

25

55

kΩ

resistor⁽²⁾

V_F(NRST)NRST input filtered pulse

-

100⁽¹⁾

-

ns

V_NF(NRST)NRST input not filtered pulse

700⁽¹⁾

1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

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1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V_IL(NRST)max level specified in

Table 47: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.

NPOR pin characteristics

The NPOR pin input driver uses the CMOS technology. It is connected to a permanent pull-

up resistor to the V

, R

.

DDA

PU

Unless otherwise specified, the parameters given in Table 48 below are derived from tests

performed under ambient temperature and supply voltage conditions summarized in

Table 18: General operating conditions.

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Symbol

Electrical characteristics

Table 48. NPOR pin characteristics

Parameter

Conditions

Min

Typ

Max

Unit

V_IL(NPOR)NPOR Input low level voltage

-

0.475 V_DDA- 0.2⁽¹⁾

V

NPOR Input high level

V_IH(NPOR)

voltage

-

0.5 V_DDA+ 0.2⁽¹⁾

-

NPOR Schmitt trigger voltage

V_hys(NPOR)

hysteresis

-

100⁽¹⁾

40

mV

Weak pull-up equivalent

R_PU

V_IN= V_SS

25

55

kΩ

resistor⁽²⁾

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series

resistance is minimal (~10% order).

6.3.15

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 49 are derived from tests

performed under the conditions summarized in Table 18: General operating conditions.

Note:

It is recommended to perform a calibration after each power-up.

Table 49. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Analog supply voltage for

ADC ON

V_DDA

-

2.4

-

3.6

V

Current consumption of

the ADC⁽¹⁾

I_{DDA (ADC)}

f_ADC

V_DDA= 3.3 V

-

0.9

-

mA

ADC clock frequency

Sampling rate

-

0.6

-

14

1

MHz

(2)

f_S

12-bit resolution

0.043

f

_ADC= 14 MHz,

-

823

kHz

(2)

12-bit resolution

External trigger frequency

f_TRIG

12-bit resolution

-

17

1/f_ADC

V

V_AIN

Conversion voltage range

External input impedance

0

V_DDA

See Equation 1 and

Table 50 for details

(2)

R_AIN

-

50

1

kΩ

pF

Sampling switch

resistance

(2)

-

R_ADC

Internal sample and hold

capacitor

(2)

8

C_ADC

f

_ADC= 14 MHz

5.9

83

µs

(2)(3)

Calibration time

t_CAL

-

1/f_ADC

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Table 49. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1.5 ADC

cycles + 3

f_PCLKcycles

1.5 ADC

cycles + 2

f_PCLKcycles

ADC clock = HSI14

-

ADC_DR register ready

latency

(2)(4)

W_LATENCY

f_PCLK

cycle

ADC clock = PCLK/2

-

4.5

8.5

-

f_PCLK

cycle

ADC clock = PCLK/4

f

_ADC= f_PCLK/2 = 14 MHz

0.196

5.5

µs

1/f_PCLK

µs

f

_ADC= f_PCLK/2

(2)

Trigger conversion latency f_ADC= f_PCLK/4 = 12 MHz

f_ADC= f_PCLK/4

0.219

10.5

-

t_latr

1/f_PCLK

µs

f_ADC= f_HSI14= 14 MHz

0.179

-

0.250

-

ADC jitter on trigger

conversion

Jitter_ADC

f

_ADC= f_HSI14

1

1/f_HSI14

f_ADC= 14 MHz

0.107

1.5

-

17.1

µs

(2)

Sampling time

Stabilization time

t_S

-

239.5

1/f_ADC

(2)

t_STAB

14

f_ADC= 14 MHz,

12-bit resolution

1

-

18

µs

Total conversion time

(including sampling time)

(2)

t_CONV

14 to 252 (t_Sfor sampling +12.5 for

successive approximation)

12-bit resolution

1/f_ADC

1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I_DDAand 60 µA

on I_DDshould be taken into account.

2. Guaranteed by design, not tested in production.

3. Specified value includes only ADC timing. It does not include the latency of the register access.

4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.

Equation 1: R

max formula

AIN

T_S

R_AIN< --------------------------------------------------------------- – R_ADC

f_ADC× C_ADC× ln(2^{N + 2}

)

The formula above (Equation 1) is used to determine the maximum external impedance

allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 50. R

max for f

t_S(µs)

= 14 MHz

ADC

AIN

T_s(cycles)

R_AINmax (kΩ)⁽¹⁾

1.5

7.5

0.11

0.54

0.96

0.4

5.9

13.5

11.4

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Table 50. R

max for f

= 14 MHz (continued)

AIN

ADC

T_s(cycles)

t_S(µs)

R_AINmax (kΩ)⁽¹⁾

28.5

41.5

55.5

71.5

239.5

2.04

2.96

3.96

5.11

17.1

25.2

37.2

50

NA

1. Guaranteed by design, not tested in production.

(1)(2)(3)

Table 51. ADC accuracy

Symbol

Parameter

Test conditions

Typ

Max⁽⁴⁾

Unit

ET

EO

EG

ED

EL

Total unadjusted error

Offset error

±1.3

±1

±2

±1.5

±1

f

_PCLK= 48 MHz,

f_ADC= 14 MHz, R_AIN< 10 kΩ

V_DDA= 3 V to 3.6 V

T_A= 25 °C

Gain error

±0.5

±0.7

±0.8

±3.3

±1.9

±2.8

±0.7

±1.2

±3.3

±1.9

±2.8

±0.7

±1.2

LSB

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

±1.5

±4

ET

EO

EG

ED

EL

f_PCLK= 48 MHz,

f_ADC= 14 MHz, R_AIN< 10 kΩ

±2.8

±3

Gain error

LSB

V_DDA= 2.7 V to 3.6 V

T_A= - 40 to 105 °C

Differential linearity error

Integral linearity error

Total unadjusted error

Offset error

±1.3

±1.7

±4

ET

EO

EG

ED

EL

f_PCLK= 48 MHz,

f_ADC= 14 MHz, R_AIN< 10 kΩ

±2.8

±3

Gain error

V

_DDA= 2.4 V to 3.6 V

Differential linearity error

Integral linearity error

±1.3

±1.7

T_A= 25 °C

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input

pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog

input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject

negative current.

Any positive injection current within the limits specified for I_INJ(PIN)and ΣI_INJ(PIN)in Section 6.3.13 does not affect the ADC

accuracy.

3. Better performance may be achieved in restricted V_DDA, frequency and temperature ranges.

4. Data based on characterization results, not tested in production.

DocID026079 Rev 5

71/102

79

Electrical characteristics

STM32F038x6

Figure 23. ADC accuracy characteristics

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1. Refer to Table 49: ADC characteristics for the values of R_AIN, R_ADCand C_ADC

.

2. C_parasiticrepresents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high C_parasiticvalue will downgrade conversion accuracy. To remedy

this, f_ADCshould be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 11: Power supply

scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as

close as possible to the chip.

72/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

6.3.16

Temperature sensor characteristics

Table 52. TS characteristics

Symbol

Parameter

V_SENSElinearity with temperature

Avg_Slope⁽¹⁾Average slope

Min

Typ

Max

Unit

(1)

T_L

-

4.0

1.34

-

± 1

4.3

1.43

-

± 2

4.6

°C

mV/°C

V

V₃₀

Voltage at 30 °C (± 5 °C)⁽²⁾

1.52

10

(1)

t_START

ADC_IN16 buffer startup time

µs

ADC sampling time when reading the

temperature

t_{S_temp}

4

-

µs

1. Guaranteed by design, not tested in production.

2. Measured at V_DDA= 3.3 V ± 10 mV. The V₃₀ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:

Temperature sensor calibration values.

6.3.17

V

monitoring characteristics

BAT

Table 53. V

monitoring characteristics

BAT

Symbol

Parameter

Resistor bridge for V_BAT

Min

Typ

Max

Unit

R

Q

-

2 x 50

-

kΩ

-

Ratio on V_BATmeasurement

Error on Q

2

-

Er⁽¹⁾

–1

4

+1

-

%

µs

(1)

t_{S_vbat}

ADC sampling time when reading the V_BAT

-

1. Guaranteed by design, not tested in production.

6.3.18

Timer characteristics

The parameters given in the following tables are guaranteed by design.

Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 54. TIMx characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_TIMxCLK

ns

-

1

-

t_res(TIM)

Timer resolution time

f_TIMxCLK= 48 MHz

-

20.8

Timer external clock

frequency on CH1 to

CH4

f_TIMxCLK/2

MHz

f_EXT

f_TIMxCLK= 48 MHz

-

24

-

MHz

2¹⁶

t_TIMxCLK

-

16-bit timer maximum

period

f_TIMxCLK= 48 MHz

-

1365

µs

t_{MAX_COUNT}

2³²

t_TIMxCLK

32-bit counter

maximum period

f_TIMxCLK= 48 MHz

89.48

s

DocID026079 Rev 5

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79

Electrical characteristics

STM32F038x6

(1)

Table 55. IWDG min/max timeout period at 40 kHz (LSI)

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Prescaler divider PR[2:0] bits

Unit

/4

/8

0

0.1

0.2

0.4

0.8

1.6

3.2

6.4

409.6

819.2

1

/16

/32

/64

/128

/256

2

1638.4

3276.8

6553.6

13107.2

26214.4

3

4

ms

5

6 or 7

1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30

to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing

of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.

Table 56. WWDG min/max timeout value at 48 MHz (PCLK)

Prescaler

WDGTB

Min timeout value

Max timeout value

Unit

1

2

4

8

0

1

2

3

0.0853

0.1706

0.3413

0.6826

5.4613

10.9226

21.8453

43.6906

ms

6.3.19

Communication interfaces

I²C interface characteristics

2

The I C interface meets the timings requirements of the I C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

2

The I C timings requirements are guaranteed by design when the I2Cx peripheral is

properly configured (refer to Reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and V

is disabled, but is still present. Only FTf I/O pins

DDIOx

support Fm+ low level output current maximum requirement. Refer to Section 6.3.13: I/O

2

port characteristics for the I C I/Os characteristics.

2

All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog

filter characteristics:

74/102

DocID026079 Rev 5

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Electrical characteristics

2

(1)

Table 57. I C analog filter characteristics

Symbol

Parameter

Min

Max

Unit

Maximum width of spikes that are

suppressed by the analog filter

t_AF

50⁽²⁾

260⁽³⁾

ns

1. Guaranteed by design, not tested in production.

2. Spikes with widths below t_AF(min)are filtered.

3. Spikes with widths above t_AF(max)are not filtered

SPI/I²S characteristics

2

Unless otherwise specified, the parameters given in Table 58 for SPI or in Table 59 for I S

are derived from tests performed under the ambient temperature, f frequency and

PCLKx

supply voltage conditions summarized in Table 18: General operating conditions.

Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate

2

function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I S).

(1)

Table 58. SPI characteristics

Symbol

Parameter

Conditions

Master mode

Min

Max

Unit

-

18

f_SCK

1/t_c(SCK)

SPI clock frequency

MHz

Slave mode

t_r(SCK)

t_f(SCK)

SPI clock rise and fall

time

Capacitive load: C = 15 pF

-

6

ns

%

t_su(NSS)

t_h(NSS)

t_w(SCKH)

NSS setup time

NSS hold time

Slave mode

4Tpclk

-

2Tpclk + 10

Master mode, f_PCLK= 36 MHz,

presc = 4

SCK high and low time

Data input setup time

Tpclk/2 -2

Tpclk/2 + 1

t_w(SCKL)

Master mode

Slave mode

Master mode

Slave mode

4

5

-

t_su(MI)

t_su(SI)

-

t_h(MI)

t_h(SI)

4

-

Data input hold time

5

-

(2)

t_a(SO)

Data output access time Slave mode, f_PCLK= 20 MHz

Data output disable time Slave mode

0

3Tpclk

(3)

t_dis(SO)

0

18

t_v(SO)

t_v(MO)

t_h(SO)

t_h(MO)

Data output valid time

Slave mode (after enable edge)

Master mode (after enable edge)

Slave mode (after enable edge)

Master mode (after enable edge)

-

22.5

-

6

-

11.5

2

Data output hold time

-

SPI slave input clock

duty cycle

DuCy(SCK)

Slave mode

25

75

1. Data based on characterization results, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

DocID026079 Rev 5

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79

Electrical characteristics

STM32F038x6

Figure 25. SPI timing diagram - slave mode and CPHA = 0

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Figure 26. SPI timing diagram - slave mode and CPHA = 1

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1. Measurement points are done at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

76/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

Figure 27. SPI timing diagram - master mode

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1. Measurement points are done at CMOS levels: 0.3 V_DDand 0.7 V_DD

.

2

(1)

Table 59. I S characteristics

Conditions

Symbol

Parameter

Min

Max

Unit

Master mode (data: 16 bits, Audio

frequency = 48 kHz)

1.597

1.601

f_CK

1/t_c(CK)

I²S clock frequency

MHz

Slave mode

0

-

6.5

t_r(CK)

t_f(CK)

I²S clock rise time

I²S clock fall time

I²S clock high time

I²S clock low time

WS valid time

10

12

-

Capacitive load C_L= 15 pF

-

t_w(CKH)

t_w(CKL)

t_v(WS)

t_h(WS)

t_su(WS)

t_h(WS)

306

312

2

Master f_PCLK= 16 MHz, audio

frequency = 48 kHz

-

ns

%

Master mode

Slave mode

-

WS hold time

2

-

WS setup time

7

-

WS hold time

0

-

I²S slave input clock duty

cycle

DuCy(SCK)

Slave mode

25

75

DocID026079 Rev 5

77/102

79

Electrical characteristics

STM32F038x6

2

(1)

Table 59. I S characteristics (continued)

Conditions

Symbol

Parameter

Data input setup time

Min

Max

Unit

t_{su(SD_MR)}

t_{su(SD_SR)}

Master receiver

6

2

-

Slave receiver

(2)

t_{h(SD_MR)}

Master receiver

Slave receiver

4

-

Data input hold time

Data output valid time

Data output hold time

(2)

t_{h(SD_SR)}

0.5

-

ns

(2)

t_{v(SD_MT)}

Master transmitter

Slave transmitter

Master transmitter

Slave transmitter

4

31

-

(2)

t_{v(SD_ST)}

t_{h(SD_MT)}

t_{h(SD_ST)}

-

0

13

-

1. Data based on design simulation and/or characterization results, not tested in production.

2. Depends on f_PCLK. For example, if f_PCLK= 8 MHz, then T_PCLK= 1/f_PLCLK= 125 ns.

2

Figure 28. I S slave timing diagram (Philips protocol)

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1. Measurement points are done at CMOS levels: 0.3 × V_DDIOxand 0.7 × V_DDIOx

.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

78/102

DocID026079 Rev 5

STM32F038x6

Electrical characteristics

2

Figure 29. I S master timing diagram (Philips protocol)

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1. Data based on characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first

byte.

DocID026079 Rev 5

79/102

79

Package information

STM32F038x6

7

Package information

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

7.1

LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.

Figure 30. LQFP48 package outline

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1. Drawing is not to scale.

80/102

DocID026079 Rev 5

STM32F038x6

Package information

inches⁽¹⁾

Table 60. LQFP48 package mechanical data

millimeters

Symbol

Min

Typ

Max

Min

Typ

Max

A

A1

A2

b

-

0.050

1.350

0.170

0.090

8.800

6.800

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

-

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

-

1.400

0.220

-

0.0551

0.0087

-

c

D

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

0.3543

0.2756

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

D1

D3

E

8.800

6.800

-

9.200

7.200

-

0.3465

0.2677

-

0.3622

0.2835

-

E1

E3

e

-

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

k

0°

7°

0°

7°

ccc

-

0.080

-

0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 31. Recommended footprint for LQFP48 package

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ꢇꢋꢃꢁ

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AIꢊꢉꢂꢊꢊD

1. Dimensions are expressed in millimeters.

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Package information

STM32F038x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 32. LQFP48 package marking example

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

7.2

UFQFPN32 package information

UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.

82/102

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Package information

Figure 33. UFQFPN32 package outline

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1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.

3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device

ground and must be connected. It is referred to as pin 0 in Table: Pin definitions.

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Package information

STM32F038x6

Table 61. UFQFPN32 package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A3

b

0.500

0.000

-

0.550

0.020

0.152

0.230

5.000

3.500

5.000

3.500

0.500

0.400

-

0.600

0.050

-

0.0197

0.0000

-

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1969

0.1378

0.0197

0.0157

-

0.0236

0.0020

-

0.180

4.900

3.400

4.900

3.400

-

0.280

5.100

3.600

5.100

3.600

-

0.0071

0.1929

0.1339

0.1929

0.1339

-

0.0110

0.2008

0.1417

0.2008

0.1417

-

D

D1

D2

E

E1

E2

e

L

0.300

-

0.500

0.080

0.0118

-

0.0197

0.0031

ddd

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 34. Recommended footprint for UFQFPN32 package

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ꢀꢆꢋꢁ

ꢏꢆꢀꢁ

ꢀꢆꢃꢏ

ꢁꢆꢏꢁ

ꢆ

ꢇꢊ

ꢁꢆꢀꢁ

ꢇꢅ

ꢋ

ꢁꢆꢓꢏ

ꢀꢆꢋꢁ

$ꢁ%ꢋB)3B9ꢐ

1. Dimensions are expressed in millimeters.

84/102

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Package information

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 35. UFQFPN32 package marking example

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

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Package information

STM32F038x6

7.3

UFQFPN28 package information

UFQFPN28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.

Figure 36. UFQFPN28 package outline

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1. Drawing is not to scale.

(1)

Table 62. UFQFPN28 package mechanical data

millimeters

Typ

inches

Symbol

Min

Max

Min

Typ

Max

A

A1

D

0.500

-

0.550

0.000

4.000

3.000

4.000

3.000

0.400

0.350

0.152

0.250

0.500

0.600

0.050

4.100

3.100

4.100

3.100

0.500

0.450

-

0.0197

-

0.0217

0.0000

0.1575

0.1181

0.1575

0.1181

0.0157

0.0138

0.0060

0.0098

0.0197

0.0236

0.0020

0.1614

0.1220

0.1614

0.1220

0.0197

0.0177

-

3.900

2.900

3.900

2.900

0.300

0.250

-

0.1535

0.1142

0.1535

0.1142

0.0118

0.0098

-

D1

E

E1

L

L1

T

b

0.200

-

0.300

-

0.0079

-

0.0118

-

e

86/102

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STM32F038x6

Package information

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 37. Recommended footprint for UFQFPN28 package

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ꢀꢆꢀꢁ

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ꢁꢆꢐꢍ

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ꢁꢆꢏꢁ

ꢀꢆꢀꢁ

$ꢁ%ꢁB)3B9ꢀ

1. Dimensions are expressed in millimeters.

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Package information

STM32F038x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 38. UFQFPN28 package marking example

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

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Package information

7.4

WLCSP25 package information

WLCSP25 is a 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale package.

Figure 39. WLCSP25 package outline

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1. Drawing is not to scale.

Table 63. WLCSP25 package mechanical data

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

A

A1

A2

A3⁽²⁾

b^{(3) (4)}

D

0.525

0.555

0.175

0.380

0.025

0.250

2.423

2.325

0.400

1.600

0.4115

0.3625

0.585

0.0207

0.0219

0.0069

0.0150

0.0010

0.0098

0.0954

0.0915

0.0157

0.0630

0.0162

0.0143

0.0230

-

0.220

0.280

0.0087

0.0110

2.388

2.458

0.0940

0.0968

E

2.29

2.36

0.0902

0.0929

e

-

e1

e2

F

G

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Package information

STM32F038x6

Table 63. WLCSP25 package mechanical data (continued)

millimeters

Typ

inches⁽¹⁾

Symbol

Min

Max

Min

Typ

Max

aaa

bbb

ccc

ddd

eee

-

0.100

0.050

-

0.0039

0.0020

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating.

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

4. Primary datum Z and seating plane are defined by the spherical crowns of the bump.

Figure 40. Recommended footprint for WLCSP25 package

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Table 64. WLCSP25 recommended PCB design rules

Dimension Recommended values

Pitch

Dpad

0.4 mm

0.225 mm

0.290 mm typ. (depends on the soldermask

registration tolerance)

Dsm

Stencil opening

Stencil thickness

0.250 mm

0.100 mm

90/102

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Package information

Device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 41. WLCSP25 package marking example

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

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Package information

STM32F038x6

7.5

TSSOP20 package information

TSSOP20 is a 20-lead thin shrink small-outline, 6.5 x 4.4 mm, 0.65 mm pitch, package.

Figure 42.TSSOP20 package outline

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1. Drawing is not to scale.

Table 65. TSSOP20 package mechanical data

millimeters

Typ.

inches⁽¹⁾

Symbol

Min.

Max.

Min.

Typ.

Max.

A

A1

A2

b

-

1.200

0.150

1.050

0.300

0.200

6.600

4.500

-

0.0472

0.0059

0.0413

0.0118

0.0079

0.2598

0.1772

-

0.050

0.800

0.190

0.090

6.400

6.200

4.300

-

0.0020

0.0315

0.0075

0.0035

0.2520

0.2441

0.1693

-

1.000

-

0.0394

-

c

-

D⁽²⁾

6.500

6.400

4.400

0.650

0.600

1.000

0.2559

0.2520

0.1732

0.0256

0.0236

0.0394

E

E1⁽³⁾

e

L

0.450

-

0.750

-

0.0177

-

0.0295

-

L1

92/102

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Package information

Table 65. TSSOP20 package mechanical data (continued)

millimeters

Typ.

inches⁽¹⁾

Symbol

Min.

Max.

Min.

Typ.

Max.

k

0°

-

8°

0°

-

8°

aaa

0.100

0.0039

1. Values in inches are converted from mm and rounded to four decimal digits.

2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs

shall not exceed 0.15mm per side.

3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not

exceed 0.25mm per side.

Figure 43. Recommended footprint for TSSOP20 package

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ꢍꢁ

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9!?&0?6ꢊ

1. Dimensions are expressed in millimeters.

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Package information

STM32F038x6

Device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier

location.

Other optional marking or inset/upset marks, which identify the parts throughout supply

chain operations, are not indicated below.

Figure 44. TSSOP20 package marking example

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified

and therefore not approved for use in production. ST is not responsible for any consequences resulting

from such use. In no event will ST be liable for the customer using any of these engineering samples in

production. ST's Quality department must be contacted prior to any decision to use these engineering

samples to run a qualification activity.

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Package information

7.6

Thermal characteristics

The maximum chip junction temperature (T max) must never exceed the values given in

J

Table 18: General operating conditions.

The maximum chip-junction temperature, T max, in degrees Celsius, may be calculated

J

using the following equation:

T max = T max + (P max x Θ )

J

A

D

JA

Where:

•

T max is the maximum ambient temperature in °C,

A

Θ

is the package junction-to-ambient thermal resistance, in °C/W,

JA

P max is the sum of P

max and P max (P max = P

max + P max),

INT I/O

D

INT

I/O

D

P

max is the product of I and V , expressed in Watts. This is the maximum chip

DD DD

INT

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (V × I ) + Σ ((V

– V ) × I ),

DDIOx OH OH

I/O

OL

taking into account the actual V / I and V / I of the I/Os at low and high level in the

OL OL

OH OH

application.

Table 66. Package thermal characteristics

Parameter

Symbol

Value

Unit

Thermal resistance junction-ambient

LQFP48 - 7 × 7 mm

55

Thermal resistance junction-ambient

UFQFPN32 - 5 × 5 mm

38

118

74

Thermal resistance junction-ambient

UFQFPN28 - 4 × 4 mm

Θ

°C/W

JA

Thermal resistance junction-ambient

WLCSP25 - 2.13 x 2.07 mm

Thermal resistance junction-ambient

TSSOP20 - 6.5 x 4.4 mm

110

7.6.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org

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Package information

STM32F038x6

7.6.2

Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering

information scheme shown in Section 8: Ordering information.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.

As applications do not commonly use the STM32F038x6 at maximum dissipation, it is useful

to calculate the exact power consumption and junction temperature to determine which

temperature range will be best suited to the application.

The following examples show how to calculate the temperature range needed for a given

application.

Example 1: High-performance application

Assuming the following application conditions:

Maximum ambient temperature T

= 80 °C (measured according to JESD51-2),

Amax

I

= 50 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V and maximum 8 I/Os used at the same time in output

OL

at low level with I = 20 mA, V = 1.3 V

OL

P

50 mA × 3.5 V= 175 mW

INTmax =

× 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

IOmax = 20

This gives: P

= 175 mW and P

= 272 mW:

IOmax

INTmax

P

175 272 = 447 mW

+

Dmax =

Using the values obtained in Table 66 T

is calculated as follows:

Jmax

–

T

For LQFP48, 55 °C/W

= 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C

Jmax

This is within the range of the suffix 6 version parts (–40 < T < 105 °C) see Table 18:

J

General operating conditions.

In this case, parts must be ordered at least with the temperature range suffix 6 (see

Section 8: Ordering information).

Note:

With this given P

Dmax we can find the TAmax allowed for a given device temperature range (order code suffix

6 or 7).

Suffix 6: T

Suffix 7: T

= T

- (55°C/W × 447 mW) = 105-24.585 = 80.415 °C

- (55°C/W × 447 mW) = 125-24.585 = 100.415 °C

Amax

Jmax

Amax

Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient

temperatures with a low dissipation, as long as junction temperature T remains within the

J

specified range.

96/102

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Package information

Assuming the following application conditions:

Maximum ambient temperature T = 100 °C (measured according to JESD51-2),

Amax

I

= 20 mA, V = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

DD

level with I = 8 mA, V = 0.4 V

OL

P

20 mA × 3.5 V= 70 mW

INTmax =

× 8 mA × 0.4 V = 64 mW

IOmax = 20

This gives: P

= 70 mW and P

= 64 mW:

IOmax

INTmax

P

70 64 = 134 mW

Dmax =

+

Thus: P

= 134 mW

Dmax

Using the values obtained in Table 66 T

is calculated as follows:

Jmax

–

T

For LQFP48, 55 °C/W

= 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C

Jmax

This is above the range of the suffix 6 version parts (–40 < T < 105 °C).

J

In this case, parts must be ordered at least with the temperature range suffix 7 (see

Section 8: Ordering information) unless we reduce the power dissipation in order to be able

to use suffix 6 parts.

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Ordering information

STM32F038x6

8

Ordering information

For a list of available options (memory, package, and so on) or for further information on any

aspect of this device, please contact your nearest ST sales office.

Table 67. Ordering information scheme

Example:

STM32

F

038 G

6

T

6

x

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = General-purpose

Sub-family

038 = STM32F038xx

Pin count

F = 20 pins

E = 25 pins

G = 28 pins

K = 32 pins

C = 48 pins

User code memory size

6 = 32 Kbyte

Package

P = TSSOP

U = UFQFPN

T = LQFP

Y = WLCSP

Temperature range

6 = –40 °C to +85 °C

7 = –40 °C to +105 °C

Options

xxx = code ID of programmed parts (includes packing type)

TR = tape and reel packing

blank = tray packing

98/102

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Revision history

9

Revision history

Table 68. Document revision history

Date

Revision

Changes

28-May-2014

1

Initial release.

Updated:

– Table 2: STM32F038x6 family device features and

peripheral counts

– Figure 8: STM32F038x6 memory map

– AF1 alternate functions for PA0, PA1, PA2, PA3 and

PA4 in Table 11: Alternate functions selected through

GPIOA_AFR registers for port A

– the footnote for V_INmax value in Table 14: Voltage

characteristics

– the footnote for max V_INin Table 17: General

operating conditions

– Table 20: Typical and maximum current consumption

from VDD supply at VDD = 1.8 V

– Table 21: Typical and maximum current consumption

from the VDDA supply

– Table 23: Typical and maximum current consumption

from the VBAT supply

– Table 19: Embedded internal reference voltage with

the addition of t_STARTparameter

24-Sep-2015

2

– Table 48: ADC characteristics

– Table 51: TS characteristics: removed the min. value

for t_STARTparameter

– the typical value for R parameter in Table 52: V_BAT

monitoring characteristics

– V_ESD(CDM)class and value in Table 40: ESD absolute

maximum ratings

– the structure of Section 7: Package information

Added:

– Figure 32: LQFP48 marking example (package top

view)

– Figure 35: UFQFPN32 marking example (package top

view)

– Figure 38: UFQFPN28 marking example (package top

view)

– Figure 44: TSSOP20 marking example (package top

view).

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Revision history

STM32F038x6

Table 68. Document revision history (continued)

Date

Revision

Changes

Added WLCSP25 package, updates in the following:

– Table 1: Device summary

– Section 2: Description

– Table 2: STM32F038x6 family device features and

peripheral counts

2

– Section 4: Pinouts and pin description: addition of

Figure 6: WLCSP25 25-ball package ballout (bump

side) and update of Table 10: Pin definitions,

24-Sep-2015

(continued)

– Table 17: General operating conditions

– Section 7: Package information with the addition of

Section 7.4: WLCSP25 package information

– Table 65: Package thermal characteristics

Cover page:

– number of timers added in the title

– “20 mA” I²C output drive replaced with “extra”

– number of GPIOs and 5V-tolerant GPIOs corrected

Section 2: Description:

– Figure 1: Block diagram updated

Section 3: Functional overview:

– Figure 2: Clock tree updated

– Section 3.5.3: Low-power modes - added inf. on

peripherals configurable to operate with HSI

– Section 3.10.2: Internal voltage reference (V_REFINT) -

removed information on comparators

– Section 3.11.2: General-purpose timers (TIM2, 3, 14,

16, 17) - number of gen-purpose timers corrected

– Table 7: STM32F038x6 I²C implementation - added

“extra” output drive current

16-Dec-2015

3

– Table 8: STM32F038x6 USART implementation

added

Section 4: Pinouts and pin description:

– Package pinout figures updated (look and feel)

– Figure 6: WLCSP25 package pinout - now presented

in top view

– Table 11: Pin definitions - notes 3 and 6 added

Section 6: Electrical characteristics:

– Table 20: Embedded internal reference voltage:

removed -40°-to-85° condition and associated note for

V_REFINT

– Table 25 and Table 24 values rounded to 1 decimal

– Table 41: ESD absolute maximum ratings updated

– Table 44: I/O static characteristics - removed note

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STM32F038x6

Revision history

Table 68. Document revision history (continued)

Date

Revision

Changes

– Table 49: ADC characteristics - updated some

parameter values, test conditions and added

footnotes ⁽³⁾and ⁽⁴⁾

– Section 6.3.15: 12-bit ADC characteristics - changed

introductory sentence

– Table 59: I²S characteristics: table reorganized,

t_{v(SD_ST)}max value updated

16-Dec-2015

3

Section 7: Package information:

– Figure 37: Recommended footprint for UFQFPN28

package updated

Section 8: Part numbering:

– added tray packing to options

Section 6: Electrical characteristics:

– Table 32: LSE oscillator characteristics (f_LSE= 32.768

kHz) - information on configuring different drive

capabilities removed. See the corresponding

reference manual.

– Table 20: Embedded internal reference voltage -

V_REFINTvalues

10-Jan-2017

4

– Figure 25: SPI timing diagram - slave mode and

CPHA = 0 and Figure 26: SPI timing diagram - slave

mode and CPHA = 1 enhanced and corrected

Section 8: Ordering information:

– The name of the section changed from the previous

“Part numbering”

Section 7: Package information:

– Figure 41: WLCSP25 package marking example - the

composition of the package marking fields and

character sizes corrected. Check the product errata

sheet for additional information.

15-May-2017

5

– Notes under package marking figures modified.

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101

STM32F038x6

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and

improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order

acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or

the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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型号：	STM32F038K6
厂家：	ST
描述：	Clock management
文件：	总102页 (文件大小：1704K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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