SPEAR-09-H020 [STMICROELECTRONICS]
IC,PERIPHERAL (MULTIFUNCTION) CONTROLLER,CMOS,BGA,420PIN;
| 型号： | SPEAR-09-H020 |
| 厂家： | 
ST |
| 描述： | IC,PERIPHERAL (MULTIFUNCTION) CONTROLLER,CMOS,BGA,420PIN |
| 文件： | 总7页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPEAR-09-H020
SPEAr™ Head
ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC
DATA BRIEF
Features
■ ARM926EJ-S - fMAX 266 MHz,
32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and
JTAG interfaces
■ 200K customizable equivalent ASIC gates with
8 channels internal DMA high speed
accelerator function and 112 dedicated
general purpose I/Os
PBGA420
■ Multilayer AMBA 2.0 compliant Bus with
fMAX 133 MHz
■ ADC 8 bits, 230 Ksps, 16 analog input
■ Programmable internal clock generator and
channels
dithered function
■ Real Time Clock
■ 16 KB single port SRAM embedded
■ WatchDog
■ Dynamic RAM interface:
16 bit DDR, 32 / 16 bit SDRAM
■ 4 General Purpose Timers
■ SPI interface connecting serial ROM and Flash
■ Package: PBGA 384+36 6R (23x23x2.16 mm)
devices
■ 2 USB 2.0 Host independent ports with
Overview
integrated PHYs
SPEAr Head is
belonging to SPEAr family, the innovative
customizable System on Chips.
a
powerful digital engine
■ USB 2.0 Device with integrated PHY
■ Ethernet MAC 10/100 with MII management
interface
The device integrates an ARM core with a large
set of proven IPs (Intellectual Properties) and a
configurable logic block that allows very fast
customization of unique and/or proprietary
solutions, with low effort and low investment.
■ 3 independent UARTs up to 115 Kbps
(Software Flow Control mode)
■ I²C Master mode - Fast and Slow speed
■ 6 General Purpose I/Os
Optimized for embedded applications.
Order codes
Part number
Op. Temp. range, °C
Package
Packing
SPEAR-09-H020
0 to 70
PBGA420 (23x23x2.16 mm)
Tray
Rev 1
1/7
October 2005
For further information contact your local STMicroelectronics sales office.
www.st.com
7
1 Product description
SPEAR-09-H20
1
Product description
SPEAr Head is a powerful System on Chip based on 110nm HCMOS and consists of 2 main
parts: an ARM based architecture and an embedded customizable logic block.
The high performance ARM architecture frees the user from the task of developing a complete
RISC system.
The customizable logic block allows user to design custom logic and special functions.
SPEAr Head is optimized for embedded applications and thanks to its high performance can be
used for a wide range of different purposes.
Main blocks description:
1. CPU: ARM926EJ-S running at 266 MHz. It has:
–
–
–
–
–
–
–
–
–
MMU
32 KB of instruction CACHE
16 KB of data CACHE
8 KB of instruction TCM (Tightly Coupled Memory)
8 KB of data TCM
AMBA Bus interface
Coprocessor interface
JTAG
ETM9 (Embedded Trace Macro-cell) for debug; large size version.
2. Main Bus System: a complete AMBA Bus 2.0 subsystem connects different masters and
slaves.
The subsystem includes:
–
–
–
AHB Bus, for high performance devices
APB Bus, for low power / lower speed devices connectivity
Bus Matrix, for improving connection between the peripherals
Parts of these buses are available for the customizable logic block.
3. Interrupt Controller: the Interrupt Controller has 32 interrupt sources which are prioritized
and vectorized.
4. On-chip memory: 4 independent static RAM cuts, 4 KB each, are available.
They can be used on AHB Bus or directly by the custom logic.
5. Dynamic Memory Controller: it is a Multi-Port Memory Controller which is able to connect
directly to memory sizes from 16 to 512 Mbits; the data size can be 8 or 16 bits for both
DDR and SDRAM, also 32 bits for SDRAM. The external data bus can be maximum 32 bit
wide at maximum clock frequency of 133 MHz and have up to 4 chip selects; the
accessible memory is 256 MB.
Internally it handles 7 ports supporting the following masters: AHB Bus, Bus Matrix, 2 USB
2.0 Hosts, USB 2.0 Device, Ethernet MAC, eASIC MacroCell.
The Multi-Port Memory Controller block has a programmable arbitration scheme and the
transactions happen on a different layer from the main bus.
6. Serial Peripheral Interface: it allows a serial connection to ROM and Flash.
The block is connected as a slave on the main AHB Bus, through the Bus Matrix.
The default bus size is 32 bit wide and the accessible memory is 64 MB at a maximum
speed of 50 MHz
2/7
SPEAR-09-H20
1 Product description
7. USB 2.0 Hosts: these peripherals are compatible with USB 2.0 High-Speed specification.
They can work simultaneously either in Full-Speed or in High-Speed mode.
The peripherals have dedicated channels to the Multi-Port Memory Controller and 4 slave
ports for CPU programming.
The PHYs are embedded.
8. USB 2.0 Device: the peripheral is compatible with USB 2.0 High-Speed specifications.
A dedicated channel connects the peripheral with the Multi-Port Memory Controller and
registers and internal FIFO are accessible from the CPU through the main AHB Bus.
An USB-Plug Detector block is also available to verify the presence of the VBUS voltage.
The port is provided with the following endpoints on the top of the endpoint 0:
–
–
3 bulkin / bulkout endpoints
2 isochronous endpoints.
The PHY is integrated.
9. Ethernet Media Access Control (MAC) 10/100: this peripheral is compatible with IEEE 802.3
standard and supports the MII management interface for the direct configuration of the
external PHY.
It is connected to the Multi-Port Memory Controller through a dedicated channel.
The Ethernet controller and the configuration registers are accessible from the main AHB
Bus.
10. ADC: 8 bit resolution, 230 Ksps (Kilo-sample per second), with 16 analog input channels.
Connected to APB bus.
11. UARTs: 3 independent interfaces, up to 115 Kbps each, support Software Flow Control.
Connected to APB bus.
12. I2C supporting Master mode protocol in Low and Full speed.
Connected to APB bus.
13. 6 General Purpose I/O signals are available for user configuration.
Connected to APB bus.
14. Embedded features: programmable Clock System and Dithered function, Real Time Clock,
Watchdog, 4 General Purpose Timers.
All blocks are interfaced with APB Bus.
15. Customizable Logic: it consists of an embedded macro where it is possible to map up to
200K equivalent ASIC gates. The same logic can be alternatively used to implement 32
KBytes of SRAM. Logic gates and RAM bits can be mixed in the same configuration so
that processing elements, tightly coupled with embedded memories, can be easily
implemented.
The MacroCell has 2 dedicated buses, each of them connected with a 4 channel DMA in
order to speed up the data flow with the main memories.
8 interrupt lines and 112 dedicated general purpose I/Os are available.
To allow a simple development of project, customizable logic can be emulated by an
external FPGA, where customer can map his logic; FPGA is easy linkable and keeps the
access to all on-chip and I/Os interfaces of the macro.
3/7
1 Product description
SPEAR-09-H20
Figure 1. Block diagram
Connectivity
Ethernet
PHY
PHY
USB 2.0 Host
PHY
MAC 10/100
USB 2.0 Device
USB 2.0 Host
AHB Bus
M
e
m
o
r
Multi-Port
JTAG
ETM9
VIC
Memory
CTRL
ARM926EJ-S
y
C I
I CACHE D CACHE
I TCM D TCM
MMU
I
n
t
e
r
Bus
SPI
for
Bridge
f
a
c
e
s
ROM, Flash
Customizable
Logic
Customer IOs
CLK
Sys
4
RTC
WdT
GPTs
16 KB RAM
APB Bus
6
3
I²C
ADC
GPIOs
UARTs
Connectivity
4/7
SPEAR-09-H20
2 Package information
2
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages.
These packages have a Lead-free second level interconnect. The category of second Level
Interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 2. PBGA420 Mechanical Data & Package Dimensions
mm
MIN. TYP. MAX. MIN. TYP. MAX.
2.16 0.085
inch
DIM.
OUTLINE AND
MECHANICAL DATA
A
A1
A2
b
0.30
0.012
1.53
0.60
0.060
0.70 0.020 0.024 0.027
0.50
D
22.80 23.00 23.20 0.8976 0.905 0.913
D1
D2
E
21.00
0.827
0.787
20.00
22.80 32.00 23.20
E1
E2
e
21.00
20.00
1.00
1.00
0.20
0.25
0.10
0.039
0.039
F
ddd
eee
fff
0.008
0.010
0.004
PBGA420 (23x23x2.16mm)
Ball Grid Array Package
7740354 A
5/7
3 Revision history
SPEAR-09-H20
3
Revision history
Date
Revision
Changes
19-Oct-2005
1
Initial release.
6/7
SPEAR-09-H20
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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www.st.com
7/7
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