SPEAR-09-H022_06_技术文档

SPEAR-09-H022

SPEAr™ Head200

ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC

PRELIMINARY DATA

Features

■ ARM926EJ-S - f

266 MHz,

MAX

32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and

JTAG interfaces

■ 200K customizable equivalent ASIC gates

(16K LUT equivalent) with 8 channels internal

DMA high speed accelerator function and 112

dedicated general purpose I/Os

PBGA420

■ Multilayer AMBA 2.0 compliant Bus with

f

133 MHz

MAX

■ ADC 8 bits, 230 Ksps, 16 analog input

■ Programmable internal clock generator with

enhancedPLL function, specially optimized for

E.M.I. reduction

channels

■ Real Time Clock

■ 16 KB single port SRAM embedded

■ WatchDog

■ Dynamic RAM interface:

■ 4 General Purpose Timers

■ Operating temperature: - 40 to 85 °C

■ Package: PBGA 384+36 6R (23x23x1.81 mm)

16 bit DDR, 32 / 16 bit SDRAM

■ SPI interface connecting serial ROM and Flash

devices

■ 2 USB 2.0 Host independent ports with

Overview

integrated PHYs

SPEAr Head200 is a powerful digital engine

belonging to SPEAr family, the innovative

customizable System on Chips.

■ USB 2.0 Device with integrated PHY

■ Ethernet MAC 10/100 with MII management

interface

The device integrates an ARM core with a large

set of proven IPs (Intellectual Properties) and a

configurable logic block that allows very fast

customization of unique and/or proprietary

solutions, with low effort and low investment.

■ 3 independent UARTs up to 115 Kbps

(Software Flow Control mode)

2

■ I C Master mode - Fast and Slow speed

■ 6 General Purpose I/Os

Optimized for embedded applications.

Order codes

Part number

Op. Temp. range, °C

Package

Packing

SPEAR-09-H022

-40 to 85

PBGA420 (23x23x1.81 mm)

Tray

September 2006

Rev 5

1/71

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

SPEAR-09-H022

Contents

1

2

3

Reference documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

3.2

3.3

3.4

3.5

CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Internal bus structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Memory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.5.1

3.5.2

3.5.3

Memory on chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Multi-port memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6

3.7

High speed connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.1

3.6.2

3.6.3

USB 2.0 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

USB 2.0 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Ethernet 10/100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Low speed connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.7.1

3.7.2

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.8

3.9

General purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.10 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.11 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.12 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.13 Customizable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4

5

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1

5.2

Functional pin groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Special I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.1

USB 2.0 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/71

SPEAR-09-H022

Contents

5.2.2

DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6

7

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1

SPEAr Head200 software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1.1

Boot process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Serial Flash at 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

DRAM at 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

7.1.2

Booting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8

9

ARM926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1

9.2

9.3

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Reset and PLL change parameters sequence . . . . . . . . . . . . . . . . . . . . . 35

Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10

Vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10.2 Vector interrupt controller flow sequence . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.3 Simple interrupt flow sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10.4 Interrupt sources in SPEAr Head200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

11

12

DMA controller block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.2 DMA control state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Multi-Port Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

12.2 MPMC DELAY LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3 SSTLL PAD CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13

SPI memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

13.2 SMI description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3/71

Contents

SPEAR-09-H022

13.2.1 Transfer rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13.2.2 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13.2.3 Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Hardware mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Software mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

13.2.4 Booting from external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

14

15

Ethernet MAC 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

USB 2.0 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

15.1.1 USB2.0PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

15.1.2 UHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

16

USB 2.0 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.1.1 USB2.0PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.1.2 UDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.1.3 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

16.1.4 USB plug detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

17

18

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2

I C controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

18.2 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

18.3 I²C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

19

20

General purpose I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

20.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

21

Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4/71

SPEAR-09-H022

Contents

22

23

24

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Customizable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24.2 Custom project development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24.2.1 SPEAr Head behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24.2.2 External FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

24.3 Customization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

24.4 Power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

24.4.1 Bitstream download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

24.4.2 Connection startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

24.4.3 Programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

25

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

25.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

25.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

25.2.1 Supply voltage specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

25.2.2 I/O voltage specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

26

27

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5/71

List of tables

SPEAR-09-H022

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Pin description by functional groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pins belonging to POWER group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Memory mapping at reset (REMAP = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory Mapping after reset after remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Clock system I/O off-chip interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Parameters for 12 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Interrupt sources in SPEAr Head200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Supported memory cuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Multi-Port Memory Controller AHB port assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Multi-Port Memory Controller off-chip interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Output impedance configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

SPI signal interfaces description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

SMI Supported instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

External pins of ADC macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Low Voltage TTL DC input specification (3 < VDD < 3.6). . . . . . . . . . . . . . . . . . . . . . . . . . 67

Low Voltage TTL DC output specification (3 < VDD < 3.6) . . . . . . . . . . . . . . . . . . . . . . . . 67

Pull-up and Pull-down characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

LVCMOS DC input specification (3 < VDD < 3.6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

LVCMOS DC output specification (3 < VDD < 3.6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

DC input specification of bidirectional SSTL pins (2.3 < VDD DDR < 2.7) . . . . . . . . . . . . . 68

DC input specification of bidirectional differential SSTL pins . . . . . . . . . . . . . . . . . . . . . . . 68

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6/71

SPEAR-09-H022

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

ARM926EJ-S block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock system block interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

State machine of clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Oscillator board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Model for crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DMA State Machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Data packet transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 10. MPMC DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 11. SPI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 12. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 13. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 14. Ethernet MAC Controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2

Figure 15. I C Controller block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

2

Figure 16. I C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 17. Transfer sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 18. GPIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 19. Emulation with external FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 20. PBGA420 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7/71

Reference documentation

SPEAR-09-H022

1

Reference documentation

1. ARM926EJ-S - Technical Reference Manual

2. AMBA 2.0 Specification

3. EIA/JESD8-9 Specification

4. USB2.0 Specification

5. OCHI Specification

6. ECHI Specification

7. UTMI Specification

8. USB Specification

9. IEEE 802.3 Specification

2

10. I C - Bus Specification

8/71

SPEAR-09-H022

Product Overview

2

Product Overview

SPEAr Head200 is a powerful System on Chip based on 110nm HCMOS and consists of 2

main parts: an ARM based architecture and an embedded customizable logic block.

The high performance ARM architecture frees the user from the task of developing a

complete RISC system.

The customizable logic block allows user to design custom logic and special functions.

SPEAr Head200 is optimized for embedded applications and thanks to its high performance

can be used for a wide range of different purposes.

Main blocks description:

1. CPU: ARM926EJ-S running at 266 MHz.

It has:

–

MMU

32 KB of instruction CACHE

16 KB of data CACHE

8 KB of instruction TCM (Tightly Coupled Memory)

8 KB of data TCM

AMBA Bus interface

Coprocessor interface

JTAG

ETM9 (Embedded Trace Macro-cell) for debug; large size version.

2. Main Bus System: a complete AMBA Bus 2.0 subsystem connects different masters

and slaves.

The subsystem includes:

–

AHB Bus, for high performance devices

APB Bus, for low power / lower speed devices connectivity

Bus Matrix, for improving connection between the peripherals

Bus System supports two masters: the ARM926EJ-S and the Customizable Logic

block, connected to AHB Bus. All others blocks are slaves.

3. Clock and Reset System: fully programmable block with:

–

Separated set-up between clocks of AHB Bus and APB Bus peripherals

E.M.I. reduction mode, replacing all traditional drop methods for Electro-Magnetic

Interference

–

Debug mode, compliant with ARM debug status

4. Interrupt Controller: the Interrupt Controller has 32 interrupt sources which are

prioritized and vectorized.

5. On-chip memory: 4 independent static RAM cuts, 4 KB each, are available.

They can be used on AHB Bus or directly by the custom logic.

6. Dynamic Memory Controller: it is a Multi-Port Memory Controller which is able to

connect directly to memory sizes from 16 to 512 Mbits; the data size can be 8 or 16 bits

for both DDR and SDRAM, also 32 bits for SDRAM. The external data bus can be

maximum 32 bit wide at maximum clock frequency of 133 MHz and have up to 4 chip

selects; the accessible memory is 256 MB.

Internally it handles 7 ports supporting the following masters: AHB Bus, Bus Matrix, 2

USB 2.0 Hosts, USB 2.0 Device, Ethernet MAC, eASIC™ MacroCell.

9/71

Product Overview

SPEAR-09-H022

The Multi-Port Memory Controller block has a programmable arbitration scheme and

the transactions happen on a different layer from the main bus.

7. Serial Peripheral Interface: it allows a serial connection to ROM and Flash.

The block is connected as a slave on the main AHB Bus, through the Bus Matrix.

The default bus size is 32 bit wide and the accessible memory is 64 MB at a maximum

speed of 50 MHz

8. USB 2.0 Hosts: these peripherals are compatible with USB 2.0 High-Speed

specification. They can work simultaneously either in Full-Speed or in High-Speed

mode.

The peripherals have dedicated channels to the Multi-Port Memory Controller and 4

slave ports for CPU programming.

The PHYs are embedded.

9. USB 2.0 Device: the peripheral is compatible with USB 2.0 High-Speed specifications.

A dedicated channel connects the peripheral with the Multi-Port Memory Controller and

registers.

An USB-Plug Detector block is also available to verify the presence of the VBUS

voltage.

The port is provided with the following endpoints on the top of the endpoint 0:

–

3 bulkin / bulkout endpoints

2 isochronous endpoints

The PHY is integrated.

10. Ethernet Media Access Control (MAC) 10/100: this peripheral is compatible with IEEE

802.3 standard and supports the MII management interface for the direct configuration

of the external PHY.

It is connected to the Multi-Port Memory Controller through a dedicated channel.

The Ethernet controller and the configuration registers are accessible from the main

AHB Bus.

11. ADC: 8 bit resolution, 230 Ksps (Kilo-sample per second), with 16 analog input

channels. Connected to APB bus.

12. UART's: 3 independent interfaces, up to 115 Kbps each, support Software Flow

Control.

Connected to APB bus.

13. I²C supports Master mode protocol in Low and Full speed.

Connected to APB bus.

14. 6 General Purpose I/O signals are available for user configuration.

Connected to APB bus.

15. Embedded features: Real Time Clock, Watchdog, 4 General Purpose Timers.

All blocks are interfaced with APB Bus.

16. Customizable Logic: it consists of an embedded macro where it is possible to map up

to 200K equivalent ASIC gates. The same logic can be alternatively used to implement

32 KBytes of SRAM. Logic gates and RAM bits can be mixed in the same configuration

so that processing elements, tightly coupled with embedded memories, can be easily

implemented.

The MacroCell has 2 dedicated buses, each of them connected with a 4 channel DMA

in order to speed up the data flow with the main memories.

8 interrupt lines and 112 dedicated general purpose I/Os are available.

To allow a simple development of project, customizable logic can be emulated by an

external FPGA, where customer can map his logic; FPGA is easy linkable and keeps

the access to all on-chip and I/Os interfaces of the macro.

10/71

SPEAR-09-H022

Features

3

Features

3.1

CPU

It is an ARM926EJ-S RISC Processor

●

ARM926EJ-S RISC Processor

266 MHz (downward scalable)

f

MAX

Virtual address support with MMU

32 KB instruction CACHE (4 way set associative)

16 KB data CACHE (4 way set associative)

8 KB instruction TCM

8 KB data TCM

Coprocessor interface

JTAG

ETM9 (rev 2.2), large size FIFO

3.2

3.3

3.4

Internal bus structures

●

Multilayer structure AMBA 2.0 compliant

133 MHz

f

MAX

High speed I/Os with embedded DMA function

Clock system

●

Programmable clock generator

PLL with E.M.I. reduction

Low Jitter PLL for USB 2.0

Interrupt controller

●

IRQ and FIQ interrupt generations

Support up to 32 standard interrupts

Support up to 16 vectored interrupts

Software interrupt generation

3.5

Memory system

3.5.1

Memory on chip

16 KBytes single-port SRAM embedded in the eASIC™ MacroCell.

It can be used on AHB Bus or directly by the custom logic.

11/71

Features

SPEAR-09-H022

3.5.2

SPI

●

4 chip selects for asynchronous devices (ROM, Flash)

Supports Normal mode 20 MHz and Fast mode 50 MHz

AHB slave

Accessible memory: 64 MB

8 / 16 / 32 bit widths

Programmable wait states

3.5.3

Multi-port memory controller

●

Maximum clock frequency 133 MHz

Support up to 7 AHB master requests

AHB slave

Support for 8, 16 and 32 bit wide SDRAM

Support for 8 and 16 bit wide DDR

4 chip selects

Physical addressable memory up to 256 MB

Memory clock tuning to match the timing of different memory vendors

3.6

High speed connectivity

3.6.1

USB 2.0 host

●

2 USB 2.0 Host controllers with their UTMI PHY port embedded

High-Speed / Full-Speed / Low-Speed modes USB 2.0 complaint

DMA FIFO

2 AHB slaves for configuration and FIFO access

2 AHB masters for data transfer

3.6.2

USB 2.0 device

●

UDC 2.0 controller with embedded PHY

High-Speed / Full-Speed / Low-Speed modes USB 2.0 complaint

USB Self-Power mode

DMA FIFO

Master interface for DMA transfer to DRAM memory

AHB slaves for: configuration, Plug autodetect

Endpoints on the top of endpoint 0: 3 bulkin / bulkout, 2 isochronous

12/71

SPEAR-09-H022

Features

3.6.3

Ethernet 10/100

●

MAC110 controller compliant with IEEE 802.3 standard

Supporting MII 10/100 Mbits/s

MII management protocol interface

TX FIFO (512x36 Dual Port)

RX FIFO (512x36 Dual Port)

Master interface for DMA transfer to DRAM memory

AHB slave for configuration

3.7

Low speed connectivity

3.7.1

UART

●

Support for 8 bit serial data TX and RX

Selectable 2 / 1 Stop bits

Selectable Even, Odd and No Parity

Parity, Overrun and Framing Error detector

Max transfer rate: 115 Kbps

2

3.7.2

I C

2

●

Standard I C mode (100 KHz) / Fast I C mode (400 KHz)

Master interface only

2

Master functions control all I C bus specific sequencing, protocol, arbitration and timing

Detection of bus errors during transfers

3.8

3.9

General purpose I/Os

6 programmable GP I/Os

Analog to Digital Converter

●

8 bit resolutions

230 Ksps

16 analog input channels (0 - 3.3 V)

INL 1 LSB

DNL 0.5 LSB

Programmable conversion speed - minimum conversion time 4.3 µs

13/71

Features

SPEAR-09-H022

3.10

Real time clock

●

Real time clock-calendar (RTC)

14 digit (YYYY MM DD hh mm ss) precision

Clocked by 32.768 KHz low power clock input

Separated power supply (1.2 V)

3.11

Watchdog timer

●

Programmable 16 bit Watchdog timer with reset output signal (more than 200 system

clock period to initial peripheral devices)

●

Programmable period 1 ~ 10 sec.

For recovery from unexpected system Hang-up

3.12

3.13

General purpose timers

●

Four 16 bit timers with 8 bit prescaler

Frequency range: 3.96 Hz - 66.5 MHz

Operating mode: Auto Reload and Single Shot

Customizable logic

●

200K equivalent ASIC gate (16K LUT equivalent) configurable either custom logic or 32

KBytes single-port SRAM or mixing logic and RAM

●

2 dedicated buses, each of them connected with a 4 channel DMA

8 interrupt lines (level type) available

112 dedicated GP I/Os

Single VIA mask configurable interconnections

Emulation by an external FPGA, keeping on-chip and I/O interfaces

14/71

SPEAR-09-H022

Block diagram

4

Block diagram

Figure 1. Block diagram

C U S T O M E R

I / O s

Dithered

System

Clock

ARM926EJ-S

Real

Time

Clock

VIC

WdT

200K eASIC™ gates

4 GPTs

USB 2.0

Host

+

A

H

B

4 KB

A

P

B

H

I

SRAM

SRAM SRAM

SRAM

G

H

PHY

L

O

W

B

u

s

B

u

s

Programmable

Interface

gDMA0

gDMA1

S

P

E

D

USB 2.0

Host

+

3 UARTs

S

P

E

D

PHY

AHB Bus Matrix

I²C

C

O

N

E

C

T

I

USB 2.0

Device

+

C

O

N

E

C

T

I

Bus

Bridge

6 GP I/Os

PHY

ADC

8 bits,

V

I

V

I

Ethernet

MAC

16 channels

T

Y

Multi-Port

Memory

CTRL

SPI

for

T

Y

ROM, Flash

M E M O R Y

I N T E R F A C E S

AHB

Processor Bus Layer

APB

Master

Slave

Non Processor AHB Layer

15/71

Pin description

SPEAR-09-H022

5

Pin description

5.1

Functional pin groups

With reference to Figure 20. Package schematic -Section 26, here follows the pin list, sorted

by their belonging IP. All supply and ground pins are classified as power signals and

gathered in the Table 2.

Table 1.

Group

Pin description by functional groups

Signal Name

AIN[0]

Ball

Direction

Function

Pin Type

V20

V19

V18

V17

V16

T22

T21

T19

P18

N18

M18

L18

U22

U21

U20

U19

T20

E22

E21

D22

D21

AIN[1]

AIN[2]

AIN[3]

AIN[4]

AIN[5]

AIN[6]

AIN[7]

Input

ADC analog input channel

Analog buffer,

3.3 V capable

ADC

AIN[8]

AIN[9]

AIN[10]

AIN[11]

AIN[12]

AIN[13]

AIN[14]

AIN[15]

TEST_OUT

TEST0

TEST1

TEST2

TEST3

Output ADC output test pad

Test configuration port.

TTL input buffer,

3.3 V capable,

with Pull Down

Input

For the functional mode they have

to be set to 0

DEBUG

eASIC

TTL Schmitt trigger

input buffer,

PLL_BYPASS

H5

Input

I/O

Enable / disable PLL bypass

eASIC general purpose IO

3.3 V capable

eASICGP_IO[0]

eASICGP_IO[1]

E1

F2

TTL bidirectional

buffer,

3.3 V capable,

4 mA drive capability

16/71

SPEAR-09-H022

Pin description

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

Ball

Direction

Function

eASICGP_IO[2]

eASICGP_IO[3]

eASICGP_IO[4]

eASICGP_IO[5]

eASICGP_IO[6]

eASICGP_IO[7]

eASICGP_IO[8]

eASICGP_IO[9]

eASICGP_IO[10]

eASICGP_IO[11]

eASICGP_IO[12]

eASICGP_IO[13]

eASICGP_IO[14]

eASICGP_IO[15]

eASICGP_IO[16]

eASICGP_IO[17]

eASICGP_IO[18]

eASICGP_IO[19]

eASICGP_IO[20]

eASICGP_IO[21]

eASICGP_IO[22]

eASICGP_IO[23]

eASICGP_IO[24]

eASICGP_IO[25]

eASICGP_IO[26]

eASICGP_IO[27]

eASICGP_IO[28]

eASICGP_IO[29]

eASICGP_IO[30]

eASICGP_IO[31]

eASICGP_IO[32]

eASICGP_IO[33]

eASICGP_IO[34]

G3

D1

E2

C1

F3

D2

B1

G4

E3

C2

A1

F4

D3

B2

A2

C3

E4

G5

B3

D4

F5

A3

E5

C4

A4

B4

C5

D5

B5

A5

E6

D6

B6

I/O

TTL bidirectional

buffer,

eASIC

eASIC general purpose IO

3.3 V capable,

4 mA drive capability

17/71

Pin description

SPEAR-09-H022

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

Ball

Direction

Function

eASICGP_IO[35]

eASICGP_IO[36]

eASICGP_IO[37]

eASICGP_IO[38]

eASICGP_IO[39]

eASICGP_IO[40]

eASICGP_IO[41]

eASICGP_IO[42]

eASICGP_IO[43]

eASICGP_IO[44]

eASICGP_IO[45]

eASICGP_IO[46]

eASICGP_IO[47]

eASICGP_IO[48]

eASICGP_IO[49]

eASICGP_IO[50]

eASICGP_IO[51]

eASICGP_IO[52]

eASICGP_IO[53]

eASICGP_IO[54]

eASICGP_IO[55]

eASICGP_IO[56]

eASICGP_IO[57]

eASICGP_IO[58]

eASICGP_IO[59]

eASICGP_IO[60]

eASICGP_IO[61]

eASICGP_IO[62]

eASICGP_IO[63]

eASICGP_IO[64]

eASICGP_IO[65]

C6

A7

A6

C7

B7

E7

D7

E8

A8

B8

C8

D8

B9

A9

TTL bidirectional

buffer,

A10

C9

eASIC

I/O

eASIC general purpose IO

3.3 V capable,

D9

4 mA drive capability

B10

A11

E9

C10

B11

D10

A12

C11

B12

A13

E10

D11

C12

B13

18/71

SPEAR-09-H022

Pin description

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

Ball

Direction

Function

eASICGP_IO[66]

eASICGP_IO[67]

eASICGP_IO[68]

eASICGP_IO[69]

eASICGP_IO[70]

eASICGP_IO[71]

eASICGP_IO[72]

eASICGP_IO[73]

eASICGP_IO[74]

eASICGP_IO[75]

eASICGP_IO[76]

eASICGP_IO[77]

eASICGP_IO[78]

eASICGP_IO[79]

eASICGP_IO[80]

eASICGP_IO[81]

eASICGP_IO[82]

eASICGP_IO[83]

eASICGP_IO[84]

eASICGP_IO[85]

eASICGP_IO[86]

eASICGP_IO[87]

eASICGP_IO[88]

eASICGP_IO[89]

eASICGP_IO[90]

eASICGP_IO[91]

eASICGP_IO[92]

eASICGP_IO[93]

eASICGP_IO[94]

eASICGP_IO[95]

eASICGP_IO[96]

eASICGP_IO[97]

eASICGP_IO[98]

A14

A15

B14

C13

D12

E11

A16

B15

C14

D13

A17

B16

E12

C15

A18

B17

D14

A19

C16

E13

B18

D15

C17

B19

C18

E14

D16

B21

C19

D17

E15

C20

D18

TTL bidirectional

buffer,

eASIC

I/O

eASIC general purpose IO

3.3 V capable,

4 mA drive capability

19/71

Pin description

SPEAR-09-H022

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

Ball

Direction

Function

eASICGP_IO[99]

eASICGP_IO[100]

eASICGP_IO[101]

eASICGP_IO[102]

eASICGP_IO[103]

eASICGP_IO[104]

eASICGP_IO[105]

eASICGP_IO[106]

eASICGP_IO[107]

eASICGP_IO[108]

eASICGP_IO[109]

eASICGP_IO[110]

eASICGP_IO[111]

eASIC_EXT_CLOCK

E16

D19

E17

D20

E18

E19

F18

E20

F20

F19

G19

G20

G18

H18

TTL bidirectional

buffer,

eASIC general purpose IO

3.3 V capable,

4 mA drive capability

I/O

eASIC

eAISC Program Interface out

clock

TTL bidirectional

buffer,

eASIC_PI_CLOCK

eASIC_CLK

R18

G2

3.3 V capable,

eASIC output clock

8 mA drive capability

TTL input buffer,

3.3 V capable

with Pull Down

CONFIG_DEVEL

A20

Input

External FPGA emulation mode

TX_CLK

TXD[0]

TXD[1]

TXD[2]

TXD[3]

TX_EN

CRS

H19

J18

J19

K18

J20

J21

J22

K19

K20

K21

K22

L19

L20

L21

L22

Ethernet input TX clock

Ethernet TX output data

Output

Ethernet TX enable

TTL bidirectional

buffer,

Carrier sense input

3.3 V capable,

Ethernet COL

RX_CLK

Collision detection input

Ethernet input RX clock

4 mA drive capability,

with Pull Down

Input

RXD[0]

RXD[1]

RXD[2]

RXD[3]

RX_DV

RX_ER

Ethernet RX input data

Input

Data valid on RX

Data error detected

20/71

SPEAR-09-H022

Pin description

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

Ball

Direction

Function

TTL bidirectional

buffer,

3.3 V capable,

MDC

M19

Output Output timing reference for MDIO

Ethernet

4 mA drive capability,

with Pull Down

MDIO

M20

R22

R21

R20

R19

P22

P21

M21

I/O

I/O data to PHY

GP_IO[0]

GP_IO[1]

GP_IO[2]

GP_IO[3]

GP_IO[4]

GP_IO[5]

SDA

TTL bidirectional

buffer,

GPI/Os

General Purpose IO

3.3 V capable,

8 mA drive capability

TTL bidirectional

buffer,

I²C serial data

3.3 V capable,

I²C

I/O

SCL

TDO

M22

A21

4 mA drive capability,

with Pull Up

TTL bidirectional

buffer,

Output Jtag TDO

3.3 V capable,

4 mA drive capability

TDI

A22

B20

B22

C21

C22

T1

Input

Jtag TDI

JTAG

TTL bidirectional

buffer,

TMS

Jtag TMS

3.3 V capable,

RTCK

TCK

Output Jtag output clock

Input Jtag clock

Output Jtag reset

4 mA drive capability,

with Pull Up

nTRST

MCLK_in

MCLK_out

Input

12 MHz input crystal

Oscillator

MASTER

CLOCK

3.3 V capable

U1

Output 12 MHz output crystal

TTL Schmitt trigger

input buffer,

MASTER

RESET

MRESET

H4

Input

I/O

Master reset

3.3 V capable

MPMCDATA[0]

MPMCDATA[1]

MPMCDATA[2]

MPMCDATA[3]

MPMCDATA[4]

MPMCDATA[5]

AA12

Y12

LVTTL / SSTL

ClassII bidirectional

buffer

W12

AB13

AA13

Y13

MPMC

DDR / SDRAM data

21/71

Pin description

SPEAR-09-H022

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

MPMCDATA[6]

Ball

Direction

Function

W13

AA14

AA16

AB18

AB19

AB20

AB21

AA21

AB22

AA22

AA18

AA17

Y22

MPMCDATA[7]

MPMCDATA[8]

MPMCDATA[9]

MPMCDATA[10]

MPMCDATA[11]

MPMCDATA[12]

MPMCDATA[13]

MPMCDATA[14]

MPMCDATA[15]

MPMCDATA[16]

MPMCDATA[17]

MPMCDATA[18]

MPMCDATA[19]

MPMCDATA[20]

MPMCDATA[21]

MPMCDATA[22]

LVTTL / SSTL

ClassII bidirectional

buffer

I/O

DDR / SDRAM data

Y21

Y20

Y19

Y18

TTL bidirectional

buffer,

MPMC MPMCDATA[23]

MPMCDATA[24]

Y17

I/O

SDRAM data

3.3 V capable,

Y16

8 mA drive capability

MPMCDATA[25]

W22

W21

W20

W19

W18

W17

W16

AB8

AA8

Y8

MPMCDATA[26]

MPMCDATA[27]

MPMCDATA[28]

MPMCDATA[29]

MPMCDATA[30]

MPMCDATA[31]

MPMCADDROUT[0]

MPMCADDROUT[1]

MPMCADDROUT[2]

MPMCADDROUT[3]

MPMCADDROUT[4]

MPMCADDROUT[5]

MPMCADDROUT[6]

MPMCADDROUT[7]

MPMCADDROUT[8]

W8

LVTTL / SSTL

ClassII bidirectional

buffer

AB9

AA9

Y9

Output DDR / SDRAM data

W9

AB10

22/71

SPEAR-09-H022

Pin description

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

Ball

Direction

Function

MPMCADDROUT[9]

MPMCADDROUT[10]

MPMCADDROUT[11]

MPMCADDROUT[12]

MPMCADDROUT[13]

MPMCADDROUT[14]

nMPMCDYCSOUT[0]

nMPMCDYCSOUT[1]

nMPMCDYCSOUT[2]

nMPMCDYCSOUT[3]

MPMCCKEOUT[0]

MPMCCKEOUT[1]

MPMCCLKOUT[0]

AA10

Y10

W10

AB11

AA11

Y11

DDR / SDRAM data

LVTTL / SSTL

ClassII bidirectional

buffer

AB6

AA6

DDR / SDRAM chip select

Y6

W6

W11

AB12

AB17

AB16

AB15

AB14

Y14

DDR / SDRAM clock enable

output

DDR / SDRAM output clock 1

DDR / SDRAM output clock 1 neg.

DDR / SDRAM output clock 2

DDR / SDRAM output clock 2 neg.

LVTTL / SSTL

ClassII bidirectional

Output

nMPMCCLKOUT[0]

MPMCCLKOUT[1]

differential

buffer

MPMC

nMPMCCLKOUT[1]

MPMCDQMOUT[0]

LVTTL / SSTL

ClassII bidirectional

buffer

DDR / SDRAM data mask out

MPMCDQMOUT[1]

MPMCDQMOUT[2]

W15

AA19

TTL bidirectional

buffer,

SDRAM data mask out

DDR data strobe

3.3 V capable,

MPMCDQMOUT[3]

AA20

8 mA drive capability

MPMCDQS[0]

AA15

Y15

Y7

MPMCDQS[1]

LVTTL / SSTL

ClassII bidirectional

buffer

nMPMCCASOUT

nMPMCRASOUT

nMPMCWEOUT

DDR / SDRAM CAS output strobe

DDR / SDRAM write enable

AA7

AB7

Voltage reference

SSTL / CMOS mode.

Analog buffer, 3.3 V

capable

SSTL_VREF

W14

Input

This pin is used both as logic state

and as power supply

RTCXO

RTCXI

AB5

AB4

Output 32 KHz output crystal

Input 32 KHz input crystal

Oscillator 1.2 V

capable

RTC

SMI

TTL bidirectional

buffer,

SMINCS[0]

G22

Output Serial Flash chip select

3.3 V capable,

4 mA drive capability

23/71

Pin description

SPEAR-09-H022

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

SMINCS[1]

Ball

Direction

Function

G21

F22

TTL bidirectional

buffer,

SMINCS[2]

SMINCS[3]

Serial Flash chip select

3.3 V capable,

F21

4 mA drive capability

TTL bidirectional

buffer,

SMICLK

H20

Output Serial Flash output clock

3.3 V capable,

8 mA drive capability

SMI

TTL bidirectional

buffer,

3.3 V capable,

SMIDATAIN

SMIDATAOUT

UART1_RXD

UART1_TXD

UART2_RXD

UART2_TXD

UART3_RXD

UART3_TXD

H21

H22

N19

N20

N21

N22

P19

P20

Input

Serial Flash data in

8 mA drive capability,

with Pull Up

TTL bidirectional

buffer,

Output Serial Flash data out

3.3 V capable,

8 mA drive capability

TTL bidirectional

buffer,

3.3 V capable,

Input

Uart1 RX data

4 mA drive capability,

with Pull Down

TTL bidirectional

buffer,

Output Uart1 TX data

3.3 V capable,

4 mA drive capability

TTL bidirectional

buffer,

3.3 V capable,

Input

Uart2 RX data

4 mA drive capability,

with Pull Down

UARTs

TTL bidirectional

buffer,

Output Uart2 TX data

3.3 V capable,

4 mA drive capability

TTL bidirectional

buffer,

3.3 V capable,

Input

Uart3 RX data

4 mA drive capability,

with Pull Down

TTL bidirectional

buffer,

Output Uart3 TX data

3.3 V capable,

4 mA drive capability

24/71

SPEAR-09-H022

Pin description

Pin Type

Table 1.

Group

Pin description by functional groups (continued)

Signal Name

DMNS

Ball

Direction

Function

W1

V1

P1

N1

L1

I/O

D - port of USB device

D + port of USB device

D - port of USB host1

D + port of USB host1

D - port of USB host2

D + port of USB host2

DPLS

HOST1_DP

HOST1_DM

HOST2_DP

HOST2_DM

HOST1_VBUS

Analog buffer, 5 V

tolerant

K1

H2

Output USB host1 VBUS signal

TTL bidirectional

buffer,

3.3 V capable,

HOST2_VBUS

H1

Output USB host2 VBUS signal

4 mA drive capability

TTL bidirectional

buffer,

USBs

3.3 V capable,

OVERCURH1

G1

I/O

USB host1 overcurrent

USB host2 overcurrent

4 mA drive capability,

with Pull Down

TTL bidirectional

buffer,

OVERCURH2

F1

3.3 V capable,

4 mA drive capability

TTL bidirectional

buffer,

3.3 V capable,

VBUS

RREF

H3

K5

I/O

USB device VBUS signal

USB reference resistor

4 mA drive capability,

with Pull Down

Analog buffer,

3.3 V capable

Input

Table 2.

Group

Pins belonging to POWER group

Signal Name

vdde3v3

Ball

Function

Note ⁽¹⁾

Note ⁽²⁾

Note ⁽³⁾

Note ⁽⁴⁾

Note ⁽⁵⁾

V22

Digital 3.3 V power

vdd

Digital 1.2 V power

gnde

Digital ground

vdd2v5

thermal_gnd

DDR / SDR digital 3.3 / 2.5V power

Thermal Pad

POWER anavdd_3v3_adc

anagnd_3v3_adc

VREFP_adc

Dedicated ADC 3.3 V power

Dedicated ADC ground

ADC positive reference Voltage

ADC pegative reference Voltage

U18

V21

VREFN_adc

T18

vdd_dith

W7

DDR / SDR dedicated digital PLL 3.3 V power

DRR / SDR dedicated digital PLL ground

vss_dith

V7

25/71

Pin description

SPEAR-09-H022

Table 2.

Group

Pins belonging to POWER group (continued)

Signal Name

Ball

Function

Voltage reference SSTL / CMOS mode.

SSTL_VREF

W14

This pin is used both as logic state and as power supply

1.2 V dedicated power for RTC

Dedicated digital ground for RTC

Dedicated USB PLL analog 3.3 V power

Dedicated USB PLL analog ground

Dedicated USB PLL digital 1.2 V power

Dedicated USB PLL digital ground

Dedicated USB 1.2 V power

Dedicated USB 3.3 V power

Dedicated USB ground

vdd1v2_date_osci

vdd_date_osci

gnd_date_osci

gnde_date_osci

anavdd_3v3_pll1600

anagnd_3v3_pll1600

digvdd_1v2_pll1600

diggnd_1v2_pll1600

vddl_1v2_d

AB2

AA5

AA4

AB3

R2

P4

R4

U2

W3

U4

U3

P2

N5

N3

L4

vddb_1v2_d

vddc_1v2_d

vdd_usb

vddc_1v2_h1

vddb_1v2_h1

vddl_1v2_h1

vddc_1v2_h0

vddb_1v2_h0

vddl_1v2_h0

vdd3_3v3_d

K4

K3

J4

POWER

W4

P5

L3

vdde3v3_usb

vdd3_3v3_h1

vdd3_3v3_h0

vssl_3v3_d

J3

W5

W2

U5

R3

N4

N2

M2

J2

vssb_1v2_d

Dedicated USB ground

vssc_1v2_d

Dedicated USB ground

gnde_usb

Dedicated USB ground

gnd_usb

Dedicated USB ground

vssc_1v2_h1

vssb_1v2_h1

vssl_3v3_h0

vssl_3v3_h1

vssb_1v2_h0

vssc_1v2_h0

Dedicated USB ground

L2

Dedicated USB ground

J5

Dedicated USB ground

K2

Dedicated USB ground

1. Signal spread on the following balls: F7, F8, F9, F12, F13, F14, F17, G17 H6, J6, K17, L17, M6, N6, P6, P17, R17, U6, U16.

2. Signal spread on the following balls: F6, F10, F11, F15, F16, G6, H17, J17, K6, L6, M17, N17, R6, T6, T17, U17, V8, V15..

3. Signal spread on the following balls: J9 to J14, K9 to K14, L9 to L14, M9 to M14, N9 to N14, P9 to P14.

4. Signal spread on the following balls: U7 to U15

5. Signal spread on the following balls: L5, M3, M4, M5, R1, R5, T2 to T5.

26/71

SPEAR-09-H022

Pin description

5.2

Special I/Os

5.2.1

USB 2.0 Transceiver

SPEAr Head has three USB 2.0 UTMI + Multimode ATX transceivers. One transceiver will

be used by the USB Device controller, and two will be used by the Hosts. These are all

integrated into a single USB three-PHYs macro.

5.2.2

DRAM

Data and address buses of Multi-Port Memory Controller used to connect to the banks

memory are constituted of programmable pins.

27/71

Memory map

SPEAR-09-H022

6

Memory map

Table 3.

START

Memory map

END

PERIPHERAL

NOTES

ADRESS

ADDRESS

0x0000_0000

0x1000_0000

0x1000_8000

0x1000_9000

0x1000_A000

0x1000_B000

0x1000_C000

0x1000_D000

0x1000_E000

0x1000_F000

0x1000_F400

0x03FF_FFFF Serial Memory

0x0FFF_FFFF DRAM

64 MB (on reset before the remap)

256 MB

0x1000_07FF USB Device

0x1000_8FFF USB Device Plug Detect

0x1000_9FFF USB Host 1 EHCI

0x1000_AFFF USB Host 1 OHCI

0x1000_BFFF Vectored Interrupt CTRL

0x1000_CFFF DRAM CTRL (MPMC)

0x1000_DFFF USB Host 2 EHCI

0x1000_EFFF USB Host 2 OHCI

0x1000_F3FF Serial Memory CTRL

0x11FF_FFFF Default Slave

APB Control Status

0x1200_0FFF

0x1200_0000

Register

0x1200_1000

0x1200_2000

0x1200_1FFF GPT 0 and GPT 1

0x1200_2FFF GPT 2 and GPT 3

General Configuration

0x1200_3FFF

0x1200_3000

Registers

0x1200_4000

0x1200_5000

0x1200_6000

0x1200_7000

0x1200_8000

0x1200_9000

0x1200_A000

0x1200_B000

0x1200_C000

0x1200_D000

0x1200_E000

0x1210_0000

0x1200_4FFF WdT

0x1200_5FFF RTC

0x1200_6FFF GPIO 0 → GPIO 5

0x1200_7FFF I²C

0x1200_8FFF UART 1

0x1200_9FFF UART 2

0x1200_AFFF UART 3

0x1200_BFFF ADC

0x1200_CFFF gDMA 1

0x1200_DFFF gDMA 2

0x120F_FFFF Default Slave

0x12FF_FFFF Default Slave

eASIC™

0x1300_03FF

0x1300_0000

0x1300_0400

Programmable Interface

0x13FF_FFFF Default Slave

28/71

SPEAR-09-H022

Memory map

Table 3.

START

Memory map (continued)

END

PERIPHERAL

NOTES

ADRESS

ADDRESS

0x1400_0000

0x1600_0000

0x15FF_FFFF Ethernet MAC

0x19FF_FFFF Serial Memory

64 MB (on reset after the remap)

(maximum addressable size

available for the set of the full

master and the 2 slaves is 1.5 GB)

0x1A00_0000

0x2000_0000

0x1FFF_FFFF Default Slave

eASIC™ AHB

0x7FFF_FFFF

SUBSYSTEM

Write transactions on the APB Bus are all considered 32 bit wide unless otherwise stated.

All the access to the Default Slave will cause an abort exception.

Memory map is repeated starting from the address 0x8000_0000.

29/71

Power on sequence

SPEAR-09-H022

7

Power on sequence

7.1

SPEAr Head200 software architecture

7.1.1

Boot process

Memory mapping

A major consideration in the design of an embedded ARM application is the layout of the

memory map, in particular the memory that is situated at address 0x0. Following reset, the

core starts to fetch instructions from 0x0, so there must be some executable code

accessible from that address. In an embedded system, this requires ROM to be present, at

least initially.

Serial Flash at 0x0

The SPEAr Head200 has been designed to use the REMAP concept into its AHB primary

bus decoder. The decoder selection for the initial address range (first 64 MB) is conditioned

with the content of an AHB remap register, which can be programmed by software at any

time.

The Serial Flash memory space is accessible in the address range 0x9600_0000 -

0x99FF_FFFF (64 MB), with or without remap.

At reset, the Serial Flash memory is 'aliased' at 0x0, which means that the AHB decoder

selects the Serial Flash space when accessing the address range 0x0000_0000 to

0x03FF_FFFF. Please note that DRAM is unreachable in this state.

Table 4.

Memory mapping at reset (REMAP = 0)

ADDRESS RANGE

SIZE [MB]

DESCRIPTION

0x9600_0000 - 0x99FF_FFFF

0x0000_0000 - 0x03FF_FFFF

64

Serial Flash

Serial Flash (remap)

DRAM at 0x0

After reset, the boot program makes the remapping, so that the system will be able to

access the complete 256 MB of logic memory space associated to DRAM in the range

0x0000_0000 - 0x0FFF_FFFF.

Table 5.

Memory Mapping after reset after remapping

ADDRESS RANGE

SIZE [MB]

DESCRIPTION

0x9600_0000 - 0x99FF_FFFF

0x0000_0000 - 0x0FFF_FFFF

64

Serial Flash

DRAM

256

30/71

SPEAR-09-H022

Power on sequence

7.1.2

Booting sequence

A simple initial description of the boot process is showed in the following steps:

1. Power on to fetch the RESET vector at 0x0000_0000 (from the aliased-copy of Serial

Flash).

2. Perform any critical CPU initialization at this time.

3. Load into the Program Counter (PC) the address of a routine that will be executed

directly from the non-aliased mapping of Serial Flash (0x9600_0000 + addr_of_routine)

and which main objectives are:

–

un-map the aliased-copy of the Serial Flash (set REMAP = 1)

copy the program text and data into DRAM.

4. Returning from this routine will set the Program Counter back to DRAM.

31/71

ARM926EJ-S

SPEAR-09-H022

8

ARM926EJ-S

The processor is the powerful ARM926EJ-S, targeted for multi-tasking applications.

Belonging to ARM9 general purposes family microprocessor, it principally stands out for the

Memory Management Unit, which provides virtually memory features, making it also

compliant with WindowsCE, Linux and SymbianOS operating systems.

The ARM926EJ-S supports the 32 bit ARM and 16 bit Thumb instruction sets, enabling the

user to trade off between high performance and high code density and includes features for

efficient execution of Java byte codes.

Besides, it has the ARM debug architecture and includes logic to assist in software debug.

Its main features are:

●

f

266 MHz (downward scalable)

MAX

MMU

32 KB of instruction CACHE

16 KB of data CACHE

8 KB of instruction TCM (Tightly Coupled Memory)

8 KB of data TCM

AMBA Bus interface

Coprocessor interface

JTAG

ETM9 (Embedded Trace Macro-cell) for debug; large size version.

Figure 2. ARM926EJ-S block diagram

32/71

SPEAR-09-H022

Clock and reset system

9

Clock and reset system

9.1

Overview

The Clock System block is a fully programmable block able to generate all clocks necessary

at the chip, except for USB 2.0 Host and Device controllers, which have a dedicated PLL.

The clocks, at default operative frequency, are:

●

clock @ 266 MHz for ARM system

●

clock @ 133 MHz for AHB Bus and AHB peripherals, eASIC MacroCell and Bus Bridge

included

●

clock @ 66.5 MHz for, APB Bus and APB peripherals, Bus Bridge included

clock @ 20 MHz for eASIC Programmable Interface

The frequencies are the maximum allowed value and the user can modify them by

programming dedicated registers.

The Clock System consists of 2 main parts: a Multi-Clock Generator block and an internal

PLL.

The Multi-Clock Generator block, starting from a reference signal (which generally is

delivered from the PLL), generates all clocks for the IPs of SPEAr Head200 according to

dedicated programmable registers.

The PLL, starting from the oscillator input of 12 MHz, generates a clock signal at a

frequency corresponding at the highest of the chip, which is the reference signal used by the

Multi-Clock Generator block to obtain all chip clocks. Its main features is the Electro-

Magnetic Interference reduction capability: user has the possibility to set up the PLL in order

to add a triangular wave to the VCO clock; the resulting signal will have the spectrum (and

the power) spread on a small range (programmable) of frequencies centred on F0 (VCO

Freq.), obtaining minimum electromagnetic emissions. This method replace all the other

traditional methods of E.M.I. reduction, as filtering, ferrite beads, chokes, adding power

layers and ground planets to PCBs, metal shielding etc., allowing sensible cost saving for

customers.

There are 3 operating modes:

–

Normal mode: the Clock System delivers signals at the operative frequency. The

reference signal of the Multi-Clock Generator block is that generated by PLL

–

Pseudo-Functional mode: in this mode PLL is bypassed and the reference signal

is delivered from off-chip. The generated clocks are coherent with programmed

registers.

The purpose of Pseudo-Functional mode is let the rest of the chip properly work in

case of PLL failure.

This mode is set by assigning the following logic state to the Test pins:

TEST0 → 1

TEST1 → 0

TEST2 → 0

TEST3 → 0

–

Debug mode: is the operating state when the ARM is in Debug mode. The block

works as in Normal Mode but, APB peripheral clocks, eASIC clock and eASIC PI

clock are gated

33/71

Clock and reset system

Figure 3. Clock system block interfaces

SPEAR-09-H022

MCLK_out

MCLK_in

CLOCK

PLL_BYPASS

SYSTEM

internal clocks

MRESET

The I/O signals accessible from off-chip are listed in Table 6 Clock System I/O off-chip

interfaces:

Table 6.

Clock system I/O off-chip interface

SIGNALS

DIRECTION

SIZE [bit]

DESCRIPTION

MCLK_in

Input

1

Oscillator input (12 MHz)

PLL_BYPASS

External clock in Test mode

Oscillator output. It supplies the

signal MCLK_in inverted

MCLK_out

MRESET

Output

Input

1

Asynchronous reset

34/71

SPEAR-09-H022

Clock and reset system

9.2

Reset and PLL change parameters sequence

Figure 4 shows a simplified flow chart of clock system FSM.

The system remains in an IDLE state until RESET signal is asserted: RESET → 0.

When RESET = 0 the FSM change state and reaches the PLL PWR-UP state; when PLL

locks (PLL_LOCK = 1), means that the PLL_OUT signal oscillates at 264 MHz and the PLL

starts to work, so that the FSM advances in the next states.

In CLOCK ENABLED state the clocks can propagate in the system; then the FSM goes in

SYSTEM ON state; it remains in this state in the normal chip working.

Figure 4. State machine of clock system

To reach at a clock frequency of 266 MHz, PLL had to be appropriately programmed

because this frequency isn't an integer multiple of 12 MHz.

After this programming, the FSM stops all the clocks and exits from SYSTEM ON state

proceeding in PLL SETTING state; here the new parameters are stored in the PLL.

If the PLL isn't in Dithered mode the FSM waits for PLL lock, going in LOCK WAIT state, and

then will reach SYSTEM ON state when PLL locks.

If the PLL is in Dithered mode, the lock signal loses his meaning and there's no need to wait

for PLL lock, so the FSM jumps directly from PLL SETTING to SYSTEM ON.

When FSM is in SYSTEM ON, all clocks are enabled.

35/71

Clock and reset system

SPEAR-09-H022

9.3

Crystal connection

The crystal will be connected to the chip as shown in the following schematic.

Figure 5. Oscillator board schematic

22 pF

MCLK_in

Crystal

1 MOhm

MCLK_out

10 pF

The chip will only be used with a crystal (not a ceramic resonator). The Figure 6 Model for

crystal details the model used and the Table 7 Parameters for 12 MHz Crystal specifies the

parameters for the crystal.

Figure 6. Model for crystal

L1

C1

C0

R1

Table 7.

#

Parameters for 12 MHz crystal

L1 (uH)

C1 (fF)

R1 (Ohm)

C0 pF)

Notes:

Model 1

Model 2

Model 3

Model 4

6200

7500

470

15.7

13.2

10

15

7

3.3

94.6

14.5

12.45

11.6

2.75

17465

10.08

11.9965MHz Taitien

36/71

SPEAR-09-H022

Vectored interrupt controller

10

Vectored interrupt controller

10.1

Overview

The Vector Interrupt Controller provides a software interface to interrupt system, in order to

determine the source that is requesting a service and where the service routing is loaded.

It supplies the starting address, or vector address, of the service routine corresponding to

the highest priority requesting interrupt source.

In an ARM system 2 level of interrupt are available:

–

Fast Interrupt Request (FIQ) for low latency interrupt handling

Interrupt Request (IRQ) for standard interrupts

Generally, you only use a single FIQ source at a time to provide a true low-latency interrupt.

This has the following benefits:

●

You can execute the interrupt service routine directly without determining the source of

the interrupt

●

It reduces interrupt latency. You can use the banked registers available for FIQ

interrupts more efficiently, because you do not require a context save

The interrupt inputs must be level sensitive, active HIGH, and held asserted until the

interrupt service routine clears the interrupt. Edge-triggered interrupts are not compatible.

The interrupt inputs do not have to be synchronous to AHB clock.

The main features of Vectored Interrupt Controller are:

●

Compliance to AMBA Specification Rev. 2.0

IRQ and FIQ interrupt generation

AHB mapped for faster interrupt

Hardware priority

Support for 32 standard interrupts

Support for 16 vectored interrupts

Software interrupt generation

Interrupt masking

Interrupt request status.

Since 32 interrupts are supported, there are 32 interrupt input lines, coming from different

sources. They are selected by a bit position and the software controls every line to generate

software interrupts; it can generate 16 vectored interrupts. A vectored interrupt can generate

only an IRQ interrupt.

The interrupt priority is controlled by hardware and it is as follow:

1. FIQ interrupt

2. Vectored IRQ interrupt. The higher priority is 0; the lower is 15

3. Non vectored IRQ interrupt

37/71

Vectored interrupt controller

SPEAR-09-H022

10.2

Vector interrupt controller flow sequence

The following procedure shows the sequence for the vectored interrupt flow:

1. An interrupt occurs

2. The CPU branches to either the IRQ or FIQ Interrupt Vector

3. If the Interrupt is an IRQ, CPU read the VICVectAddr register and branch to the

interrupt service routine. This can be done using a LDR PC instruction. Reading the

VICVectAddr register updates the interrupt controllers hardware priority register

4. Stack the Workspace so that the IRQ interrupts can be re-enabled

5. Enable the IRQ interrupts so that a higher priority can be serviced

6. Execute the Interrupt Service Routine (ISR)

7. Clear the Requesting Interrupt in the peripheral, or write to the VICSoftIntClear register

if the request was generated by a software interrupt

8. Disable the Interrupts and Restore the Workspace

9. Write to the VICVectAddr register. This clears the respective interrupt in the internal

interrupt priority

10. Return from the interrupt. This re-enables the interrupts

10.3

Simple interrupt flow sequence

The following procedure shows the sequence for the simple interrupt flow:

1. An interrupt occurs

2. Branch to IRQ or FIQ interrupt vector

3. Branch to the Interrupt Handler

4. Interrogate the VICIRQStatus register to determine which source generated the

interrupt, and prioritize the interrupts if there are multiple active interrupt sources. This

takes a number of instructions to compute

5. Branch to the correct ISR

6. Execute the ISR

7. Clear the interrupt. If the request was generated by a software interrupt, the

VICSoftIntClear register must be written too

8. Check the VICIRQStatus register to ensure that no other interrupt is active. If there is

an active request go to Step 4

9. Return from Interrupt

38/71

SPEAR-09-H022

Vectored interrupt controller

10.4

Interrupt sources in SPEAr Head200

Table 8.

Interrupt sources in SPEAr Head200

SOURCE

INTERRUPT LINE

0

eASIC0

eASIC1

eASIC2

eASIC3

SMI

1

2

3

4

5

RTC

6

USB HOST 1 – OHCI

USB HOST 2 – OHCI

USB HOST 1 – EHCI

USB HOST 2 – EHCI

USB DEVICE

MAC

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

I²C

GPT4

GPT3

gDMA1

gDMA0

GPT2

GPT1

UART2

UART1

UART0

ADC

Reserved

eASIC4

eASIC5

eASIC6

eASIC7

39/71

DMA controller block

SPEAR-09-H022

11

DMA controller block

SPEAr Head200 has 2 DMA Controllers used to transfer data between aASIC MacroCell

and memory.

A DMA Controller can service up to 4 data streams at one time; a data transfer consists of a

sequence of a DMA data packet transfers. There are two types of a data packet transfer

●

one is from the source to the DMA Controller

●

one other is from DMA Controller to the destination.

Each DMA Controller has an AHB Master interface to transfer data between DMA Controller

and either a source or a destination, and has an APB Slave interface used to program its

registers.

11.1

Functional description

Figure 7. DMA block diagram

As a DMA requests are received, the Request Logic will arbiter between them and set the

channel request signal. When a channel request is asserted, the State Machine starts a

data transfer: first a data packet is transferred from a source to the DMA channel and then

from the FIFO to the destination.

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DMA controller block

11.2

DMA control state machine

Figure 8. DMA State Machine diagram

The DMA control SM is always reset into the IDLE state.

As a channel request is asserted, SM moves to READ state and the AHB Master will start a

data packet transfer; SM selects appropriate source address.

When SM is in WRITE state, it selects the destination address and the data width from the

Data Stream register and the AHB Master will transfer all data from the FIFO to the

destination.

When the AHB Master has transferred the data packet, it asserts a Packend signal and the

SM will move to the next state, which depends on the channel request signals.

The state transitions from the READ or WRITE states can occur only when a whole data

packet has been transferred.

Figure 9. Data packet transfer

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Multi-Port Memory Controller

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12

Multi-Port Memory Controller

12.1

Overview

The DRAM interface is controlled by the on-chip Multi-Port Memory Controller.

Its main features are:

●

Supports for SDRAM up to 32 bit wide

Supports for DDR up to 16 bit wide

Maximum clock frequency 133 MHz

8 AHB port connections

4 chip selects

Total addressable memory: 256 MB

Maximum memory bank size: 64 MB

Read and Write buffers to reduce latency

Programmable timings

Table 9.

Supported memory cuts

SIZE [MB]

BANK NUMBER

ROW LENGTH

COLUMN LENGTH

16 (2 MB x 8 bits)

2

4

11

12

11

12

13

9

8

16 (1 MB x 16 bits)

64 (8 MB x 8 bits)

9

64 (4 MB x 16 bits)

64 (2 MB x 32 bits)

128 (16 MB x 8 bits)

128 (8 MB x 16 bits)

128 (4 MB x 32 bits)

256 (32 MB x 8 bits)

256 (16 MB x 16 bits)

256 (8 MB x 32 bits)

512 (64 MB x 8 bits)

512 (32 MB x 16 bits)

8

10

9

8

10

9

8

11

10

Table 10. Multi-Port Memory Controller AHB port assignment

PORT

SIZE [bit]

PRIORITY

MASTER

0

1

2

3

32

-

Max

Bus Matrix

Reserved

32

eASIC™

USB 2.0 Device

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Multi-Port Memory Controller

Table 10. Multi-Port Memory Controller AHB port assignment (continued)

PORT

SIZE [bit]

PRIORITY

MASTER

4

5

6

7

32

USB 2.0 Host 1

USB 2.0 Host 2

Ethernet MAC

Min.

Main AHB System Bus

The table is compiled in decreasing order of priority.

The I/O interfaces accessible from off-chip are listed here:

Table 11. Multi-Port Memory Controller off-chip interfaces

SIGNAL

MPMCDQS

DIRECTION

SIZE [bit]

DESCRIPTION

Input

Bidirectional

Output

2

32

2

Data Strobe

MPMCDATA

Read / write data

DRAM clock

MPMCCLKOUT

nMPMCCLKOUT

MPMCCKEOUT

MPMCDQMOUT

nMPMCRASOUT

nMPMCCASOUT

nMPMCWEOUT

nMPMCDYCSOUT

MPMCADDROUT

Output

2

DRAM inverted clock

DRAM clock enable

Data mask

2

4

1

RAS (active low)

CAS (active low)

Write Enable (active low)

Chip Select (active low)

Address

1

4

15

Voltage reference SSTL / CMOS mode:

SSTL → 1.25 V

SSTL_VREF

Input

1

CMOS → 0 V

This pin is used both as logic state and as

power supply.

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Multi-Port Memory Controller

SPEAR-09-H022

12.2

MPMC DELAY LINES

As shown in Figure 10, there are 4 DLLsp.

The CLOCKOUT delay line is used to tuner the clock driven from MPMC to external DRAM

to match setup / hold constraints on external memory. This Delay Lines is used in the "clock

delay methodology" suitable for SDRAM memory.

The AHB Bus Delay Lines delays the DRAM command signal (ADDR, CAS, RAS, ...) to

capture easily read data from DRAM; this technique is called "command delay".

The DQSINL and DQSINH Delay Lines delay respectively the DQS0 (least 8 bit data strobe)

and DQS1 (highest 8 bit of data strobe) signals coming from DDR.

Only the least 7 bits of these registers are significant because the Delay Lines programming

parameter can vary from 0 to 127.

Figure 10. MPMC DLL

AHB Bus clock

HCLK_DLY

ADDR, CAS, RAS, WE, ..

HCLK

DLL

DRAM

COMMAND

DRIVER

DATA_OUT

DDR

CLOCKOUT

DLL

MPMC

SDR

DDR

DATA_IN

DQS

DQSINL

DQSINU

DLL

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Multi-Port Memory Controller

12.3

SSTLL PAD CONFIGURATION

The Stub Series-Terminated Logic (SSTL) interface standard is intended for high-speed

memory interface applications and specifies switching characteristics such that operating

frequencies up to 200 MHz are attainable.

The primary application for SSTL devices is to interface with SDRAMs.

In SPEAr Head200 SSTL pads are used for pins:

●

MPMCDATA[15:0]

MPMCADDROUT

MPMCCLKOUT

nMPMCCLKOUT

To enable the 2.5V SSTL mode the least significant bit has to be set to 0; when this bit is

sets to 1 the 3.3V CMOS mode is enabled.

It is also possible to program the pad output impedance. Each pad has two configurable

inputs to change output impedance: ZOUTPROGB and ZOUTPROGA.

Below the table to configure output impedance:

Table 12. Output impedance configuration

OUTPUT BUFFER

ZOUTPROGA

ZOUTPROGB

IMPEDANCE

0

1

0

1

0

1

25Ω

35Ω

45Ω

55Ω

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SPI memories

SPEAR-09-H022

13

SPI memories

13.1

Overview

SPEAr Head200 supports the SPI memory devices Flash and EEPROM.

SPI controller, also called Serial Memory Interface (SMI), provides an AHB slave interface to

SPI memories and allows CPU to use them as data storage or code execution.

Main features are

●

SPI master type

Up to 20 MHz clock speed in Standard Read mode and 50 MHz in Fast Read mode

4 chips select

Up to 16 MBytes address space per bank

Selectable 3 Byte addressing for Flash and 2 Byte addressing for EEPROM

Programmable clock prescaler

External memory boot mode capability

32, 16 or 8 bit AHB interface

Interrupt request on write complete or software transfer complete

The compatible SPI memories are:

–

STMicroelectronics M25Pxxx, M45Pxxx

STMicroelectronics M95xxx except M95040, M95020 and M95010

ATMEL AT25Fxx

YMC Y25Fxx

SST SST25LFxx

The I/O interfaces accessible from off-chip are listed here:

Figure 11. SPI Interfaces

SMINCS

SMICLK

SPI

SMIDATAIN

SMIDATAOUT

Table 13. SPI signal interfaces description

Signal

SMIDATAIN

Direction

Size [bit]

Description

Memory output

Input

1

4

SMIDATAOUT

SMICLK

Output

Memory input

Memory clock

SMINCS

Bankchip selects (active low)

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SPEAR-09-H022

SPI memories

At power on the boot code is enabled from the static memory Bank0 by default; this has to

be a Flash bank memory. Moreover, at power on, the memory clock signal is 19 MHz, the

Release Deep Power-Down is 29 µs and the base address for external memories is 0.

13.2

SMI description

The main components of the SMI are two:

–

The SMI CLOCK PRESCALER, which sets-up the memory clock

The SMI DATA PROCESSING & CONTROL, which is the logic controlling the

transfer of the data

Figure 12. Block diagram

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SPI memories

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13.2.1

Transfer rules

The following rules apply to the access from the AHB to the SPI Controller:

●

Endianness is fixed to Little-Endian

SPLIT / RETRY responses are not supported

Bursts must not cross bank boundaries

Size of data transfers for memories can be byte / half-word / word

Size of data transfers for registers must be 32 bit wide

Read Requests: all types of BURST are supported. Wrapping bursts take more time

than incrementing bursts, as there is a break in the address increment

●

Write Requests: wrapping bursts are not supported, and provoke an ERROR response

on HRESP

When BUSY transfer: the SPI Controller is held until busy is inactive

If instead of Flash memories are used EEPORMs, the address for a Read has to be

ADDRESS + 1 while we want to read the one located at ADDRESS.

The communication protocol used is SPI in CPOL = 1 and CPHA = 1 mode.

The instructions supported are listed in Table 2. SMI Supported instructions.

Table 14. SMI Supported instructions

OPCODE

DESCRIPTION

03

0B

05

06

02

Read data bytes

Read data high speed

Read status register

Write enable

Page program

Release from deep

power-down

AB

13.2.2

Memory map

External memory is mapped in AHB address space as shown in Figure 13.

Figure 13. Memory map

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SPEAR-09-H022

SPI memories

where xx is 16, the address of SMI in the memory map is from 0x1600_0000 to

0x19F_FFFF

13.2.3

Operation mode

Two operation modes exist:

–

Hardware mode is used to serve AHB read and write requests. This is the

functional mode at reset.

–

Software mode is used to serve no AHB requests., during normal working

In both cases SMI can work:

●

or in Normal mode, up to a frequency of 20 MHz (19 Mhz at power on)

either in Fast mode, in a range frequency between 20 MHz and 50 MHz

●

Hardware mode

At reset, the SMI operates in Hardware mode. In this mode, the transmit register and receive

register must not be accessed. They are managed by the SMI State Machine and used to

communicate with the external memory devices whenever an AHB master read or write to

an address in external memory.

Software mode

In Software Mode, transmit register and receive register are accessible. Direct AHB

transfers to/from external memories are not allowed.

Software mode is used to transfer any data or commands from the transmit register to

external memory and to read data directly in the receive register. The transfer is started

using a dedicated bit.

For example Software mode is used to erase Flash memory before writing. Erase cannot be

managed in Hardware mode due to incompatibilities which exist between Flash devices

from different vendors.

In Software mode, application code, being executed by the core, cannot be fetched from

external memory. It must either reside in internal memory, or be previously loaded from

external memory while the SMI is in Hardware mode.

13.2.4

Booting from external memory

SPEAr Head200 has an external boot from a Serial Flash at the Bank0 and the following

command sequence is sent to it:

●

Release from Deep Power-Down

29 µs delay

Read of Status register

Read of data bytes at memory start location

All other banks are disabled at reset and must be enabled by setting dedicated bits before

they can be accessed.

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Ethernet MAC 110

SPEAR-09-H022

14

Ethernet MAC 110

14.1

Overview

The Ethernet MAC controller is compliant with IEEE 802.3 specifications and provides the

following features:

●

Built-in DMA engine to manage Memory transfers

Collision Detection in Half Duplex mode (CSMA/CD)

Control Frames support in Full Duplex mode (IEEE 802.3)

IEEE 802.3 Media Independent Interface (MII), Reduced Media Independent Interface

(RMII) and General Purpose Serial Interface (GPSI)

The Ethernet MAC Controller is composed of two blocks:

●

the DMA_MAC controller, which provides DMA facilities on top of the MAC110 block.

It is able to support two types of operations:

–

write_type RX: data are moved from the MAC110 to a memory destination on the

AMBA bus

–

read_type TX: data are moved from a memory source on the AMBA bus to the

MAC110

●

the MAC110 IP block: it implements the LAN CSMA/CD sublayer for the following

families of systems: 10 Mb/s and 100 Mb/s of data rates for baseband and broadband

systems

Figure 14. Ethernet MAC Controller block diagram

DMA_MAC

Local FIFO

MII

I/F

AHB Master

connected to

MPMC

PHY

DATA

RX DMA

TX DMA

MAC110

MIM

AHB Slave

Configuration

Conguration register array

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SPEAR-09-H022

USB 2.0 Host

15

USB 2.0 Host

15.1

Overview

SPEAr Head has two fully independent USB 2.0 Hosts and each one is constituted with 2

main blocks:

●

the USB2.0PHY that executes the serialization and the de-serialization and implements

the transceiver for the USB line.

●

the USB2.0 Host Controller (UHC). It is connected on AHB Bus and generates the

commands for USB2.0PHY in UTMI+ interface.

15.1.1

15.1.2

USB2.0PHY

The USB2.0PHY is a hard macro included in SPEAr Head. It is designed using standard

cells and custom cells. In this way has been possible to reach the max speed of USB: 480

Mbits/sec.

The macro is able to set his speed in LS / FS for USB 1.1 and in HS for USB 2.0.

UHC

The UHC is able to detect the USB speed configuration: USB 1.1 (LS / FS), USB 2.0 (HS)

via UTMI+ interface.

When the speed is detected, the controller uses 2 sub-controllers: EHCI (Enhanced Host

Controller Interface) for 2.0 configuration and OHCI (Open Host Controller Interface) for 1.1

configuration.

There is an AHB master and a slave for everyone of these controllers.

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USB 2.0 Device

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16

USB 2.0 Device

16.1

Overview

The USB 2.0 Device is constituted with 4 main blocks:

●

USB2.0PHY that executes the serialization and the de-serialization and implements the

transceiver for the USB line

UDC, the USB 2.0 Device Controller. It is connected on AHB Bus and generates the

commands for USB2.0PHY in UTMI+ interface

a dedicated DMA macro to transfer data between the Device Controller and Multi-Port

Memory Controller

USB Plug Detect, which detects the connection of the device

16.1.1

16.1.2

USB2.0PHY

The USB2.0PHY is a hard macro that can reach the max speed HS of USB: 480 Mbits/Sec.

UDC

The UDC is able to detect the USB connection speed via UTMI+ interface.

There is an AHB master and two slaves.

The UDC contains 6 endpoints (0 control, 1 Bulk IN, 2 Bulk OUT, 3 ISO IN, 4 ISO OUT, 5

Interrupt IN)

The UDC contains 4 configurations.

16.1.3

16.1.4

DMA

Provided with a master interface on the AHB Bus, it manage data transfer between Device

Controller CRSs and the FIFO embedded in the block.

USB plug detect

The Plug Detect detects when the Device is connected to an Host and is receiving the

VBUS signal.

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UART

17

UART

UART provides a standard serial data communication with transmit and receive channels

that can operate concurrently to handle a full-duplex operation.

Two internal FIFO for transmitted and received data, deep 16 and wide 8 bits, are present;

these FIFO can be enabled or disabled through a register.

Interrupts are provided to control reception and transmission of serial data.

The clock for both transmit and receive channels is provided by an internal Baud-Rate

generator that divides the AHB Bus clock by any divisor value from 1 to 255. The output

clock frequency of baud generator is sixteen times the baud rate value.

The maximum speed achieved is 115 KBauds.

In SPEAr Head200 there are 3 UART's, APB Bus slaves.

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2

I C controller

SPEAR-09-H022

2

18

I C controller

18.1

Overview

2

The controller serves as an interface between the APB Bus and the serial I C bus. It

provides master functions, and controls all I C bus-specific sequencing, protocol, arbitration

and timing. Supported Standard (100 KHz) and Fast (400 KHz) I C mode.

2

Figure 15. I C Controller block diagram

SLC

Control

I²C

APB

BUS

APB

Register

Array

BUS

Interface

SDA

Control

Main features are:

●

Parallel-bus APB / I2C protocol converter

2

Standard I C mode (100 KHz) / Fast I C mode (400 KHz)

Master interface (only).

Detection of bus errors during transfers

2

Control of all I C bus-specific sequencing, protocol, arbitration and timing

In addition to receiving and transmitting data, this interface converts it from serial to parallel

format and vice versa, using either an interrupt or a polled handshake. The interrupts can be

enabled or disabled by software.

The interface is connected to the I²C bus by a data pin (SDA) and by a clock pin (SCL). SDA

signal is synchronized by SCL signal.

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2

SPEAR-09-H022

I C controller

18.2

Operating mode

Communication flow

In Master mode, it initiates a data transfer and generates the clock signal. A serial data

transfer always begins with a start condition and ends with a stop condition. Both start and

stop conditions are generated by software.

The first byte following the start condition is the address byte; it is always transmitted in

Master mode.

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must

send an acknowledge bit to the transmitter.

2

Figure 16. I C timing

Acknowledge may be enabled and disabled by software.

2

The I C interface address and / or general call address can be selected by software.

2

The speed of the I C interface may be selected between Standard (0 - 100 KHz) and

Fast (100 - 400 KHz).

SDA / SCL line control

Transmitter mode: the interface holds the clock line low before transmission to wait for the

microcontroller to write the byte in the Data Register.

Receiver mode: the interface holds the clock line low after reception to wait for the

microcontroller to read the byte in the Data Register.

The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on

2

the I C bus mode.

2

When the I C cell is enabled, the SDA and SCL ports must be configured as floating open-

drain output or floating input. In this case, the value of the external pull-up resistance used

depends on the application.

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2

I C controller

SPEAR-09-H022

18.3

I²C functional description

Master Mode

The I²C clock is generated by the master peripheral.

The interface operates in Master mode through the generation of the Start condition: Start

bit set to 1 in the control register and I²C not busy (Busy flag set to 0).

Once the Start condition is sent, if interrupts are enabled, an Event Flag bit and a Start bit

are set by hardware. Then the master waits for a read of the register used to observe bus

activity (SR1 register) followed by a write in the data register DR with the Slave address

byte, holding the SCL line low (see Figure 17 Transfer sequencing EV5). Then the slave

address byte is sent to the SDA line via the internal shift register.

After completion of these transfers, the Event Flag bit is set by hardware with interrupt

generation. Then the master waits for a read of the SR1 register followed by a write in the

control register CR (for example set the Peripheral Enable bit), holding the SCL line low

(see Figure 17 Transfer sequencing EV6).

Next the Master must enter Receiver or Transmitter mode.

Master Receiver

Following the address transmission and after SR1 and CR registers have been accessed,

the Master receives bytes from the SDA line into the DR register via the internal shift

register. After each byte the interface generates in sequence:

1) Acknowledge pulse if the acknowledge bit ACK in the control register is set

2) Event Flag and the Byte Transfer Finish bits are set by hardware with an interrupt.

Then the interface waits for a read of the SR1 register followed by a read of the DR register,

holding the SCL line low (see Figure 17 Transfer sequencing EV7).

To close the communication: before reading the last byte from the DR register, set the Stop

bit to generate the Stop condition.

In order to generate the non-acknowledge pulse after the last received data byte, the ACK

bit must be cleared just before reading the second last data byte.

Master Transmitter

Following the address transmission and after SR1 register has been read, the Master sends

bytes from the DR register to the SDA line via the internal shift register.

The master waits for a read of the SR1 register followed by a write in the DR register,

holding the SCL line low (see Figure 17 Transfer sequencing EV8).

When the acknowledge bit is received, the interface sets Event Flag and the Byte Transfer

Finish bits with an interrupt.

To close the communication: after writing the last byte to the DR register, set the Stop bit to

generate the Stop condition.

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SPEAR-09-H022

I C controller

Error Cases

●

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the

Event Flag and BERR bits are set by hardware with an interrupt.

●

AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by

hardware with an interrupt. To resume, set the Start or Stop bit.

In all these cases, the SCL line is not held low; however, the SDA line can remain low due to

possible 0 bits transmitted last. It is then necessary to release both lines by software.

Figure 17. Transfer sequencing

Legend:

S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge

EVx=Event (with interrupt if ITE=1)

EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.

EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

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General purpose I/Os

SPEAR-09-H022

19

General purpose I/Os

The GPIO block consists of 6 General Purpose IOs which act as buffers between the IO

pads and the processor core: data is stored in the GPIO block and can be written to and

read from by the processor via the APB Bus.

Figure 18. GPIO block diagram

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ADC

20

ADC

20.1

Overview

The ADC integrated in SPEAr Head200 is the ST-ADC8MUX16 and it is connected to APB

Bus. It is a successive approximation ADC and its main features are:

●

8 bit resolutions

230 Ksps

16 analog input channels (0 - 3.3 V)

INL 1 LSB

DNL 0.5 LSB

Programmable conversion speed - minimum conversion time 4.3 µs

For any ADC input channel the number of collected samples for the average can be 1 or 2's

power, up to 128.

Positive and negative reference voltages are supply by dedicated pins:

–

positive → VREFP_adc pin

negative → VREFN_adc pin

20.2

Functional description

Conversion starts when enabling bit is set to 1; as it finishes, an interrupt signal is generated

(a bit of conversion ready is set to 1). At this point the reading of the data could begin and

when it finishes, conversion ready and the enabling bits becomes 0.

The signals accessible off-chip are listed in Table 15 External pins of ADC macro.

Table 15. External pins of ADC macro

SIGNAL

DIRECTION

DESCRIPTION

AID[15:0]

Input

Analog channels

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Real time clock

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21

Real time clock

The Real Time Clock block implements 3 functions:

●

time-of-day clock in 24 hour mode

calendar

alarm

Time and calendar value are stored in binary code decimal format.

The RTC provides also a self-isolation mode, which allows it working even if power isn't

supplied to the rest of the device.

It is an APB Bus slave.

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SPEAR-09-H022

Watchdog timer

22

Watchdog timer

The WdT is based on a programmable 8 bit counter and generates a hot reset (single pulse)

when it overflows. This reset will restart the ARM but the code will not be downloaded again.

The timer should be cleared by the software before it overflows.

The counter is clocked by a slow signal coming from a 17 bit prescaler clocked by the APB

clock. So that, as APB Bus has a frequency of 133 MHz, the elapsing time is 0.25 second.

The WdT is an APB Slave device.

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General purpose timers

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23

General purpose timers

SPEAr Head200 has 4 GPTs, connected as APB Bus slaves.

A GPT is constituted by 2 channels and each one consists of a programmable 16 bit counter

and a dedicated 8 bit timer clock prescaler. The programmable 8 bit prescaler unit performs

a clock division by 1, 2, 4, 8, 16, 32, 64, 128, and 256, allowing a frequency range from 3.96

Hz to 48 MHz.

Two modes of operation are available for each GPT:

●

Auto Reload Mode. When the timer is enabled, the counter is cleared and starts

incrementing. When it reaches the compare register value, an interrupt source is

activated, the counter first is automatically cleared and then restarts incrementing.

The process is repeated until the timer is disabled.

●

Single Shot Mode. When the timer is enabled, the counter is cleared and starts

incrementing. When it reaches the compare register value, an interrupt source is

activated, the counter stopped and the timer disabled.

The current timer counter value could be read from a register.

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SPEAR-09-H022

Customizable logic

24

Customizable logic

24.1

Overview

The Customizable Logic consists of an embedded macro where it is possible embedding a

custom project by mapping up to 200K equivalent ASIC gates (corresponding at 16K LUT).

The logic is interfaced with the rest of the system so that can be implemented:

●

AHB sub-systems with masters and slaves (via 1 AHB full master, 1 AHB full slave, 1

AHB master lite, 2 AHB slave ports)

●

AHB master lite connected to DRAM controller

AHB memories (via AHB slave ports) implemented by configuring the logic cells as

SRAM elements.

●

I/O protocol handlers (via the 112 dedicated GPIO connections)

8 interrupt channels

8 DMA requests

4 independent SRAM data channels (via dedicated connection to on-chip 16 KByte

SRAM)

All of the above configuration scenarios can be mixed together in the same user-defined

logic.

24.2

Custom project development

There are 2 ways to develop a project to embed in SPEAr Head200: through SPEAr Head

behavioral model or through external FPGA.

24.2.1

24.2.2

SPEAr Head behavioral model

In the first case ST provides behavioral model of the fixed architecture allowing the final user

to verify custom logic. Verification procedure is the same as a standard ASIC flow

External FPGA

The custom project to design in the customizable logic can be implemented on an external

FPGA, which emulates eASIC™ logic cells. The purpose of this characteristic is allowing

the user to develop his project both under real-time constraints and compliant to eASIC™

MacroCell features.

This mode is enabled by using the GPIO interface, which is internally configured to support

full-master and full-slave AHB ports. Figure 19 Emulation with external FPGA highlights the

described behavior. In order to enable the "development mode", the configuration pin has to

be set to state logic 1. After this configuration the logic implemented in the external FPGA

●

can completely interact with the following scenarios:

–

AHB sub-systems with masters and slaves connected to the main system bus (full

masters and full slaves peripherals)

–

I/O protocol handlers (via 112 dedicated FPGA I/Os)

4 interrupt channels

4 DMA requests

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Customizable logic

All the above scenarios can be mixed in the same FPGA configuration

SPEAR-09-H022

●

can be tested in order to verify the accordance with eASIC™ MacroCell features, by

running the ARM926EJ-S software debugger on a PC connected to SPEAr Head200.

Once this test has been completed successfully, then the user-defined logic is ready to

be moved without any additional changes within the on-chip eASIC™ configurable

logic.

Figure 19. Emulation with external FPGA

SPEAr™ Head

Configuration pin set to

Development Mode

AHB BUS

FPGA

Custom

Design

eASIC™

24.3

Customization process

The customization process requires two separate steps, executed at different times:

1. Programming layer fabrication (single VIA-mask).

2. Bitstream download.

The step 1 defines the interconnection between the customizable logic cells and is executed

at fabrication level on top of the silicon wafers stored in the fab.

The step 2 defines the logic function for each customizable logic cell and is executed after

that the system has been powered up by dedicated software routines running on the

ARM926 microprocessor.

Both Bitstream and VIA-mask realize the user-defined customization for the entire device.

The eASIC™ mapping flow starts from the RTL description of the user-defined

customization, with the purpose to generate the VIA-mask and configuration Bitstream.

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SPEAR-09-H022

Customizable logic

24.4

Power on sequence

Once the system is powered-on, the eASIC™ logic has to be properly configured before its

usage. In order to accomplish this task, two main operations have to be performed (both

using dedicated software routines running on the ARM9 microprocessor):

1. Bitstream download

2. Startup of connection between the eASIC™ MacroCell and the rest of the device

Both steeps are driven by the a control register programmable via APB bus.

24.4.1

Bitstream download

The bitstream download operation is responsible for the eASIC™ logic initialization, since

each configurable cell of the customizable logic is loaded with a data stream that represents

the mapped logic function. Each operation of this download is performed by a dedicated

software routine that read and writes data across the Control register reserved bits.

The bitstream is a 32 KByte data that is stored in the external non-volatile memory of the

SPEAr™ device.

24.4.2

24.4.3

Connection startup

Once the eASIC™ logic is up and running due to the Bitstream initialization, next steep is its

reset, in order to allow connections to the other IPs of the chip. The reset routine is activated

by programming the Control register.

Last steep is the enabling of needed connections, by setting the Status register.

Programming interface

In order to achieve the Bitstream download and the reset routine, a dedicate logic has been

embedded in the SPEAr Head200: the Programming Interface, which also includes the

Control register.

65/71

Electrical characteristics

SPEAR-09-H022

25

Electrical characteristics

25.1

Absolute maximum ratings

This product contains devices to protect the inputs against damage due to high static

voltages; however it is advisable to take normal precaution to avoid application of any

voltage higher than the specified maximum rated voltages.

Table 16. Absolute maximum rating values

Symbol

Parameter

Value

Unit

VDD core Supply voltage core

2.1

6.4

5.4

2.1

6.4

5.4

V

VDD I/O

Supply voltage I/O

VDD PLL Supply voltage PLL

VDD SDR Supply voltage SDRAM

VDD DDR Supply voltage DDR

VDD RTC Supply voltage RTC

Vi TTL

Input voltage TTL (3.3 and 5 V tolerant)

Vi SRAM Input voltage SDRAM

Vi DDR

Input voltage DDR

Input voltage USB (Host and Device) data signal

interfaces

Vi USBds

6.4

V

Vi USBrr

Vi AN

Tj

Input voltage USB reference resistor

Analog input voltage ADC

Junction temperature

6.4

V

6.4

-40 to 125

-55 to 150

°C

Tstg

Storage temperature

VHBM

VCDM

This device is compliant with Human Body Model JEDEC spec JESD22-A114C Class 2

This device is compliant with Charge Device Model JEDEC spec JESD22-C101C Class 2

The average chip-junction temperature, Tj, can be calculated using the following equation:

T = T + (P · Θ )

j

A

D

JA

where:

●

T is the ambient temperature in °C

A

Θ

is the package Junction-to-Ambient thermal resistance, which is 34 °C/W

JA

P = P

+ P

PORT

D

INT

–

P

is the chip internal power

is the power dissipation on Input and Output pins; user determined

PORT

If P

is neglected, an approximate relationship between P is:

D

PORT

P = K / (Tj + 273 °C)

D

And, solving first equations:

2

K = P · (T + 273 °C) + Θ x P

D

A

JA

66/71

SPEAR-09-H022

Electrical characteristics

K is a constant for the particular, which can be determined through last equation by

measuring P at equilibrium, for a know T

D

A

Using this value of K, the value of P and T can be obtained by solving first and second

D

J

equation, iteratively for any value of T .

A

25.2

DC electrical characteristics

25.2.1

Supply voltage specifications

The recommended operating conditions are listed in the following table:

Table 17. Recommended operating conditions

Symbol

VDD core Supply voltage core

VDD I/O Supply voltage I/O

Description

Min.

Typ.

Max.

Unit

1.14

3

1.2

3.3

2.5

1.2

1.26

3.6

2.7

1.32

85

V

VDD PLL Supply voltage PLL

VDD SDR Supply voltage SDRAM

VDD DDR Supply voltage DDR

VDD RTC Supply voltage RTC

3

V

3

V

2.3

1.08

-40

V

Top

Operating temperature

°C

25.2.2

I/O voltage specifications

25.2.2.1

LVTTL I/O (compliant with EIA/JEDEC standard JESD8-B)

For LVTTL (3.3 V capable) pins, the allowed I/O voltages are:

Table 18. Low Voltage TTL DC input specification (3 < VDD < 3.6)

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Vil

Vih

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

0.8

V

2

Vhyst

0.495

0.620

Table 19. Low Voltage TTL DC output specification (3 < VDD < 3.6)

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Vol

Low level output voltage

High level output voltage

Iol = X mA *

Ioh = X mA *

0.15

V

Voh

VDD - 0.15

* X is the source / sink current under worst case conditions and it is reflected in the name of the I/O cell

according to the drive capability.

67/71

Electrical characteristics

Table 20. Pull-up and Pull-down characteristics

SPEAR-09-H022

Symbol

Parameter

Pull-up current

Test Condition

Min.

Typ.

Max.

Unit

Ipu

Ipd

Vi = 0 V

Vi = VDD

Vi = 0 V

40

30

32

27

60

50

110

133

75

µA

Pull-down current

Rup

Rpd

Equivalent Pull-up resistance

KOhm

Equivalent Pull-down resistance Vi = VDD

100

25.2.2.2

LVCMOS/SSTL I/O

If the I/Os are set as LVCMOS (for SDRAM memories), the DC electrical characteristics are

the following:

Table 21. LVCMOS DC input specification (3 < VDD < 3.6)

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Vout ≥ Voh (min)

or Vout ≤ Vol (max)

Vil

Low level input voltage

-0.3

2

0.8

V

Vih

Iin

High level input voltage

Input Current

VDD+0.3

5

V

Vin = 0 or Vin =VDD

µA

Table 22. LVCMOS DC output specification (3 < VDD < 3.6)

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Low level output

voltage

Vol

VDD = min, Iol = 100 µA

0.2

V

High level output

voltage

Voh

VDD = min, Ioh = -100 µA

VDD - 0.2

V

Instead when they are set as (for DDR memories), refer to following tables:

Table 23. DC input specification of bidirectional SSTL pins (2.3 < VDD DDR < 2.7)

Symbol

Parameter

Min.

Max.

Unit

Vil

Low level input voltage

High level input voltage

-0.3

SSTL_VREF – 0.15

VDD DDR – 0.15

V

Vih

SSTL_VREF + 0.15

Table 24. DC input specification of bidirectional differential SSTL pins

(2.3 < VDD DDR < 2.7)

Symbol

Parameter

Min.

Max.

Unit

Vin

DC input signal voltage

-0.3

VDD DDR + 0.3

VDD DDR + 0.6

V

Vswing

DC differential input voltage

0.36

68/71

SPEAR-09-H022

Package information

26

Package information

®

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 20. PBGA420 Mechanical Data & Package Dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN.

TYP. MAX. MIN.

TYP. MAX.

0.0713

A

A1

A2

A3

A4

b

1.81

0.0106

1.305

0.27

0.0514

0.0205

0.0309

0.52

0.785

0.45

0.50

0.55 0.0177 0.0197 0.0217

D

22.80 23.00 23.20 0.8976 0.9055 0.9134

21.00 0.8268

22.80 23.00 23.20 0.8976 0.9055 0.9134

D1

E

E1

e

21.00

1.00

0.8268

0.0394

F

ddd

eee

fff

0.20

0.25

0.10

0.0079

0.0098

0.0039

PBGA420 (23x23x1.81mm)

Ball Grid Array Package

7859856 A

69/71

Revision history

SPEAR-09-H022

27

Revision history

Table 25. Document revision history

Date

Revision

Changes

17-Oct-2005

1

Initial release.

Changed the Part Number from SPEAR-09-H020 to SPEAR-

09-H022.

01-Dec-2005

2

Modified/added some dates in the Chapter 7.

29-Mar-2006

03-Aug-2006

3

4

Changed Block diagram & Pin out.

Modified Table 2: Pins belonging to POWER group.

Modified Chapter 2: Product Overview: point 9.

Modified Chapter 3.6.2: USB 2.0 device.

28-Sep-2006

5

Modified Table 2: Pins belonging to POWER group: ball “AB2”.

Modified Section 16.1.2: UDC.

Modified Table 16: Absolute maximum rating values.

70/71

SPEAR-09-H022

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71/71


型号：	SPEAR-09-H022_06
厂家：	ST
描述：	SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC 的SPEAr Head200 ARM 926 ， 200K定制eASIC公司大门，大型的IP组合的SoC
文件：	总71页 (文件大小：930K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPEAR-09-H022_06 [STMICROELECTRONICS]

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