M59PW032100N1T [STMICROELECTRONICS]
2MX16 FLASH 3V PROM, 100ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48;
| 型号： | M59PW032100N1T |
| 厂家： | 
ST |
| 描述： | 2MX16 FLASH 3V PROM, 100ns, PDSO48, 12 X 20 MM, PLASTIC, TSOP-48 可编程只读存储器 光电二极管 |
| 文件： | 总23页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M59PW032
32 Mbit (2Mb x16, Uniform Block)
3V Supply LightFlash™ Memory
NOT FOR NEW DESIGN
FEATURES SUMMARY
■
■
MASK-ROM PIN-OUT COMPATIBLE
SUPPLY VOLTAGE
Figure 1. Packages
–
–
VCC = 2.7 to 3.6V for Read
VPP = 11.4 to 12.6V for Program
■
■
ACCESS TIME
–
–
90ns at VCC = 3.0 to 3.6V
100, 110ns at VCC = 2.7 to 3.6V
SO44 (M)
PROGRAMMING TIME
–
–
9µs per Word typical
Multiple Word Programming Option
(4s typical Chip Program)
■
■
SUITABLE FOR ON-BOARD
PROGRAMMING
ERASE TIME
TSOP48 (N)
12 x 20mm
–
21s typical Chip Erase
UNIFORM BLOCKS
16 blocks of 2 Mbits
PROGRAM/ERASE CONTROLLER
Embedded Word Program algorithms
■
■
–
–
■
■
10,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
–
–
Manufacturer Code: 0020h
Device Code: 88AEh
December 2005
1/23
This is information on a product still in production but not recommended for new designs.
M59PW032
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
V
V
CC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 10
2/23
M59PW032
Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
PP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Status Register Bit DQ1 is reserved.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Chip Enable Controlled, Write AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . 19
Table 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . 19
Figure 13.TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Outline . . . . . . . . . . 20
Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Mechanical Data . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M59PW032
SUMMARY DESCRIPTION
The M59PW032 is a 32 Mbit (2Mb x16), Mask-
ROM pin-out compatible, non-volatile LightFlash
memory, that can be read, erased and
reprogrammed. Read operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. Program and Erase operations require an
additional VPP (11.4 to 12.6V) power supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 8 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased (see
Table 2., Block Addresses). Program and Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase Con-
troller (P/E.C.) simplifies the process of program-
ming or erasing the memory by taking care of all of
the special operations that are required to update
the memory contents.
The M59PW032 features an innovative command,
Multiple Word Program, that is used to program
large streams of data. It greatly reduces the total
programming time when a large number of Words
are written to the memory at any one time. Using
this command the entire memory can be pro-
grammed in 4s, compared to 18s using the stan-
dard Word Program.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allow simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44 and TSOP48
(12x20mm) packages. The memory is supplied
with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ15
Data Inputs/Outputs
Chip Enable
V
V
PP
CC
E
G
Output Enable
21
16
V
Supply Voltage read
Supply Voltage program erase
Ground
CC
A0-A20
DQ0-DQ15
V
PP
V
SS
M59PW032
E
NC
Not Connected Internally
G
V
SS
AI07226
4/23
M59PW032
Figure 3. SO Connections
Figure 4. TSOP Connections
V
1
48
V
PP
SS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
V
A16
A15
A14
A13
A12
A11
SS
2
DQ15
3
DQ7
4
A9
DQ14
DQ6
5
A10
A11
A12
A13
A14
A15
A16
6
DQ13
DQ5
7
A10
A9
8
DQ12
DQ4
V
9
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
A19
V
CC
M59PW032
12
13
37
36
V
SS
CC
M59PW032
V
PP
A20
NC
V
V
SS
G
SS
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
A18
A17
A7
DQ15
DQ7
DQ0
DQ8
DQ14
DQ6
A6
DQ1
A5
DQ9
DQ13
DQ5
A4
A3
A2
A1
A0
DQ2
DQ10
DQ3
DQ12
DQ4
DQ11
V
CC
V
V
SS
24
25
AI07227
E
SS
AI07267
5/23
M59PW032
Table 2. Block Addresses
Block Number
Address Range
0E0000h-0FFFFFh
0C0000h-0DFFFFh
0A0000h-0BFFFFh
080000h-09FFFFh
060000h-07FFFFh
040000h-05FFFFh
020000h-03FFFFh
000000h-01FFFFh
Block Number
Address Range
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
1E0000h-1FFFFFh
1C0000h-1DFFFFh
1A0000h-1BFFFFh
180000h-19FFFFh
160000h-17FFFFh
140000h-15FFFFh
120000h-13FFFFh
100000h-11FFFFh
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
also allows Bus Write operations, when VPP is in
the VHH range.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for Read operations.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program Controller.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
tions, ICC3
.
VPP Program Supply Voltage. VPP is both a
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin.
When the VPP is in the VHH range (see Table
11., DC Characteristics, for the relevant values)
the Program/Erase operation is enabled. During
such operations the VPP must be stable in the VHH
range.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
If the VPP is kept under the VHH range, particularly
in the voltage range 0 to 3.6V, any Program/Erase
operation is disabled or stopped.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
tions, when VPP is in the VHH range.
Note that VPP must not be left floating or uncon-
nected as the device may become unreliable.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operations of the memory. It
6/23
M59PW032
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Table 3., Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11., DC Characteristics.
During program operation the memory will contin-
ue to use the Program Supply Current, ICC3, for
Program operation until the operation completes.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs and applying a Low signal, VIL, to Chip En-
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 10., Read AC
Waveforms, and Table 12., Read AC Characteris-
tics, for details of when the output becomes valid.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when VPP is set to VHH. A valid Bus Write opera-
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure
11., Write AC Waveforms, Chip Enable Con-
trolled, and Table 13., Chip Enable Controlled,
Write AC Characteristics, for details of the timing
requirements.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Table 3., Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 3. Bus Operations
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15-DQ0
V
Operation
Bus Read
E
G
PP
(3)
V
V
Cell Address
Data Output
Data Input
Hi-Z
IL
IL
IL
IH
IH
XX
V
V
V
V
Bus Write
Command Address
HH
X
Output Disable
Standby
X
X
X
V
X
X
Hi-Z
IH
A0 = V , A1 = V ,
Read Manufacturer
Code
IL
IL
V
V
V
V
V
0020h
88AEh
IL
IL
IL
IL
HH
HH
Others V or V
IL
IH
A0 = V , A1 = V ,
IH
IL
V
Read Device Code
Others V or V
IL
IH
Note: 1. X = V or V
.
IH
IL
2. XX = V , V or V
IL
IH
HH
3. When reading Status Register during Program/Erase algorithm execution V must be kept at V
.
HH
PP
7/23
M59PW032
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Refer to Tables 4 and 5, for a summary of the com-
mands.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
VPP must be set to VHH during the Read/Reset
command. If VPP is set to either VIL or VIH the com-
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
once. VPP must be set to VHH during Multiple Word
Program. If VPP is set either VIL or VIH the com-
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
Auto Select Command.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. VPP
must be set to VHH during the Auto Select com-
mand. If VPP is set to either VIL or VIH the com-
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the P/E.C. has started (see Table 7 and
Figure 6).
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 5., Multiple Word Program Command,
and Figure 5., Multiple Word Program Flowchart).
Word Program Command.
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the P/E.C. is ready to accept the op-
eration (see Table 7 and Figure 6).
The Program Phase is executed in three different
sub-phases:
The Word Program command can be used to pro-
gram a Word to the memory array. VPP must be
set to VHH during Word Program. If VPP is set to ei-
ther VIL or VIH the command will be ignored, the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the P/E.C.
1. The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
8/23
M59PW032
Start Address and the first Word to be
programmed.
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
2. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A20 equal to
the Start Address), that indicates to the PC
that the Program Phase has to continue. A0 to
A16 are ‘don’t care’.
3. Finally, after all Words have been
programmed, a Bus Write operation (the
(n+1)th) with a Final Address, FA (A17 or a
higher address pin different from the Start
Address), ends the Program Phase.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 6.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’.
Block Erase Command.
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
The memory is now set to enter the Verify Phase.
V
PP must be set to VHH during Block Erase. If VPP
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode.
Six Bus Write operations are required to select the
block . The Block Erase operation starts the P/E.C.
after the last Bus Write operation. The Status Reg-
ister can be read after the sixth Bus Write opera-
tion. See the Status Register for details on how to
identify if the P/E.C. has started the Block Erase
operation.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the P/E.C. is ready for the next oper-
ation or if the reprogram of the location has failed
(see Table 7 and Figure 6).
Three successive steps are required to execute
the Verify Phase of the command:
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
1. The first Bus Write operation of the Verify
Phase latches the Start Address and the Word
to be verified.
2. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A20
equal to the Start Address).
3. Finally, after all Words have been verified, a
Bus Write cycle with a Final Address, FA (A17
or a higher address pin different from the Start
Address) ends the Verify Phase.
Chip Erase Command.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 7
and Figure 6).
If the Verify Phase accomplishes successfully, the
memory returns to the Read mode and DQ6 stops
toggling.
On the contrary, if the P/E.C. fails to reprogram a
given location, the Verify Phase terminates, DQ6
continues toggling and error bit DQ5 is set in the
Status Register. If the error is due to a VPP failure
DQ4 is also set.
V
PP must be set to VHH during Chip Erase. If VPP
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the P/E.C.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
9/23
M59PW032
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
Table 4. Standard Commands
Bus Write Operations
Command
1st
2nd
Data
3rd
Data
4th
5th
6th
Add
X
Data
F0
Add
Add
Add
Data
Add
Data
Add
Data
1
3
3
4
6
6
Read/Reset
555
555
555
555
555
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
X
F0
90
A0
80
80
Auto Select
Word Program
Block Erase
Chip Erase
555
555
555
555
PA
PD
AA
AA
555
555
2AA
2AA
55
55
BA
30
10
555
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Bus Write Operations
Phase
1st
Add Data Add Data Add Data Add Data Add Data
555 AA 2AA 55 555 20
2nd
3rd
4th
5th
nth
Final
Add Data Add Data
Set-Up
3
Program n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
Verify n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
CA
CA
PAn
PAn
FA
FA
X
X
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Typical after
(1)
Parameter
Min
Max
Unit
Typ
21
(1)
10k W/E Cycles
Chip Erase
25
120
6
s
Block Erase (128 KWords)
Program (Word)
1.5
9
s
200
35
µs
Chip Program (Multiple Word)
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
4
s
s
18
35
10,000
cycles
Note: 1. T = 25°C, V = 12V.
A
PP
10/23
M59PW032
Figure 5. Multiple Word Program Flowchart
Start
Setup
Verify
Phase
Phase
Read Status
Register
Write AAh
Address 555h
Write 55h
Address 2AAh
NO
DQ0 = 0?
Write 20h
Address 555h
Write Data1
Start Address
Read Status
Register
Read Status
Register
NO
NO
NO
NO
DQ6
Setup time
exceeded?
NO
toggling?
DQ5 = 1 ?
DQ0 = 0?
YES
YES
YES
YES
Write Data 2
EXIT (setup failed)
DQ0 = 0?
YES
Continuing Address
Write Data1
Start Address
Read Status
Register
Program
Phase
NO
Read Status
Register
NO
DQ0 = 0?
YES
DQ5 = 1?
YES
NO
NO
NO
DQ0 = 0?
Write Data n
Continuing Address
YES
Write Data 2
Continuing Address
Read Status
Register
NO
Read Status
Register
NO
DQ0 = 0?
YES
DQ5 = 1?
YES
Exit
Phase
DQ0 = 0?
YES
Read Status
Register
Write XX
Finishing Address
Write Data n
Continuing Address
YES
NO
DQ4 = 0?
Read Status
Register
Fail error
Read Status
Register
Fail, VPP error
YES
DQ6
toggling?
Write F0h
Address XX
DQ0 = 0?
YES
NO
Write XX
Finishing Address
Exit (read mode)
AI05954
11/23
M59PW032
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. The bits in the Status Register
are summarized in Table 7., Status Register Bits.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the P/E.C. has suc-
cessfully completed its operation. The Data Poll-
ing Bit is output on DQ7 when the Status Register
is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement.
VPP Status Bit (DQ4). The VPP Status Bit can be
used to identify if any Program or Erase operation
has failed due to a VPP error. If VPP falls below VHH
during any Program or Erase operation, the oper-
ation aborts and DQ4 is set to ‘1’. If VPP remains at
VHH throughout the Program or Erase operation,
the operation completes and DQ4 is set to ‘0’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of P/E.C. operation
during a Block Erase command. Once the P/E.C.
starts erasing the Erase Timer Bit is set to ’1’. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
Figure 6., Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the P/E.C. dur-
ing Block Erase operations. The Alternative Tog-
gle Bit is output on DQ2 when the Status Register
is read.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the P/E.C. has successfully com-
pleted its operation. The Toggle Bit is output on
DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Block Erase operations the Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc., with successive
Bus Read operations from addresses within the
block being erased. Once the operation completes
the memory returns to Read mode.
After an Erase operation that causes the Error Bit
to be set, the Alternative Toggle Bit can be used to
identify where the error occurred. The Alternative
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read Operations from addresses
within a block that has not erased correctly. The
Alternative Toggle Bit does not change if the ad-
dressed block has erased correctly.
Figure 8., AC Measurement I/O Waveform, gives
an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the P/E.C. The Error Bit
is set to ’1’ when a Program, Block Erase or Chip
Erase operation fails to write the correct data to
the memory. If the Error Bit is set a Read/Reset
command must be issued before other commands
are issued. The Error bit is output on DQ5 when
the Status Register is read.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the P/E.C. is active or inactive during Multiple
Word Program. When the P/E.C. has written one
Word and is ready to accept the next Word, the bit
is set to ‘0’.
Status Register Bit DQ1 is reserved.
12/23
M59PW032
Table 7. Status Register Bits
(1)
P/E.C. Status
Programming
Waiting for data
Program fail
Address
DQ7
–
DQ6
DQ5 DQ4 DQ3
DQ2
DQ0
Command
–
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
1
0
1
0
–
–
0
0
0
0
0
1
–
1
0
1
–
–
–
Multiple Word
Program
–
–
–
(2)
–
–
–
Programming
Program error
–
DQ7
DQ7
0
–
–
–
Word Program
(2)
–
In erasing block
–
–
Toggle
Erasing
Not in
erasing block
0
0
0
Toggle
Toggle
Toggle
0
1
1
1
1
1
No Toggle
Toggle
–
–
–
Chip Erase/
Block Erase
(2)
(2)
In failed block
Erase fail
Not in
failed block
No Toggle
Note: 1. Unspecified data bits should be ignored.
2. DQ4 = 0 if V ≥ V during Program/Erase algorithm execution; DQ4 = 1 if V < V during Program/Erase algorithm execution.
PP
HH
PP
HH
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
PASS
YES
FAIL
PASS
AI03598
AI01370B
13/23
M59PW032
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
–65
–0.6
–0.6
–0.6
Max
125
150
Unit
°C
°C
V
T
Temperature Under Bias
Storage Temperature
BIAS
T
STG
(1,2)
V
IO
V
+0.6
CC
Input or Output Voltage
Read Supply Voltage
V
CC
4
V
(3)
V
PP
13.5
V
Program/Erase Supply Voltage
Note: 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V for less than 20ns during transitions.
CC
3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. V must not remain at V for more than a total
PP
HH
of 80hrs.
14/23
M59PW032
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Parameter
M59PW032
100, 110
Unit
Min
2.7
11.4
0
Max
3.6
V
V
Read Supply Voltage
V
V
CC
PP
Program/Erase Supply Voltage
12.6
70
Ambient Operating Temperature (T )
°C
pF
ns
V
A
Load Capacitance (C )
30
L
Input Rise and Fall Times
10
Input Pulse Voltages
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
1.3V
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
AI05546
OUT
C
L
C = 30pF
L
C includes JIG capacitance
L
AI05447
Table 10. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
IN
= 0V
= 0V
IN
C
V
OUT
12
pF
OUT
Note: Sampled only, not 100% tested.
15/23
M59PW032
Table 11. DC Characteristics
(1)
Symbol
Test Condition
Min
Max
±1
Unit
µA
Parameter
I
LI
0V ≤V ≤V
Input Leakage Current
IN
CC
I
0V ≤V
≤V
Output Leakage Current
Supply Current (Read)
Supply Current (Standby)
±1
µA
LO
OUT CC
E = V , G = V ,
IL
IH
I
10
mA
CC1
f = 6MHz
(2)
E = V ±0.2V
100
20
µA
mA
V
I
CC
CC2
I
Supply Current (Program)
Input Low Voltage
P/E.C. active
CC3
V
–0.5
0.8
IL
V
IH
0.7V
V
CC
+0.3
Input High Voltage
V
CC
V
V
I
= 1.8mA
OL
Output Low Voltage
Output High Voltage
0.45
V
OL
V
–0.4
I
= –100µA
V
OH
HH
CC
OH
V
I
V
V
Program Voltage
Current (Program)
11.4
12.6
10
V
PP
PP
P/E.C. Active
mA
HH
Note: 1. V must be applied simultaneously or before V and removed simultaneously or after V .
PP
CC
PP
2. Average Value.
16/23
M59PW032
Figure 10. Read AC Waveforms
A0-A20
VALID
tAVQV
tAXQX
E
tELQV
tEHQZ
G
tGLQV
tGHQZ
VALID
DQ0-DQ15
AI07228
Table 12. Read AC Characteristics
M59PW032
(1)
Symbol Alt
Test Condition
100
110
Unit
Parameter
V
= 3.0 to 3.6V V = 2.7 to 3.6V V = 2.7 to 3.6V
CC
CC
CC
E = V ,
Address Valid to
Output Valid
IL
t
t
t
t
ACC
Max
90
90
35
30
30
0
100
100
35
30
30
0
110
110
35
30
30
0
ns
ns
ns
ns
ns
ns
AVQV
G = V
IL
Chip Enable Low to
Output Valid
t
G = V
Max
Max
Max
Max
Min
ELQV
CE
IL
Output Enable Low to
Output Valid
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
t
t
G = V
t
HZ
IL
EHQZ
Output Enable High
to Output Hi-Z
(2)
E = V
t
DF
IL
GHQZ
Address Transition to
Output Transition
t
AXQX
OH
Note: 1. V must be applied after V and with the Chip Enable (E) at V .
IH
PP
CC
2. Sampled only, not 100% tested.
17/23
M59PW032
Figure 11. Write AC Waveforms, Chip Enable Controlled
A0-A20
VALID
tELAX
tAVEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ15
V
CC
tVCHEL
tVPHEL
V
PP
AI07229
Table 13. Chip Enable Controlled, Write AC Characteristics
(1)
Symbol
Alt
M59PW032
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Parameter
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
50
50
0
ELEH
CP
t
t
DVEH
DS
t
t
Chip Enable High to Input Transition
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
EHDX
DH
t
t
50
0
EHEL
CPH
t
t
AS
AVEL
t
t
100
10
10
50
ELAX
AH
t
GHEL
t
t
EHGL
OEH
t
t
t
V
V
High to Chip Enable Low
High to Chip Enable Low
VCHEL
VCS
CC
PP
(2)
Min
500
ns
t
VCS
VPHEL
Note: 1. T = 25°C; V = 11.4 to 12.6V; V = 2.7 to 3.6V.
A
PP
CC
V
must be applied after V and with the Chip Enable (E) at V .
PP
CC IH
Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
18/23
M59PW032
PACKAGE MECHANICAL
Figure 12. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline
D
44
23
c
E1 E
θ
1
22
A1
L
A2
A
L1
ddd
b
e
SO-F
Note: Drawing is not to scale.
Table 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
3.00
0.118
0.10
2.69
0.004
0.106
2.56
0.35
2.79
0.50
0.28
28.63
0.10
16.28
12.73
–
0.101
0.014
0.007
1.117
0.110
0.020
0.011
1.127
0.004
0.641
0.501
–
c
0.18
D
28.50
28.37
1.122
ddd
E
16.03
12.60
1.27
15.77
12.47
–
0.631
0.496
0.050
0.031
0.068
0.621
0.491
–
E1
e
L
0.79
L1
θ
1.73
8°
8°
N
44
44
19/23
M59PW032
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
Note: Drawing is not to scale.
Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
α
0
5
0
5
20/23
M59PW032
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M59PW032
100 M
1
T
Device Type
M59P = LightFlash Memory
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
032 = 16 Mbit (x16)
Speed
(1)
100 = 100 ns
110 = 110 ns
Package
M = SO44, 500mils body width
N = TSOP48: 12 x 20 mm
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Note: 1. This speed also guarantees 90ns access time at V = 3.0 to 3.6V.
CC
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
21/23
M59PW032
REVISION HISTORY
Table 17. Document Revision History
Date
Version
Revision Details
19-Jul-2002
1.0
First Issue
Multiple Word Program Command Table clarified (Table 5)
05-Aug-2002
05-Dec-2002
1.1
1.2
I , I clarified (Table 11)
CC1 CC2
Mask-ROM specification added
SO44 package changed to 500mils body width
Bus Operation table clarified (Table 3)
Read/Reset, Auto Select and Multiple Word Program commands clarified
90ns speed class obtained from the 100ns at V = 3.0 to 3.6V - clarification (Table
CC
12 and 13)
20-Feb-2003
30-Jan-2004
1.3
2.0
TSOP Connections diagram updated (Figure 4)
Document status promoted from Product Preview to full Datasheet.
TSOP48 package specifications changed (see Figure 13 and Table 15).
15-Mar-2005
06-Dec-2005
3.0
4.0
Table 16., Ordering Information Scheme corrected.
Datasheet status updated to ‘NOT FOR NEW DESIGN’.
22/23
M59PW032
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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23/23
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