M59PW1282120M1 [STMICROELECTRONICS]
8MX16 FLASH 12V PROM MODULE, 120ns, PDSO44, 0.500 INCH, PLASTIC, SO-44;
| 型号： | M59PW1282120M1 |
| 厂家： | 
ST |
| 描述： | 8MX16 FLASH 12V PROM MODULE, 120ns, PDSO44, 0.500 INCH, PLASTIC, SO-44 存储 内存集成电路 光电二极管 |
| 文件： | 总24页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M59PW1282
128Mbit (two 64Mb, x16, Uniform Block, LightFlash™)
3V Supply, Multiple Memory Product
FEATURES SUMMARY
■ MASK-ROM PIN-OUT COMPATIBLE
Figure 1. Package
■ TWO 64 Mbit LightFlash™ MEMORIES
STACKED IN A SINGLE PACKAGE
■ SUPPLY VOLTAGE
– V = 2.7 to 3.6V for Read
CC
– V = 11.4 to 12.6V for Program and Erase
PP
■ ACCESS TIME
– 90ns at V = 3.0 to 3.6V
CC
– 100, 120ns at V = 2.7 to 3.6V
CC
■ PROGRAMMING TIME
– 9µs per Word typical
SO44 (M)
– Multiple Word Programming Option
(16s typical Chip Program)
■ ERASE TIME
– 85s typical Chip Erase
■ UNIFORM BLOCKS
– 64 blocks of 2 Mbits
■ PROGRAM/ERASE CONTROLLER
– Embedded Word Program algorithms
■ 10,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code : 88A8h
November 2003
1/24
M59PW1282
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
CC
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address/Voltage Supply (A22/V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PP)
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 11
Figure 4. A22 Latch Procedure Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. A22 Latch Procedure AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Chip Erase Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Multiple Word Program Flowchart for 64Mbit Top and Bottom Die . . . . . . . . . . . . . . . . . 13
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M59PW1282
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
PP
Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register Bit DQ1 is reserved.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Chip Enable Controlled, Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . 21
Figure 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
M59PW1282
SUMMARY DESCRIPTION
The M59PW1282 is a 128Mbit (8Mb x16), Mask-
ROM pinout compatible, non-volatile LightFlash™
memory, that can be read, erased and repro-
grammed. Read operations can be performed us-
ing a single low voltage (2.7 to 3.6V) supply.
Program and Erase operations require an addi-
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller (P/E.C.) simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
tional V (11.4 to 12.6V) power supply. On pow-
PP
er-up the memory defaults to its Read mode where
it can be read in the same way as a ROM or
EPROM.
The Mask-ROM compatibility is obtained using a
dual function Address/Voltage Supply pin (A22/
The M59PW1282 features an innovative com-
mand, Multiple Word Program, that is used to pro-
gram large streams of data. It greatly reduces the
total programming time when a large number of
Words are written to the memory at any one time.
Using this command the entire memory can be
programmed in 16s, compared to 72s using the
standard Word Program.
The end of a Program or Erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards. Chip Enable
and Output Enable signals control the bus opera-
tion of the memory. They allow simple connection
to most microprocessors, often without additional
logic.
V
). In Read mode the A22/V pin works as an
PP
PP
address pin; in Program or Erase mode it also
works as a voltage supply pin. At the beginning of
any program or erase operation, a specific proce-
dure (see Figure 4) must be performed to internal-
ly memorize the A22 value that will be used during
the program or erase operation.
The device is composed of two 64Mbit memories
stacked in a single package. Recommended oper-
ating conditions do not allow both memories to be
active at the same time. Address A22 selects the
memory to be enabled. The other memory is in
Standby mode.
The memory is offered in SO44 package and is
supplied with all the bits set to ’1’).
The memory is divided into 64 uniform blocks that
can be erased independently so it is possible to
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A21
Address Inputs
Address Input/Supply Voltage for
Program/Erase
V
A22/V
PP
CC
A22/V
PP
DQ0-DQ15
Data Inputs/Outputs
Chip Enable
22
16
E
A0-A21
DQ0-DQ15
G
Output Enable
Supply Voltage read
Ground
V
CC
M59PW1282
E
V
SS
G
V
SS
AI07209
4/24
M59PW1282
Figure 3. SO Connections
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
2
3
4
A9
5
A10
A11
A12
A13
A14
A15
A16
A22/V
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M59PW1282
PP
V
V
SS
DQ15
SS
G
DQ0
DQ8
DQ7
DQ14
DQ6
DQ1
DQ9
DQ13
DQ5
DQ2
DQ10
DQ3
DQ12
DQ4
DQ11
V
CC
AI07208
5/24
M59PW1282
Table 2. Block Addresses
Block Number
Address Range
3E0000h-3FFFFFh
3C0000h-3DFFFFh
3A0000h-3BFFFFh
380000h-39FFFFh
360000h-37FFFFh
340000h-35FFFFh
320000h-33FFFFh
300000h-31FFFFh
2E0000h-2FFFFFh
2C0000h-2DFFFFh
2A0000h-2BFFFFh
280000h-29FFFFh
260000h-27FFFFh
240000h-25FFFFh
220000h-23FFFFh
200000h-21FFFFh
1E0000h-1FFFFFh
1C0000h-1DFFFFh
1A0000h-1BFFFFh
180000h-19FFFFh
160000h-17FFFFh
140000h-15FFFFh
120000h-13FFFFh
100000h-11FFFFh
0E0000h-0FFFFFh
0C0000h-0DFFFFh
0A0000h-0BFFFFh
080000h-09FFFFh
060000h-07FFFFh
040000h-05FFFFh
020000h-03FFFFh
000000h-01FFFFh
Block Number
Address Range
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
7E0000h-7FFFFFh
7C0000h-7DFFFFh
7A0000h-7BFFFFh
780000h-79FFFFh
760000h-77FFFFh
740000h-75FFFFh
720000h-73FFFFh
700000h-71FFFFh
6E0000h-6FFFFFh
6C0000h-6DFFFFh
6A0000h-6BFFFFh
680000h-69FFFFh
660000h-67FFFFh
640000h-65FFFFh
620000h-63FFFFh
600000h-61FFFFh
5E0000h-5FFFFFh
5C0000h-5DFFFFh
5A0000h-5BFFFFh
580000h-59FFFFh
560000h-57FFFFh
540000h-55FFFFh
520000h-53FFFFh
500000h-51FFFFh
4E0000h-4FFFFFh
4C0000h-4DFFFFh
4A0000h-4BFFFFh
480000h-49FFFFh
460000h-47FFFFh
440000h-45FFFFh
420000h-43FFFFh
400000h-41FFFFh
8
7
6
5
4
3
2
1
6/24
M59PW1282
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Write operations they represent the command
sent to the Command Interface of the Program/
Erase Controller. When reading the Status Regis-
ter they report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Interface does not
use these bits. When reading the Status Register
these bits should be ignored.
Address/Voltage Supply (A22/V ). The
PP
A22/V signal has two functions.
During read operations the A22/V signal works
as an address input, which is used to select the
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
PP
PP
tions, when V is in the V range.
PP
HH
Top (A22 = V ) or Bottom (A22 = V ) die.
IH
IL
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operations of the memory. It
During program or erase operations it also works
as a V voltage supply pin. At the beginning of
PP
also allows Bus Write operations, when V is in
PP
any program or erase operation, a specific proce-
dure (see Figure 4) must be performed to internal-
ly memorize the A22 value that will be used during
the program or erase operation.
the V range.
HH
V
Supply Voltage. The V
Supply Voltage
CC
CC
supplies the power for Read operations.
When the V is in the V
DC Characteristic, for the relevant values) pro-
range (see Table 12,
HH
A 0.1µF capacitor should be connected between
PP
the V
Supply Voltage pin and the V Ground
CC SS
gram and erase operations are enabled. During
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
such operations V
must be stable in the V
HH
PP
range. Program and erase operation are not al-
lowed when V is below the V range.
tions, I .
PP
HH
CC3
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Vss Ground. The V
for all voltage measurements.
Ground is the reference
SS
7/24
M59PW1282
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
be held within V ± 0.2V. For the Standby current
CC
level see Table 12, DC Characteristics.
During program operation the memory will contin-
Inputs and applying a Low signal, V , to Chip En-
IL
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 12, Read AC
Waveforms, and Table 12, Read AC Characteris-
tics, for details of when the output becomes valid.
ue to use the Program Supply Current, I
, for
CC3
Program operation until the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
During read array operations A22 selects Top
(A22 = V ) or Bottom (A22 = V ) die.
IH
IL
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
duced to the Standby Supply Current, I
. The
CC2
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
when V is set to V . A valid Bus Write opera-
PP
HH
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Enable. Output Enable must remain High, V ,
IH
during the whole Bus Write operation. See Figure
12, Write AC Waveforms, and Table 14, Write AC
Table 3. Bus Operations
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15-DQ0
(2)
PP
Operation
Bus Read
E
G
A22/V
(3)
V
V
IL
Cell Address
Data Output
V /V
IL
IL
IL IH
(4)
V
V
IH
V
IH
Bus Write
Command Address
Data Input
Hi-Z
V
HH
Output Disable
Standby
X
X
X
X
X
V
IH
X
Hi-Z
A0 = V , A1 = V ,
Read Manufacturer
Code
IL
IL
V
V
V
V
0020h
88AAh
IL
IL
IL
IL
HH
Others V or V
IL
IH
A0 = V , A1 = V ,
IH
IL
V
V
HH
Read Device Code
Others V or V
IL
IH
Note: 1. X = V or V
.
IH
IL
2. When reading the Status Register during a program operation A22/V must be kept at V
.
HH
PP
3. V enables the Bottom die, V enables the Top die during read array operation.
IL
IH
4. V after latching A22 at V or V .
IH
HH
IL
8/24
M59PW1282
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 4 and 5, for a summary of the com-
mands.
As the device contains two internal memories care
must be taken to issue the commands to the cor-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the P/E.C.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
rect address. To select the Top die (A22 = V ) or
IH
the Bottom die (A22 = V ) the A22 latch procedure
(see Figure 4) must be followed.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
IL
It is not necessary to repeat the A22 latch proce-
dure if all the commands are issued to the same
die, unless the power supply V is switched off.
CC
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
V
must be set to V
during the Read/Reset
PP
HH
once. V must be set to V during Multiple Word
PP
HH
command. If V is set to either V or V the com-
PP
IL
IH
Program. If V is set either V or V the com-
PP
IL
IH
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the P/E.C. has started (see Table 8 and
Figure 8).
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. V
PP
must be set to V
during the Auto Select com-
HH
mand. If V is set to either V or V the com-
PP
IL
IH
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 5, Multiple Word Program and Figure
7, Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the P/E.C. is ready to accept the op-
eration (see Table 8 and Figure 8).
with A0 = V and A1 = V . The other address bits
IL
IL
may be set to either V or V .
IL
IH
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V .
IL
IH
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. V must be
The Program Phase is executed in three different
sub-phases:
PP
set to V during Word Program. If V is set to ei-
HH
PP
ther V or V the command will be ignored, the
data will remain unchanged and the device will re-
1. The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
IL
IH
9/24
M59PW1282
Start Address and the first Word to be
programmed.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 6.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
2. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A21 equal to the
Start Address), that indicates to the PC that the
Program Phase has to continue. A0 to A16 are
‘don’t care’.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’.
Block Erase Command.
3. Finally, after all Words have been programmed,
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
th
a Bus Write operation (the (n+1) ) with a Final
Address, FA (A17 or a higher address pin
different from the Start Address), ends the
Program Phase.
V
must be set to V during Block Erase. If V
HH PP
PP
is set to either V or V the command will be ig-
IL
IH
The memory is now set to enter the Verify Phase.
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the P/E.C. is ready for the next oper-
ation or if the reprogram of the location has failed
(see Table 8 and Figure 8).
Six Bus Write operations are required to select the
block . The Block Erase operation starts the P/E.C.
after the last Bus Write operation. The Status Reg-
ister can be read after the sixth Bus Write opera-
tion. See the Status Register for details on how to
identify if the P/E.C. has started the Block Erase
operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
Three successive steps are required to execute
the Verify Phase of the command:
1. The first Bus Write operation of the Verify Phase
latches the Start Address and the Word to be
verified.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
2. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A21
equal to the Start Address).
Chip Erase Command.
3. Finally, after all Words have been verified, a Bus
Write cycle with a Final Address, FA (A17 or a
higher address pin different from the Start
Address) ends the Verify Phase.
The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
V
must be set to V during Chip Erase. If V
HH PP
PP
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 8
and Figure 8).
If the Verify Phase accomplishes successfully, the
memory returns to the Read mode and DQ6 stops
toggling.
On the contrary, if the P/E.C. fails to reprogram a
given location, the Verify Phase terminates, DQ6
continues toggling and error bit DQ5 is set in the
is set to either V or V the command will be ig-
IL IH
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the P/E.C.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
Status Register. If the error is due to a V failure
PP
DQ4 is also set.
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
10/24
M59PW1282
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
Table 4. Standard Commands
Bus Write Operations
Command
1st
2nd
Data
3rd
4th
5th
6th
Add
X
Data
F0
Add
Add
Data
Add
Data
Add
Data
Add
Data
1
3
3
4
6
6
Read/Reset
555
555
555
555
555
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
X
F0
90
A0
80
80
Auto Select
Word Program
Block Erase
Chip Erase
555
555
555
555
PA
555
555
PD
AA
AA
2AA
2AA
55
55
BA
30
10
555
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command
Bus Write Operations
Phase
1st
Add Data Add Data Add Data Add Data Add Data
555 AA 2AA 55 555 20
2nd
3rd
4th
5th
nth
Final
Add Data Add Data
Set-Up
3
Program n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
Verify n+1 SA PD1 CA PD2 CA PD3 CA PD4 CA PD5
CA PAn
CA PAn
FA
FA
X
X
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Typical after
(1)
Parameter
Min
Max
Unit
Typ
80
(1)
10k W/E Cycles
Chip Erase
85
120
6
s
Block Erase (128 KWords)
Program (Word)
1.5
9
s
200
280
280
µs
Chip Program (Multiple Word)
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
16
72
s
s
10,000
cycles
Note: 1. T = 25°C, V = 12V.
A
PP
11/24
M59PW1282
Figure 4. A22 Latch Procedure Waveforms
tA9HA9L
V
TL
A9
A22 latched on
TL rising edge
tA22VA9TL
A22/V
VALID A22
PP
A0-A8;
A10-A21
E
AI07257
Note: G = V ; DQ0–DQ15 are Don’t care; V = 10.5 ± 0.25V; V = 2.7 to 3.6V.
IH
TL
CC
Table 7. A22 Latch Procedure AC Characteristics
Symbol
Parameter
A22 valid to A9 at Third Level
A9 High to A9 Low
Min
1
Unit
t
µs
µs
A22VA9TL
t
1
A9HA9L
Figure 5. Programming Flowchart
Figure 6. Chip Erase Flowchart
Start
Start
A22 Latch procedure
A22 Latch procedure
with A22 = V
with A22 = V
IH
IH
Program Command
execution on
Chip Erase Command
execution on
64Mbit Top die
64Mbit Top die
A22 Latch procedure
A22 Latch procedure
with A22 = V
with A22 = V
IL
IL
Program Command
execution on
Chip Erase Command
execution on
64Mbit Bottom die
64Mbit Bottom die
READ (verify pattern)
on 128Mbit
Blank check
on 128Mbit
End
End
AI08208
AI08209
12/24
M59PW1282
Figure 7. Multiple Word Program Flowchart for 64Mbit Top and Bottom Die
Start
Setup
Verify
Phase
Phase
Read Status
Register
Write AAh
Address 555h
Write 55h
Address 2AAh
NO
DQ0 = 0?
Write 20h
Address 555h
Write Data1
Start Address
Read Status
Register
Read Status
Register
NO
NO
DQ5 = 1 ?
NO
NO
DQ6
Setup time
exceeded?
NO
toggling?
DQ0 = 0?
YES
YES
YES
YES
Write Data 2
Continue Address
EXIT (setup failed)
DQ0 = 0?
YES
Write Data1
Start Address
Read Status
Register
Program
Phase
NO
Read Status
Register
NO
DQ0 = 0?
YES
DQ5 = 1?
YES
NO
NO
NO
DQ0 = 0?
Write Data n
Continue Address
YES
Write Data 2
Continue Address
Read Status
Register
NO
Read Status
Register
NO
DQ0 = 0?
YES
DQ5 = 1?
YES
Exit
Phase
DQ0 = 0?
YES
Read Status
Register
Write XX
Final Address
Write Data n
Continue Address
YES
NO
DQ4 = 0?
Read Status
Register
Fail error
Read Status
Register
Fail, VPP error
YES
DQ6
toggling?
Write F0h
Address XX
DQ0 = 0?
YES
NO
Write XX
Final Address
Exit (read mode)
AI05954b
13/24
M59PW1282
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. The bits in the Status Register
are summarized in Table 8, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the P/E.C. has suc-
cessfully completed its operation. The Data Poll-
ing Bit is output on DQ7 when the Status Register
is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
V
Status Bit (DQ4). The V Status Bit can be
PP
PP
used to identify if any Program or Erase operation
has failed due to a V error. If V falls below V
PP
PP
HH
during any Program or Erase operation, the oper-
ation aborts and DQ4 is set to ‘1’. If V remains at
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
PP
V
throughout the Program or Erase operation,
HH
the operation completes and DQ4 is set to ‘0’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of P/E.C. operation
during a Block Erase command. Once the P/E.C.
starts erasing the Erase Timer Bit is set to ’1’. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the P/E.C. dur-
ing Block Erase operations. The Alternative Tog-
gle Bit is output on DQ2 when the Status Register
is read.
Figure 8, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
During Block Erase operations the Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc., with successive
Bus Read operations from addresses within the
block being erased. Once the operation completes
the memory returns to Read mode.
After an Erase operation that causes the Error Bit
to be set, the Alternative Toggle Bit can be used to
identify where the error occurred. The Alternative
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read Operations from addresses
within a block that has not erased correctly. The
Alternative Toggle Bit does not change if the ad-
dressed block has erased correctly.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the P/E.C. is active or inactive during Multiple
Word Program. When the P/E.C. has written one
Word and is ready to accept the next Word, the bit
is set to ‘0’.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the P/E.C. has successfully com-
pleted its operation. The Toggle Bit is output on
DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
Figure 9, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the P/E.C. The Error Bit
is set to ’1’ when a Program, Block Erase or Chip
Erase operation fails to write the correct data to
the memory. If the Error Bit is set a Read/Reset
command must be issued before other commands
are issued. The Error bit is output on DQ5 when
the Status Register is read.
Status Register Bit DQ1 is reserved.
14/24
M59PW1282
Table 8. Status Register Bits
(1)
P/E.C. Status
Programming
Waiting for data
Program fail
Address
DQ7
–
DQ6
DQ5 DQ4 DQ3
DQ2
DQ0
Command
–
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
1
0
1
0
–
0
0
0
0
0
1
–
1
0
1
–
–
–
Multiple Word
Program
–
–
–
–
(2)
–
–
–
Programming
Program error
–
DQ7
DQ7
0
–
–
–
Word Program
(2)
–
In erasing block
–
–
Toggle
Erasing
Not in
erasing block
0
0
0
Toggle
Toggle
Toggle
0
1
1
1
1
1
No Toggle
Toggle
–
–
–
Chip Erase/
Block Erase
(2)
(2)
In failed block
Erase fail
Not in
failed block
No Toggle
Note: 1. Unspecified data bits should be ignored.
2. DQ4 = 0 if V ≥ V during Program/Erase algorithm execution; DQ4 = 1 if V < V during Program/Erase algorithm execution.
PP
HH
PP
HH
Figure 8. Data Polling Flowchart
Figure 9. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
PASS
YES
FAIL
PASS
AI03598
AI01370B
15/24
M59PW1282
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 9. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
–65
Max
125
150
Unit
°C
T
Temperature Under Bias
Storage Temperature
BIAS
T
°C
STG
(1,2)
V
+0.6
–0.6
–0.6
–0.6
V
V
V
V
CC
Input or Output Voltage
Read Supply Voltage
IO
V
4
CC
(3)
V
PP
13.5
Program/Erase Supply Voltage
Note: 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V for less than 20ns during transitions.
CC
3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. V must not remain at V for more than a total
PP
HH
of 80hrs.
16/24
M59PW1282
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 10, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
Parameter
M59PW1282
100, 120
Unit
Min
2.7
11.4
0
Max
3.6
V
V
Read Supply Voltage
V
V
CC
Program/Erase Supply Voltage
12.6
70
PP
Ambient Operating Temperature (T )
°C
pF
ns
V
A
Load Capacitance (C )
30
L
Input Rise and Fall Times
10
Input Pulse Voltages
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Figure 10. AC Measurement I/O Waveform
Figure 11. AC Measurement Load Circuit
1.3V
1N914
3V
1.5V
0V
3.3kΩ
AI05546
DEVICE
UNDER
TEST
OUT
C
L
C = 30pF
L
C includes JIG capacitance
L
AI05447
Table 11. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
12
Unit
pF
C
V
IN
= 0V
= 0V
IN
C
V
OUT
24
pF
OUT
C
A22/V Capacitance
V
= 0V
50
pF
A22/Vpp
PP
A22/Vpp
Note: Sampled only, not 100% tested.
17/24
M59PW1282
Table 12. DC Characteristics
(1)
Symbol
Test Condition
Min
Max
±1
Unit
µA
Parameter
I
LI
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Supply Current (Standby)
Supply Current (Program)
Input Low Voltage
IN
CC
I
0V ≤ V ≤ V
OUT CC
±1
µA
LO
I
E = V , G = V , f = 6MHz
IL IH
10
mA
CC1
(2)
E = V ±0.2V
150
20
µA
mA
V
I
CC
CC2
I
P/E.C. active
CC3
V
V
–0.5
0.8
IL
0.7V
V
+0.3
Input High Voltage
V
IH
CC
CC
V
V
I
= 1.8mA
Output Low Voltage
0.45
V
OL
OL
V
–0.4
CC
Output High Voltage
I
= –100µA
V
OH
HH
OH
V
I
V
V
Program Voltage
Current (Program)
11.4
12.6
10
V
PP
P/E.C. Active
mA
HH
PP
Note: 1. V must be applied simultaneously or before V and removed simultaneously or after V .
PP
CC
PP
2. Average Value.
18/24
M59PW1282
Figure 12. Read AC Waveforms
A0-A22
VALID
tAVQV
tAXQX
E
tELQV
tEHQZ
G
tGLQV
tGHQZ
VALID
DQ0-DQ15
AI08232
Table 13. Read AC Characteristics
M59PW1282
(1)
Symbol Alt
Test Condition
100
120
Unit
Parameter
V
CC
= 3.0 to 3.6V V = 2.7 to 3.6V V = 2.7 to 3.6V
CC
CC
E = V ,
Address Valid to
Output Valid
IL
t
t
t
t
ACC
Max
90
90
35
30
30
0
100
100
35
30
30
0
120
120
35
30
30
0
ns
ns
ns
ns
ns
ns
AVQV
G = V
IL
Chip Enable Low to
Output Valid
t
G = V
Max
Max
Max
Max
Min
ELQV
CE
IL
Output Enable Low to
Output Valid
t
E = V
IL
GLQV
OE
Chip Enable High to
Output Hi-Z
(2)
t
G = V
t
HZ
IL
EHQZ
Output Enable High
to Output Hi-Z
(2)
t
E = V
t
DF
IL
GHQZ
Address Transition to
Output Transition
t
t
OH
AXQX
Note: 1. V must be applied after V and with the Chip Enable (E) at V .
IH
PP
CC
2. Sampled only, not 100% tested.
19/24
M59PW1282
Figure 13. Write AC Waveforms, Chip Enable Controlled
A0-A21
VALID
tELAX
tAVEL
tEHGL
G
E
tGHEL
tELEH
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ15
V
CC
tVCHEL
tVPHEL
A22/V
PP
AI08233
Table 14. Chip Enable Controlled, Write AC Characteristics
(1)
Symbol
Alt
M59PW1282
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
Parameter
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
t
t
Min
Min
Min
Min
Min
Min
Min
Min
Min
50
50
0
ELEH
CP
t
t
DVEH
DS
t
t
Chip Enable High to Input Transition
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
EHDX
DH
t
t
50
0
EHEL
CPH
t
t
AS
AVEL
t
t
AH
100
10
10
50
ELAX
t
GHEL
t
t
EHGL
OEH
t
t
t
V
V
High to Chip Enable Low
High to Chip Enable Low
VCHEL
VCS
CC
(2)
Min
500
ns
t
VCS
PP
VPHEL
Note: 1. T = 25°C; A22/V = 11.4 to 12.6V; V = 2.7 to 3.6V.
A
PP
CC
V
must be applied after V and with the Chip Enable (E) at V .
PP
CC IH
Sampled only, not 100% tested.
2. Not required in Auto Select or Read/Reset command sequences.
20/24
M59PW1282
PACKAGE MECHANICAL
Figure 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline
D
44
23
c
E1 E
θ
1
22
A1
L
A2
A
L1
ddd
b
e
SO-F
Note: Drawing is not to scale.
Table 15. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
3.00
0.118
0.10
2.69
0.004
0.106
2.56
0.35
2.79
0.50
0.28
28.63
0.10
16.28
12.73
–
0.101
0.014
0.007
1.117
0.110
0.020
0.011
1.127
0.004
0.641
0.501
–
c
0.18
D
28.50
28.37
1.122
ddd
E
16.03
12.60
1.27
15.77
12.47
–
0.631
0.496
0.050
0.031
0.068
0.621
0.491
–
E1
e
L
0.79
L1
θ
1.73
8°
8°
N
44
44
21/24
M59PW1282
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M59PW1282
100 M
1
T
Device Type
M59P = LightFlash™ Memory
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
128 = 128 Mbit (x16)
Device Function
2 = 2 dice stacked
Speed
(1)
100 = 100 ns
120 = 120 ns
Package
M = SO44, 500mils body width
Temperature Range
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
Note: 1. This speed also guarantees 90ns access time at V = 3.0 to 3.6V.
CC
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
22/24
M59PW1282
REVISION HISTORY
Table 17. Document Revision History
Date
Version
1.0
Revision Details
20-Jan-2003
06-Feb-2003
First Issue
2.0
Part Number changed
Document Status changed to Preliminary Data
Document extended to full size
07-Mar-2003
3.0
100ns speed class guarantees 90ns at V
= 3.0 to 3.6V
29-Apr-2003
20-Nov-2003
3.1
3.2
CC
Datasheet status updated to “Full Datasheet”.
23/24
M59PW1282
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
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24/24
相关型号：
M59PW1282120M1T
128Mbit (two 64Mb, x16, Uniform Block, LightFlash⑩) 3V Supply, Multiple Memory Product
STMICROELECTR
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