M58BW032DB55T6 [STMICROELECTRONICS]
IC,EEPROM,NOR FLASH,1MX32,CMOS,QFP,80PIN,PLASTIC;型号: | M58BW032DB55T6 |
厂家: | ST |
描述: | IC,EEPROM,NOR FLASH,1MX32,CMOS,QFP,80PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
文件: | 总60页 (文件大小:826K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M58BW032BT, M58BW032BB
M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst)
3.3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■
SUPPLY VOLTAGE
Figure 1. Packages
–
–
VDD = 3.0V to 3.6V for Program, Erase
and Read
VDDQ = VDDQIN = 1.6V to 3.6V for I/O
Buffers
■
HIGH PERFORMANCE
–
–
Access Time: 45, 55 and 60ns
75MHz Effective Zero Wait-State Burst
Read
PQFP80 (T)
–
–
Synchronous Burst Reads
Asynchronous Page Reads
■
MEMORY ORGANIZATION
– Eight 64 Kbit small parameter Blocks
BGA
– Four 128Kbit large parameter Blocks (of
which one is OTP)
– Sixty-two 512Kbit main Blocks
LBGA80 (ZA)
10 x 8 ball array
■
■
HARDWARE BLOCK PROTECTION
–
–
WP pin Lock Program and Erase
VPEN signal for Program/Erase Enable
SOFTWARE BLOCK PROTECTION
■
■
ELECTRONIC SIGNATURE
–
Tuning Protection to Lock Program and
Erase with 64-bit User Programmable
Password (M58BW032B version only)
–
–
–
Manufacturer Code: 20h
Top Device Code M58BW032xT: 8838h
Bottom Device Code M58BW032xB:
8837h
■
■
■
SECURITY
–
64-bit Unique Device Identifier (UID)
OPERATING TEMPERATURE RANGE
FAST PROGRAMMING
–
–
Automotive (Grade 3): –40 to 125°C
Industrial (Grade 6): –40 to 90°C
–
Write to Buffer and Program capability
OPTIMIZED FOR FDI DRIVERS
–
–
Common Flash Interface (CFI)
Fast Program/Erase Suspend feature in
each block
■
LOW POWER CONSUMPTION
100µA Typical Standby
–
November 2004
1/60
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. LBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. PQFP Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Tuning Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB . . . . . . . . . . . . . . . . . . . 12
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable (GD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Supply Voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ground (VSS and VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Don’t Use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Reset/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Synchronous Burst Read Bus Operations
Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby Disable Bit (M14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Wrap Burst Bit (M3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Example Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Erase All Main Blocks Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Buffer and Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tuning Protection Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tuning Protection Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Set Block Protection Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clear Block Protection Configuration Register Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 27
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program/ Write to Buffer and Program/Tuning Protection Unlock Status (Bit 4) . . . . . . . . . . 28
VPEN Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6. AC Measurement Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Asynchronous Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . 34
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . . 34
Figure 10.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11.Asynchronous Write AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12.Asynchronous Latch Controlled Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . . 38
Figure 13.Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . . . 39
Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14.Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . . . 40
Figure 15.Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . . 41
Figure 16.Synchronous Burst Read - Burst Address Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17.Reset, Power-Down and Power-up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Reset, Power-Down and Power-up AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18.LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline . . . . . . 43
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . 43
Figure 19.PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline . . . . . . . . . . . . . . . . . . . . . 44
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data. . . . . . . . . . . . . . 44
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A.FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 23.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 24.Unlock Device and Change Tuning Protection Code Flowchart . . . . . . . . . . . . . . . . . . . 50
4/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 25.Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . 51
Figure 26.Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . . 52
Figure 27.Power-up Sequence to Burst the Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28.Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . . 54
Figure 29.Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . . 55
Figure 30.Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . . 56
Figure 31.Command Interface and Program Erase Controller Flowchart (d) . . . . . . . . . . . . . . . . . 57
Figure 32.Command Interface and Program Erase Controller Flowchart (e) . . . . . . . . . . . . . . . . . 58
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SUMMARY DESCRIPTION
The M58BW032B/D is a 32Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a Double-
Word basis using a 3.0V to 3.6V VDD supply for the
circuit and a VDDQ supply down to 1.6V for the In-
put and Output buffers.
can be programmed and erased over 100,000 cy-
cles.
All blocks are protected during power-up. The
M58BW032B features four different levels of hard-
ware and software block protection to avoid un-
wanted program/erase operations:
The devices support Asynchronous (Latch Con-
trolled and Page Read) and Synchronous Bus op-
erations. The Synchronous Burst Read Interface
allows a high data transfer rate controlled by the
Burst Clock, K, signal. It is capable of bursting
fixed or unlimited lengths of data. The burst type,
latency and length are configurable and can be
easily adapted to a large variety of system clock
frequencies and microprocessors. All Writes are
Asynchronous. On power-up the memory defaults
to Read mode with an Asynchronous Bus.
The device features an asymmetrical block archi-
tecture. The M58BW032B/D has an array of 62
main blocks of 512 Kbits each, plus 4 large param-
eter blocks of 128Kbits each and 8 small parame-
ter blocks of 64 Kbits each. The large and small
parameter blocks are located either at the top
(M58BW032BT, M58BW032DT) or at the bottom
(M58BW032BB, M58BW032DB) of the address
space. The first large parameter block is referred
to as Boot Block and can be used either to store a
boot code or parameters. The memory array orga-
nization is detailed in Tables 2, Top Boot Block Ad-
dresses and 3, Bottom Boot Block Addresses.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
■
Write/Protect Enable input, WP, provides a
hardware protection of a combination of
blocks from program or erase operations. The
Block Protection configuration can be defined
individually by issuing a Set Block Protection
Configuration Register or Clear Block
Protection Configuration Register commands.
All Program or Erase operations are blocked
when Reset, RP, is held low.
A Program/Erase Enable input, VPEN, is used
to protect all blocks, preventing Program and
Erase operations from affecting their data.
The Program and Erase commands can be
password protected by the Tuning Protection
command.
■
■
■
The M58BW032D offers the same protection fea-
tures with the exception of the Tuning Block Pro-
tection which is disabled in the factory.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consump-
tion is reduced to the standby level, the device is
write protected and both the Status and Burst Con-
figuration Registers are cleared. A recovery time is
required when the RP input goes High.
A manufacturer and device code are available.
They can be read from the memory allowing pro-
gramming equipment or applications to automati-
cally match their interface to the characteristics of
the memory.
Finally, the M58BW032B/D features a Unique De-
vice Identifier (UID) which is programmed by ST. It
is unique for each die and can be used to imple-
ment cryptographic algorithms to improve securi-
ty.
The memory is offered in PQFP80 (14 x 20mm)
and LBGA80 (1.0mm pitch) packages and it is
supplied with all the bits erased (set to ’1’).
6/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 1. Signal Names
Figure 2. Logic Diagram
A0-A19
Address inputs
DQ0-DQ7
Data Input/Output, Command Input
V
V
V
Data Input/Output, Burst Configuration
Register
V
DD DDQ DDQIN
PEN
DQ8-DQ15
DQ16-DQ31 Data Input/Output
B
Burst Address Advance
Chip Enable
A0-A19
DQ0-DQ31
E
K
L
G
Output Enable
K
Burst Clock
M58BW032BT
M58BW032BB
M58BW032DT
M58BW032DB
E
L
Latch Enable
RP
G
R
R
Valid Data Ready
RP
W
GD
WP
Reset /Power-Down
Write Enable
GD
W
Output Disable
Write Protect
WP
B
V
Supply Voltage
DD
V
Power Supply for Output Buffers
Power Supply for Input Buffers only
Program/Erase Enable
Ground
DDQ
V
V
V
V
DDQIN
PEN
SS
V
V
SSQ
SS
AI08918b
Input/Output Ground
Not Connected Internally
Don’t Use as Internally Connected
SSQ
NC
DU
7/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 3. LBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A15
A14
V
V
V
A6
A3
A2
DD
PEN
A9
SS
A16
A17
DQ3
A13
A18
A12
A11
A19
DQ2
DQ6
DQ10
DQ11
L
A8
NC
A5
A7
A4
DU
A1
A0
A10
DU
DQ0
DQ4
DQ7
DQ8
DQ12
DQ14
RP
NC
DQ31
DQ28
DQ25
DQ21
DQ19
G
DQ30
DQ26
DQ24
DQ23
DQ18
R
DQ29
V
DQ1
DQ5
DQ9
WP
B
DQ27
NC
V
DDQ
DDQ
V
V
SSQ
SSQ
G
H
J
V
DQ22
DQ17
E
V
DDQ
DDQ
DQ13
DQ15
DQ20
DQ16
DU
K
V
K
V
V
W
GD
DDQIN
SS
DD
AI08920b
8/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 4. PQFP Connections (Top view through package)
DQ16
DQ17
DQ18
DQ19
1
DQ15
DQ14
DQ13
DQ12
64
V
V
V
DDQ
SSQ
DDQ
V
SSQ
DQ20
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
M58BW032BT
M58BW032BB
M58BW032DT
12
53
M58BW032DB
V
V
V
DDQ
SSQ
DDQ
V
SSQ
DQ28
DQ3
DQ2
DQ1
DQ0
A19
A18
A17
A16
DQ29
DQ30
DQ31
DU
A0
A1
A2
41
24
AI08919c
9/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Block Protection
Block Protection. When the two protections are
disabled, WP and RP at VIH, the blocks locked by
the Tuning Block Protection cannot be modified.
All blocks are protected at power-up.
The M58BW032B features four different levels of
block protection. The M58BW032D has the same
block protection with the exception of the Tuning
Block Protection, which is disabled in the factory.
Tuning Block Protection
■
Write Protect Pin, WP, - When WP is Low,
VIL, the protection status that has been
configured in the Block Protection
Configuration Register is activated. The Block
Protection Configuration Register is volatile.
Any combination of blocks is possible. Any
attempt to program or erase a protected block
will be ignored and will return an error in the
Status Register (see Table 11., Status
Register Bits).
Reset/Power-Down Pin, RP, - If the device is
held in reset mode (RP at VIL), no program or
erase operations can be performed on any
block.
Program/Erase Enable, VPEN, - VPEN
protects all blocks preventing Program and
Erase operations from affecting their data.
Program/Erase Enable must be kept High
(VIH) during all Program/Erase Controller
operations, otherwise the operations is not
guaranteed to succeed and data may become
corrupt.
The Tuning Block Protection is a software feature
to protect blocks from program or erase opera-
tions. It allows the user to lock program and erase
operations with a user definable 64 bit code. It is
only available on the M58BW032B version.
The code is written once in the Tuning Protection
Register and cannot be erased. When shipped the
flash memory will have the Tuning Protection
Code bits set to ‘1'. The user can program a ‘0’ in
any of the 64 positions. Once programmed it is not
possible to reset a bit to ‘1’ as the cells cannot be
erased. The Tuning Protection Register can be
programmed at any moment (after providing the
correct code), however once all bits are set to ‘0’
the Tuning Protection Code can no longer be al-
tered.
The Tuning Protection Code locks the program
and erase operations of all the blocks except for
blocks 12 and 13 for the bottom configuration, and
blocks 60 and 61 for the top configuration.
The tuning blocks are "locked" if the tuning protec-
tion code has not been provided, and “unlocked"
once the correct code has been provided. The tun-
ing blocks are locked after reset or power-up. The
tuning protection status can be monitored in the
Status Register. Refer to the Status Register sec-
tion.
■
■
■
Tuning Block Protection - M58BW032B
features a 64 bit password protection for
program and erase operations for a fixed
number of blocks After power-up or reset the
device is tuning protected. An Unlock
command is provided to allow program or
erase operations in all the blocks.
Refer to the Command Interface section for the
Tuning Protection Block Unlock and Tuning Pro-
tection Program commands. See Appendix A, Fig-
ure 24, 25 and 26 for suggested flowcharts for
using the Tuning Block Protection commands.
After a device reset the first two kinds of block pro-
tection (WP, RP) can be combined to give a flexi-
ble block protection. They do not affect the Tuning
10/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 2. Top Boot Block Addresses,
M58BW032BT, M58BW032DT
(1)
(2)
#
Size (Kbit)
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
Address Range
TP
yes
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
90000h-93FFFh
8C000h-8FFFFh
88000h-8BFFFh
84000h-87FFFh
80000h-83FFFh
7C000h-7FFFFh
78000h-7BFFFh
74000h-77FFFh
70000h-73FFFh
6C000h-6FFFFh
68000h-6BFFFh
64000h-67FFFh
60000h-63FFFh
5C000h-53FFFFh
58000h-5BFFFh
54000h-57FFFh
50000h-53FFFh
4C000h-4FFFFh
48000h-4BFFFh
44000h-47FFFh
40000h-43FFFh
3C000h-3FFFFh
38000h-3BFFFh
34000h-37FFFh
30000h-33FFFh
2C000h-2FFFFh
28000h-2BFFFh
24000h-27FFFh
20000h-23FFFh
1C000h-1FFFFh
18000h-1BFFFh
14000h-17FFFh
10000h-13FFFh
0C000h-0FFFFh
08000h-0BFFFh
04000h-07FFFh
00000h-03FFFh
(1)
(2)
#
Size (Kbit)
128
128
128
128
64
Address Range
FF000h-FFFFh
TP
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
(3)
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
FE000h-FEFFFh
FD000h-FDFFFh
FC000h-FCFFFh
FB800h-FBFFFh
FB000h-FB7FFh
FA800h-FAFFFh
FA000h-FA7FFh
F9800h-F9FFFh
F9000h-F97FFh
F8800h-F8FFFh
F8000h-F87FFh
F4000h-F7FFFh
F0000h-F3FFFh
EC000h-EFFFFh
E8000h-EBFFFh
E4000h-E7FFFh
E0000h-E3FFFh
DC000h-DFFFFh
D8000h-DBFFFh
D4000h-D7FFFh
D0000h-D3FFFh
CC000h-CFFFFh
C8000h-CBFFFh
C4000h-C7FFFh
C0000h-C3FFFh
BC000h-BFFFFh
B8000h-BBFFFh
B4000h-B7FFFh
B0000h-B3FFFh
AC000h-AFFFFh
A8000h-ABFFFh
A4000h-A7FFFh
A0000h-A3FFFh
9C000h-9FFFFh
98000h-9BFFFh
94000h-97FFFh
64
64
64
64
64
64
64
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
8
7
6
5
4
3
2
1
0
Note: 1. Addresses are indicated in 32-bit addressing.
2. TP = Tuning Protected Block, only available for the
M58BW032B.
3. OTP Block.
11/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 3. Bottom Boot Block Addresses,
(1)
(2)
#
Size (Kbit)
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
64
Address Range
TP
yes
M58BW032BB, M58BW032DB
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
64000h-67FFFh
60000h-63FFFh
5C000h-53FFFFh
58000h-5BFFFh
54000h-57FFFh
50000h-53FFFh
4C000h-4FFFFh
48000h-4BFFFh
44000h-47FFFh
40000h-43FFFh
3C000h-3FFFFh
38000h-3BFFFh
34000h-37FFFh
30000h-33FFFh
2C000h-2FFFFh
28000h-2BFFFh
24000h-27FFFh
20000h-23FFFh
1C000h-1FFFFh
18000h-1BFFFh
14000h-17FFFh
10000h-13FFFh
0C000h-0FFFFh
08000h-0BFFFh
07800h-07FFFh
07000h-077FFh
06800h-06FFFh
06000h-067FFh
05800h-05FFFh
05000h-057FFh
04800h-04FFFh
04000h-047FFh
03000h-03FFFh
02000h-02FFFh
(1)
(2)
#
Size (Kbit)
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
512
Address Range
TP
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
FC000h-FFFFFh
F8000h-FBFFFh
F4000h-F7FFFh
F0000h-F3FFFh
EC000h-EFFFFh
E8000h-EBFFFh
E4000h-E7FFFh
E0000h-E3FFFh
DC000h-DFFFFh
D8000h-DBFFFh
D4000h-D7FFFh
D0000h-D3FFFh
CC000h-CFFFFh
C8000h-CBFFFh
C4000h-C7FFFh
C0000h-C3FFFh
BC000h-BFFFFh
B8000h-BBFFFh
B4000h-B7FFFh
B0000h-B3FFFh
AC000h-AFFFFh
A8000h-ABFFFh
A4000h-A7FFFh
A0000h-A3FFFh
9C000h-9FFFFh
98000h-9BFFFh
94000h-97FFFh
90000h-93FFFh
8C000h-8FFFFh
88000h-8BFFFh
84000h-87FFFh
80000h-83FFFh
7C000h-7FFFFh
78000h-7BFFFh
74000h-77FFFh
70000h-73FFFh
6C000h-6FFFFh
68000h-6BFFFh
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
64
64
8
64
7
64
6
64
5
64
4
64
3
128
128
128
128
2
(3)
1
01000h-01FFFh
0
00000h-00FFFh
Note: 1. Addresses are indicated in 32-bit Word addressing.
2. TP = Tuning Protected Block, only available for the
M58BW032B.
3. OTP Block.
12/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be Low when selecting the ad-
dresses.
at VIL, the outputs are high impedance indepen-
dently of Output Enable. The Output Disable pin
must be connected to an external pull-up resistor
as there is no internal pull-up resistor to drive the
pin.
Write Enable (W). The Write Enable, W, input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The
Reset/Power-
The address inputs are latched on the rising edge
of Latch Enable L or Burst Clock K, whichever oc-
curs first, in a read operation.The address inputs
are latched on the rising edge of Chip Enable,
Write Enable or Latch Enable, whichever occurs
first in a Write operation. The address latch is
transparent when Latch Enable is Low, VIL. The
address is internally latched in an Erase or Pro-
gram operation.
Down, RP, is used to apply a hardware reset to the
memory. A hardware reset is achieved by holding
Reset/Power-Down Low, VIL, for at least tPLPH
.
Writing is inhibited to protect data, the Command
Interface and the Program/Erase Controller are re-
set. The Status Register information is cleared and
power consumption is reduced to the standby level
(IDD1). The device acts as deselected, that is the
data outputs are high impedance.
Data Inputs/Outputs (DQ0-DQ31). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
Low, VIL, and Output Disable is at VIH, the data
bus outputs data from the memory array, the Elec-
tronic Signature, the Block Protection Configura-
tion Register, the CFI Information or the contents
of Burst Configuration Register or Status Register.
The data bus is high impedance when the device
is deselected with Chip Enable at VIH, Output En-
able at VIH, Output Disable at VIL or Reset/Power-
Down at VIL. The Status Register content is output
on DQ0-DQ7 and DQ8-DQ31 are at VIL.
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
VIH deselects the memory and reduces the power
consumption to the Standby level.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation, when Output Disable GD is at
VIH. When Output Enable G is at VIH, the outputs
are high impedance independently of Output Dis-
able.
After Reset/Power-Down goes High, VIH, the
memory will be ready for Bus Read operations af-
ter a delay of tPHEL or Bus Write operations after
tPHWL
.
If Reset/Power-Down goes Low, VIL, during a
Block Erase, a Program or a Tuning Protection
Program the operation is aborted, in a time of tPL-
RH maximum, and data is altered and may be cor-
rupted.
During Power-up power should be applied simulta-
neously to VDD and VDDQ(IN) with RP held at VIL.
When the supplies are stable RP is taken to VIH.
Output Enable, G, Chip Enable, E, and Write En-
able, W, should be held at VIH during power-up.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
erase or program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
See Table 21 and Figure 17., Reset, Power-Down
and Power-up AC Waveform, for more details.
Program/Erase Enable (VPEN). The Program./
Erase Enable input, VPEN, protects all blocks, pre-
venting Program and Erase operations from mod-
ifying the data. Program/Erase Enable must be
kept High (VIH) during all operations when the Pro-
gram/Erase Controller is active, otherwise the op-
eration is not guaranteed to succeed and data may
become corrupt.
Output Disable (GD). The Output Disable, GD,
deactivates the data output buffers. When Output
Disable, GD, is at VIH, the outputs are driven by
the Output Enable. When Output Disable, GD, is
Latch Enable (L). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L, for Asynchronous Latch
13/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Enable Controlled Read or Write or Synchronous
Burst Read operations. In Synchronous Burst
Read operations the address is latched on the ac-
tive edge of the Clock when Latch Enable is Low,
VIL. Once latched, the addresses may change
without affecting the address used by the memory.
When Latch Enable is Low, VIL, the latch is trans-
parent. Latch Enable, L, can remain at VIL for
Asynchronous Random Read and Write opera-
tions.
is or will be available. When Valid Data Ready is
Low, VIL, the previous data outputs remain active.
Write Protect (WP). The Write Protect, WP, pro-
vides protection against program or erase opera-
tions. When Write Protect, WP, is at VIL, the
protection status that has been configured in the
Block Protection Configuration Register is activat-
ed. Program and erase operations to protected
blocks are disabled. When Write Protect WP is at
VIH all the blocks can be programmed or erased, if
Burst Clock (K). The Burst Clock, K, is used to
synchronize the memory with the external bus dur-
ing Synchronous Burst Read operations. Bus sig-
nals are latched on the active edge of the Clock. In
Synchronous Burst Read mode the address is
latched on the first rising clock edge when Latch
Enable is Low, VIL, or on the rising edge of Latch
Enable, whichever occurs first.
During Asynchronous bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during Synchro-
nous Burst Read operations.
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X-latency
time has expired. If Burst Address Advance is
Low, VIL, the internal address counter advances. If
Burst Address Advance is High, VIH, the internal
address counter does not change; the same data
remains on the Data Inputs/Outputs and Burst Ad-
dress Advance is not sampled until the Y-latency
expires.
no other protection is used.
Supply Voltage (VDD). The Supply Voltage, VDD
,
is the core power supply. All internal circuits draw
their current from the VDD pin, including the Pro-
gram/Erase Controller.
Output Supply Voltage (VDDQ). The Output Sup-
ply Voltage, VDDQ, is the output buffer power supply
for all operations (Read, Program and Erase) used
for DQ0-DQ31 when used as outputs.
Input Supply Voltage (VDDQIN). The Input Sup-
ply Voltage, VDDIN, is the power supply for all input
signal. Input signals are: K, B, L, W, GD, G, E, A0-
A18 and D0-D31, when used as inputs.
Ground (VSS and VSSQ). The Ground VSS is the
reference for the internal supply voltage VDD. The
Ground VSSQ is the reference for the output and
input supplies VDDQ, and VDDQIN. It is essential to
connect VSS and VSSQ together.
Note: A 0.1µF capacitor should be connected
between the Supply Voltages, VDD, VDDQ and
VDDIN and the Grounds, VSS and VSSQ to decou-
ple the current surges from the power supply.
The PCB track widths must be sufficient to car-
ry the currents required during all operations
of the parts, see Table 15., DC Characteristics,
for maximum current supply requirements.
The Burst Address Advance, B, may be tied to VIL.
Valid Data Ready (R). The Valid Data Ready
output, R, can be used during Synchronous Burst
Read operations to identify if the memory is ready
to output data or not. The Valid Data Ready output
can be configured to be active on the clock edge
of the invalid data read cycle or one cycle before.
Valid Data Ready, at VIH, indicates that new data
Don’t Use (DU). This pin should not be used as it
is internally connected. Its voltage level can be be-
tween VSS and VDDQ or leave it unconnected.
Not Connected (NC). This pin is not physically
connected to the device.
14/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
BUS OPERATIONS
Each bus operations that controls the memory is
described in this section, see Tables 4 and 5 Bus
Operations, for a summary. The bus operation is
selected through the Burst Configuration Register;
the bits in this register are described at the end of
this section.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write. No synchronous operation
can be performed until the Burst Control Register
has been configured.
see Figure Figure 9., Asynchronous Latch Con-
trolled Bus Read AC Waveforms and Table
17., Asynchronous Latch Controlled Bus Read AC
Characteristics, for details on when the output be-
comes valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
The Electronic Signature, Block Protection Config-
uration, CFI or Status Register will be read in
asynchronous mode regardless of the Burst Con-
trol Register settings.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus Operations
For asynchronous bus operations refer to Table 4
together with the following text.
Asynchronous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Block Pro-
tection Configuration Register, Status Register,
CFI and Burst Configuration Register) in the Com-
mand Interface. A valid bus operation involves set-
ting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable and
Output Enable and keeping Write Enable and Out-
put Disable High, VIH. The Data Inputs/Outputs
will output the value, see Figure 8., Asynchronous
Bus Read AC Waveforms, and Table
16., Asynchronous Bus Read AC Characteristics.,
for details of when the output becomes valid.
Asynchronous Page Read. Asynchronous
Page Read operations are used to read from sev-
eral addresses within the same memory page.
Each memory page is 4 Double-Words and is ad-
dressed by the address inputs A0 and A1.
Data is read internally and stored in the Page Buff-
er. Valid bus operations are the same as Asyn-
chronous Bus Read operations but with different
timings. The first read operation within the page
has identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. Page Read does not support Latched
Controlled Read.
See Figure 10., Asynchronous Page Read AC
Waveforms, and Table 18., Asynchronous Page
Read AC Characteristics, for details on when the
outputs become valid.
Asynchronous Bus Write. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts, and setting Chip Enable, Write Enable and
Latch Enable Low, VIL, and Output Enable High,
VIH, or Output Disable Low, VIL. The Address In-
puts are latched by the Command Interface on the
rising edge of Chip Enable or Write Enable, which-
ever occurs first. Commands and Input Data are
latched on the rising edge of Chip Enable, E, or
Write Enable, W, whichever occurs first. Output
Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write
operation.
Asynchronous Read is the default read mode
which the device enters on power-up or on return
from Reset/Power-Down.
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells or specific regis-
ters in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, VIL and keeping Write
Enable High, VIH; the address is latched on the ris-
ing edge of Latch Enable. Once latched, the Ad-
dress Inputs can change. Set Output Enable Low,
VIL, to read the data on the Data Inputs/Outputs;
See Figure 11., Asynchronous Write AC Wave-
form, and Asynchronous Write and Latch Con-
trolled Write AC Characteristics, for details of the
timing requirements.
15/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Asynchronous Latch Controlled Bus Write.
Output Disable. The data outputs are high im-
pedance when the Output Enable, G, is at VIH or
Output Disable, GD, is at VIL.
Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
VIL. The Address Inputs are latched by the Com-
mand Interface on the rising edge of Latch Enable,
Write Enable or Chip Enable, whichever occurs
first. Commands and Input Data are latched on the
rising edge of Chip Enable, E, or Write Enable, W,
whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole
Asynchronous Bus Write operation.
Standby. When Chip Enable is High, VIH, and the
Program/Erase Controller is idle, the memory en-
ters Standby mode, the power consumption is re-
duced to the standby level (IDD1) and the Data
Inputs/Outputs pins are placed in the high imped-
ance state regardless of Output Enable, Write En-
able or Output Disable inputs.
The Standby mode can be disabled by setting the
Standby Disable bit (M14) of the Burst Configura-
tion Register to ‘1’ (see Table 15., DC Character-
istics).
Reset/Power-Down. The memory is in Reset/
Power-Down mode when Reset/Power-Down,
RP, is at VIL. The power consumption is reduced
to the standby level (IDD1) and the outputs are high
impedance, independent of the Chip Enable, E,
Output Enable, G, Output Disable, GD, or Write
Enable, W, inputs. In this mode the device is write
protected and both the Status and the Burst Con-
figuration Registers are cleared. A recovery time is
required when the RP input goes High.
See Figure 12., Asynchronous Latch Controlled
Write
AC
Waveform,
and
Table
19., Asynchronous Write and Latch Controlled
Write AC Characteristics, for details of the timing
requirements.
Table 4. Asynchronous Bus Operations
Bus Operation
Step
E
G
GD
W
RP
L
A0-A19
DQ0-DQ31
Data Output
High Z
(2)
V
V
V
V
IH
V
IH
V
Address
Asynchronous Bus Read
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IH
IL
IL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
V
V
Address Latch
Read
Address
IH
IH
IL
Asynchronous Latch
Controlled Bus Read
V
V
V
V
V
IH
X
Data Output
Data Output
Data Input
High Z
IL
IL
IH
IH
IH
IH
V
V
V
IH
Asynchronous Page Read
Asynchronous Bus Write
X
Address
IH
V
V
V
IH
V
X
X
X
Address
IH
IH
IH
IH
IL
IL
IL
V
V
V
V
IH
V
V
Address Latch
Write
Address
IH
Asynchronous Latch
Controlled Bus Write
V
V
IH
X
X
X
X
X
Data Input
High Z
IL
IH
IH
IH
V
V
V
V
IH
Output Disable, G
Output Disable, GD
Standby
X
IH
V
V
V
IH
X
X
X
High Z
IL
IL
V
IH
X
X
X
X
High Z
IH
V
IL
Reset/Power-Down
Note: 1. X = Don’t Care
X
X
X
High Z
2. Data, Manufacturer Code, Device Code, Burst Configuration Register, Standby Status and Block Protection Configuration Register
are read using the Asynchronous Bus Read command.
16/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Synchronous Bus Operations
For synchronous bus operations refer to Table 5
together with the following text.
When Valid Data Ready is Low on the rising clock
edge, no new data is available and the memory
does not increment the internal address counter at
the active clock edge even if Burst Address Ad-
vance, B, is Low.
Valid Data Ready may be configured (by bit M8 of
Burst Configuration Register) to be valid immedi-
ately at the rising clock edge or one data cycle be-
fore the rising clock edge.
Synchronous Burst Read will be suspended if
Burst Address Advance, B, goes High, VIH.
If Output Enable is at VIL and Output Disable is at
VIH, the last data is still valid.
If Output Enable, G, is at VIH or Output Disable,
GD, is at VIL, but the Burst Address Advance, B, is
at VIL the internal Burst Address Counter is incre-
mented at each Burst Clock K rising edge.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 13, 14,
15 and 16, and Table 20.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The valid edge of the Clock signal is
the rising edge. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion. Refer to Figure
5
for examples of
synchronous burst operations.
In continuous burst read, one burst read operation
can access the entire memory sequentially by
keeping the Burst Address Advance B at VIL for
the appropriate number of clock cycles. At the end
of the memory address space the burst read re-
starts from the beginning at address 000000h.
A valid Synchronous Burst Read operation begins
when the Burst Clock is active and Chip Enable
and Latch Enable are Low, VIL. The burst start ad-
dress is latched and loaded into the internal Burst
Address Counter on the valid Burst Clock K edge
or on the rising edge of Latch Enable, whichever
occurs first.
After an initial memory latency time, the memory
outputs data each clock cycle (or two clock cycles
depending on the value of M9). The Burst Address
Advance B input controls the memory burst output.
The second burst output is on the next clock valid
edge after the Burst Address Advance B has been
pulled Low.
Valid Data Ready, R, monitors if the memory burst
boundary is exceeded and the Burst Controller of
the microprocessor needs to insert wait states.
Synchronous Burst Read Suspend. During
a
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
dress Advance are High, VIH. The Burst Address
Advance going High, VIH, stops the burst counter
and the Output Enable going High, VIH, inhibits the
data outputs. The Synchronous Burst Read oper-
ation can be resumed by setting Output Enable
Low.
Table 5. Synchronous Burst Read Bus Operations
A0-A19
DQ0-DQ31
Bus Operation
Step
Address Latch
E
G
GD
RP
K
L
B
(3)
V
V
IH
V
V
X
X
Address Input
IL
IL
IL
IL
IL
IH
IL
IH
IH
IH
IH
R
R
(3)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
Read
Data Output
High Z
IL
IH
IH
V
V
Read Suspend
Read Resume
X
X
IH
IH
IH
Synchronous Burst
(2)
Read
(3)
(3)
V
V
V
V
IL
V
IL
Data Output
IL
IH
IH
R
R
V
IH
V
Burst Address Advance
Read Abort, E
X
X
X
High Z
High Z
High Z
IH
V
X
X
X
X
IH
IH
V
Read Abort, RP
X
X
X
X
X
IL
Note: 1. X = Don't Care, V or V
.
IH
IL
2. M15 = 0, Bit M15 is in the Burst Configuration Register.
3. R= Rising Edge.
17/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Burst Configuration Register
6., Burst Configuration Register and Note 2.for
valid combinations of the Y-Latency, the X-Laten-
cy and the Clock frequency.
The Burst Configuration Register is used to config-
ure the type of bus access that the memory will
perform.
Valid Data Ready Bit (M8). The
Valid
Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. When the Valid Data Ready
bit is ’0’ the Valid Data Ready output pin is driven
Low for the rising clock edge when invalid data is
output on the bus. When the Valid Data Ready bit
is ’1’ the Valid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Wrap Burst Bit (M3). The burst reads can be
confined inside the 4 or 8 Word boundary (wrap) or
overcome the boundary (no wrap). The Wrap
Burst bit is used to select between wrap and no
wrap. When the Wrap Burst bit is set to ‘0’ the
burst read wraps; when it is set to ‘1’ the burst read
does not wrap.
The Burst Configuration Register is set through
the Command Interface and will retain its informa-
tion until it is re-configured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register bits are de-
scribed in Table 6. They specify the selection of
the burst length, burst type, burst X and Y laten-
cies and the Read operation. Refer to Figure 5 for
examples of synchronous burst configurations.
Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
Burst Length Bit (M2-M0). The Burst Length bits
set the maximum number of Double-Words that
can be output during a Synchronous Burst Read
operation before the address wraps. Burst lengths
of 4 or 8 and continuous burst are available.
Table 6., Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Table 7., Burst Type Definition,
gives the sequence of addresses output from a
given starting address for each length.
If either a Continuous or a No Wrap Burst Read
has been initiated the device will output data syn-
chronously. Depending on the starting address,
the device activates the Valid Data Ready output
to indicate that a delay is necessary before the
data is output. If the starting address is aligned to
a 4 Double Word boundary, the continuous burst
mode will run without activating the Valid Data
Ready output. If the starting address is not aligned
to a 4 Double Word boundary, Valid Data Ready is
activated to indicate that the device needs an in-
ternal delay to read the successive words in the ar-
ray.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous accesses.
Standby Disable Bit (M14). The Standby Dis-
able Bit, M14, is used to disable the Standby
mode. When the Standby bit is ‘1’, the device will
not enter Standby mode when Chip Enable goes
High, VIH.
X-Latency Bits (M13-M11). The X-Latency bits
are used during Synchronous Bus Read opera-
tions to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assume the values in Table
6., Burst Configuration Register. The X-Latency
bits should also be selected in accordance with
Note: 1. below Table 6., Burst Configuration Reg-
ister.
Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table
M10, M7 to M4 are reserved for future use.
18/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 6. Burst Configuration Register
Bit
Description
Value
Description
0
1
0
1
Synchronous Burst Read
M15
Read Select
Asynchronous Read (Default at power-up)
Standby Mode Enabled (Default at power-up)
M14
Standby Disable
Standby Mode Disabled
001
010
011
100
101
110
3
4
5
6
7
8
(1)
M13-M11
X-Latency
M10
M9
Reserved
0
1
0
1
One Burst Clock cycle
(2)
Y-Latency
Two Burst Clock cycles
R valid Low during valid Burst Clock edge
R valid Low one data cycle before valid Burst Clock edge
M8
M7-M4
M3
Valid Data Ready
Reserved
0
Wrap
Wrapping
1
No Wrap
001
010
111
4 Double-Words
8 Double-Words
Continuous
M2-M0
Burst Length
Note: 1. X latencies can be calculated as: (t
– t
LLKH
+ t
) + t
< (X -1) t (X is an integer number from 4 to 8 and t
AVQV
KHQV
SYSTEM MARGIN K.
K
is the clock period), where t
is the value given by the master microcontroller timing specifications.
,
LLKH
2. Y latencies can be calculated as: t
+ t
+ t < Y t .
KHQV K
KHQV
SYSTEM MARGIN
3. t
is the time margin required for the calculation.
SYSTEM MARGIN
19/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 7. Burst Type Definition
Starting
Address
x4
x8
M 3
Continuous
Sequential
Sequential
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
–
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
–
0-1-2-3-4-5-6-7-8-9-10..
1-2-3-4-5-6-7-8-9-10-11..
2-3-4-5-6-7-8-9-10-11-12..
3-4-5-6-7-8-9-10-11-12-13..
4-5-6-7-8-9-10-11-2-13-14..
5-6-7-8-9-10-11-12-13-14..
6-7-8-9-10-11-12-13-14-15..
7-8-9-10-11-12-13-14-15-16..
8-9-10-11-12-13-14-15-16-17..
0-1-2-3-4-5-6-7-8-9-10..
–
–
–
–
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
4-5-6-7
5-6-7-8
6-7-8-9
7-8-9-10
8-9-10-11
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11..
2-3-4-5-6-7-8-9-10-11-12..
3-4-5-6-7-8-9-10-11-12-13..
4-5-6-7-8-9-10-11-12-13-14..
5-6-7-8-9-10-11-12-13-14..
6-7-8-9-10-11-12-13-14-15..
7-8-9-10-11-12-13-14-15-16..
8-9-10-11-12-13-14-15-16-17..
20/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 5. Example Burst Configuration X-1-1-1
0
1
2
3
4
5
6
7
8
9
K
ADD
VALID
L
DQ
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
3-1-1-1
DQ
DQ
VALID
VALID
VALID
VALID
VALID
VALID
4-1-1-1
5-1-1-1
VALID
VALID
VALID
VALID
DQ
DQ
DQ
VALID
VALID
VALID
VALID
VALID
6-1-1-1
7-1-1-1
8-1-1-1
VALID
VALID
AI03841b
21/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
8., Commands. Refer to Table 8 in conjunction
with the text descriptions below.
The content of the Status Register may also be
read at the completion of a Program, Erase or
Suspend operation. During a Block Erase, Pro-
gram, Tuning Protection Program or Tuning Pro-
tection Unlock command, DQ7 indicates the
Program/Erase Controller status. It is valid until
the operation is completed or suspended.
Read Memory Array Command
See the section on the Status Register and Table
11 for details on the definitions of the Status Reg-
ister bits.
The Read Memory Array command returns the
memory to Read mode. One Bus Write cycle is re-
quired to issue the Read Memory Array command
and return the memory to Read mode. Subse-
quent read operations will output the addressed
memory array data. Once the command is issued
the memory remains in Read mode until another
command is issued. From Read mode Bus Read
commands will access the memory array.
Clear Status Register Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One Bus Write is required to issue the Clear
Status Register command. Once the command is
issued the memory returns to its previous mode,
subsequent Bus Read operations continue to out-
put the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Pro-
gram, Erase, Block Protect or Block Unprotect
command is issued. If any error occurs then it is
essential to clear any error bits in the Status Reg-
ister by issuing the Clear Status Register com-
mand before attempting a new Program, Erase or
Resume command.
Read Electronic Signature Command
The Read Electronic Signature command is used
to read the Manufacturer Code, the Device Code,
the Block Protection Configuration Register and
the Burst Configuration Register. One Bus Write
cycle is required to issue the Read Electronic Sig-
nature command. Once the command is issued,
subsequent Bus Read operations, depending on
the address specified, read the Manufacturer
Code, the Device Code, the Block Protection Con-
figuration or the Burst Configuration Register until
another command is issued; see Table 9., Read
Electronic Signature.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ‘1’. All
previous data in the block is lost. If the block is pro-
tected then the Erase operation will abort, the data
in the block will not be changed and the Status
Register will output the error.
Two Bus Write operations are required to issue the
command; the first write cycle sets up the Block
Erase command, the second write cycle confirms
the Block erase command and latches the block
address in the internal state machine and starts
the Program/Erase Controller. The sequence is
aborted if the Confirm command is not given and
the device will output the Status Register Data with
bits 4 and 5 set to '1'.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Erase operation the memory will only accept the
Read Status Register command and the Program/
Erase Suspend command. All other commands
will be ignored.
The command can be executed using VDD. If VPEN
is at VIH, the operation can be performed. If VPEN
goes below VIH, the operation aborts, the VPEN
Status bit in the Status Register is set to ‘1’ and the
command must be re-issued.
Read Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area. One Bus Write cycle is required to issue the
Read Query Command. Once the command is is-
sued subsequent Bus Read operations, depend-
ing on the address specified, read from the
Common Flash Interface Memory Area.
Read Status Register Command
The Read Status Register command is used to
read the Status Register. One Bus Write cycle is
required to issue the Read Status Register com-
mand. Once the command is issued subsequent
Bus Read operations read the Status Register un-
til another command is issued.
The Status Register information is present on the
output data bus (DQ0-DQ7) when Chip Enable E
and Output Enable G are at VIL and Output Dis-
able is at VIH.
An interactive update of the Status Register bits is
possible by toggling Output Enable or Output Dis-
able. It is also possible during a Program or Erase
operation, by disactivating the device with Chip
Enable at VIH and then reactivating it with Chip En-
able and Output Enable at VIL and Output Disable
at VIH.
22/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Typical Erase times are given in Table 10.
gram/Erase Suspend command. All other com-
mands will be ignored.
If Reset/Power-down, RP, falls to VIL during pro-
gramming the operation will be aborted.
See Appendix A, Figure 22., Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Erase All Main Blocks Command
The command can be executed using VDD. If VPEN
is at VIH, the operation can be performed. If VPEN
goes below VIH, the operation aborts, the VPEN
Status bit in the Status Register is set to ‘1’ and the
command must be re-issued.
See Appendix A, Figure 20., Program Flowchart
and Pseudo Code, for a suggested flowchart on
using the Program command.
The Erase All Main Blocks command is used to
erase all 63 Main Blocks, without affecting the Pa-
rameter Blocks.
Issuing the Erase All Main Blocks command sets
every bit in each Main Block to '1'. All data previ-
ously stored in the Main Blocks are lost.
Two Bus Write cycles are required to issue the
Erase All Main Blocks command. The first cycle
sets up the command, the second cycle confirms
the command and starts the Program/Erase Con-
troller. If the Confirm Command is not given the
sequence is aborted, and Status Register bits 4
and 5 are set to '1'.
If the address given in the second cycle is located
in a protected block, the Erase All Main Blocks op-
eration aborts. The data remains unchanged in all
blocks and the Status Register outputs the error.
Once the Erase All Main Blocks command has
been issued, subsequent Bus Read operations
output the Status Register. See the STATUS
REGISTER section for details.
During an Erase All Main Blocks operation, only
the Read Status Register command is accepted
by the memory; any other command are ignored.
Erase All Main Blocks, once started, cannot be
suspended.
The Erase All Main Blocks command can be exe-
cuted using VDD. If VPEN is at VIH, the operation
will be performed. If VPEN is lower than VIH the op-
eration aborts and the Status Register VPEN bit (bit
3) is set to '1'.
Write to Buffer and Program Command
The Write to Buffer and Program Command
makes use of the device’s double Word (32 bit)
Write Buffer to speed up programming.
Up to eight Double Words can be loaded into the
Write Buffer and programmed into the memory.
Four successive steps are required to issue the-
command.
1. One Bus Write operation is required to set up
the Write to Buffer and Program Command.
Any Bus Read operations will start to output
the Status Register after the 1st cycle.
2. Use one Bus Write operation to write the
selected memory Block Address (any address
in the block where the values will be
programmed can be used) along with the
value N on the Data Inputs/Outputs, where
N+1 is the number of Words to be
programmed. The maximum value of N+1 is 8
Words.
3. Use N+1 Bus Write operations to load the
address and data for each Word into the Write
Buffer. The address must be between Start
Address and Start Address plus N, where
Start Address is the first word address.
Program Command
The Program command is used to program the
memory array. Two Bus Write operations are re-
quired to issue the command; the first write cycle
sets up the Program command, the second write
cycle latches the address and data to be pro-
grammed and starts the Program/Erase Control-
ler. A program operation can be aborted by writing
FFFFFFFFh to any address after the program set-
up command has been given.
The Program command is also used to program
the OTP block. Refer to Table 8., Commands, for
details of the address.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits. During the
Program operation the memory will only accept
the Read Status Register command and the Pro-
4. Finally, use one Bus Write operation to issue
the final cycle to confirm the command and
start the Program operation.
If any address is outside the block boundaries or if
the correct sequence is not followed, Status Reg-
ister bits 4 and 5 are set to ‘1’ and the operation will
abort without affecting the data in the memory ar-
ray. A protected block must be unprotected using
the Blocks Unprotect command.
During a Write to Buffer and Program operation
the memory will only accept the Read Status Reg-
ister and the Program/Erase Suspend commands.
All other commands are ignored. The Write to
Buffer and Program command can be executed
using VDD. If VPEN is at VIH, the operation will be
performed. If VPEN is lower than VIH the operation
aborts and the Status Register VPEN bit (bit 3) is
set to '1'.
23/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
The Status Register should be cleared before re-
issuing the command.
Program/Erase Suspend Command
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command.
See Appendix A, Figure 21., Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
23., Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
The Program/Erase Suspend command is used to
pause a Program or Erase operation. The com-
mand will only be accepted during a Program or
Erase operation. It can be issued at any time dur-
ing a program or erase operation. The command
is ignored if the device is already in suspend
mode.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 10.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Program, the Write
to Buffer and Program, the Set/Clear Block Protec-
tion Configuration Register and the Program Sus-
pend commands will also be accepted. When a
program operation is completed inside a Block
Erase Suspend the Read Memory Array command
must be issued to reset the device in Read mode,
then the Erase Resume command can be issued
to complete the whole sequence. Only the blocks
not being erased may be read or programmed cor-
rectly.
Set Burst Configuration Register Command.
The Set Burst Configuration Register command is
used to write a new value to the Burst Configura-
tion Register which defines the burst length, type,
X and Y latencies, Synchronous/Asynchronous
Read mode.
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. The first
cycle writes the setup command. The second cy-
cle writes the address where the new Burst Con-
figuration Register content is to be written, and
confirms the command. If the command is not con-
firmed, the sequence is aborted and the device
outputs the Status Register with bits 4 and 5 set to
‘1’. Once the command is issued the memory re-
turns to Read mode as if a Read Memory Array
command had been issued.
The value for the Burst Configuration Register is
always presented on A0-A15. M0 is on A0, M1 on
A1, etc.; the other address bits are ignored.
Tuning Protection Unlock Command
The Tuning Protection Unlock command unlocks
the tuning protected blocks by writing the 64bit
Tuning Protection Code (M58BW032B only). After
a reset or power-up the blocks are locked and so
a Tuning Protection Unlock command must be is-
sued to allow program or erase operations on tun-
ing protected block or to program a new Tuning
Protection Code. Read operations output the Sta-
tus Register content after the unlock operation has
started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to unlock the device.
■
The first write cycle issues the Tuning
Protection Unlock Setup command (78h).
■
The second write cycle inputs the first 32 bits
of the tuning protection code on the data bus,
at address 00000h.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal reg-
ister. If b7 = ‘1’, the device is ready to accept the
second part of the code. This does not mean that
the first 32 bits match the tuning protection code,
simply that it was correctly stored for the compar-
ing. If b7 = ‘0’, the user must wait for this bit setting
(refer to write cycle AC timings).
See Appendix A, Figure 21., Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
23., Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
24/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
■
■
The third write cycle re-issues the Tuning
second part of the code. If b7 = ‘0’, the user must
wait for this bit setting (refer to write cycle AC tim-
ings).
Protection Unlock Setup command (78h).
The fourth write cycle inputs the second 32
bits of the code at address 00001h.
■
The third write cycle re-issues the Tuning
Protection Program Setup command (48h).
Bit 7 of the Status Register should again be
checked to verify that the device has successfully
stored the second part of the code. When the de-
vice is ready (b7 = ‘1’), the tuning protection status
can be monitored on Status Register bit0. If b0 =
‘0’ the device is locked; b0 = ‘1’ the device is un-
locked. If the device is still locked a Read Memory
Array command must be issued before re-issuing
the Tuning Protection Unlock command.
■
The fourth write cycle inputs the second 32
bits of the new code at address 00001h.
Bit 7 of the Status Register should again be
checked to verify that the device has successfully
stored the second part of the code. When the de-
vice is ready (b7 = ‘1’). After completion Status
Register bit 4 is set to '1' if there has been a pro-
gram failure.
Device locked means that the 64 bit password is
wrong. If the unlock operation is attempted using a
wrong code on an already unlocked device, the
device becomes locked. Status register bit 4 is set
to '1' if there has been a verify failure.
Tuning Protection Unlock command aborts if VPEN
drops below VIH or RP goes to VIL.
Programming aborts if VPEN drops below VIH or
RP goes to VIL.
A Read Memory Array command must be issued
to return the memory to read mode before issuing
any other commands. Once the code has been
changed a device reset or power-down will make
the protection active with the new code.
Once the device is successfully unlocked, a Read
Memory Array command must be issued to return
the memory to read mode before issuing any other
commands. The user can then program or erase
all blocks, depending on WP and VPEN status and
on the protection status of each block. At this
point, it is also possible to configure a new protec-
tion code. To write a new protection code into the
device tuning register, the user must perform the
Tuning Protection Program sequence. The device
can be re-locked with a reset or power-down.
See Appendix A, Figure 24, 25 and 26 for suggest-
ed flowcharts for using the Tuning Protection Pro-
gram command.
Set Block Protection Configuration Register
Command
The Set Block Protection Configuration Register
command is used to configure the Block Protec-
tion Configuration Register to ‘Protected’, for a
specific block. Protected blocks are fully protected
from program or erase when WP pin is Low, VIL.
The status of a protected block can be changed to
‘Unprotected’ by using the Clear Block Protection
Configuration Register command. At power-up, all
block are configured as ‘Protected’.
See Appendix A, Figure 24, 25 and 26 for suggest-
ed flowcharts for using the Tuning Protection Un-
lock command.
Tuning Protection Program Command.
Two bus operations are required to issue a Set
Block Protection Configuration Register com-
mand:
The Tuning Protection Program command is used
to program a new Tuning Protection Code which
can be configured by the designer of the applica-
tion (M58BW032B only). The device should be un-
locked by the Tuning Protection Unlock command
before issuing the Tuning Protection Program
command.
Read operations output the Status Register con-
tent after the program operation has started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to program the code.
■
The first cycle writes the setup command
■
The second write cycle specifies the address
of the block to protect and confirms the
command. If the command is not confirmed,
the sequence is aborted and the device
outputs the Status Register with bits 4 and 5
set to ‘1’.
To protect multiple blocks, the Set Block Protec-
tion Configuration Register command must be re-
peated for each block.
Any attempt to re-protect a block already protected
does not change its status.
Clear Block Protection Configuration Register
Command.
The Clear Block Protection Configuration Register
command is used to configure the Block Protec-
tion Configuration Register to ‘Unprotected’, for a
■
The first write cycle issues the Tuning
Protection Program Setup command (48h).
■
The second write cycle inputs the first 32 bits
of the new tuning protection code on the data
bus, at address 00000h.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal reg-
ister. If b7 = ‘1’, the device is ready to accept the
25/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
specific block thus allowing program/erase opera-
tions to this block, regardless of the WP pin status.
Two bus operations are required to issue a Clear
Block Protection Configuration Register com-
mand:
the sequence is aborted and the device
outputs the Status Register with bits 4 and 5
set to ‘1’.
To unprotect multiple blocks, the Clear Block Pro-
tection Configuration Register command must be
repeated for each block.
■
The first cycle writes the setup command
Any attempt to unprotect a block already unpro-
tected does not affect its status.
■
The second write cycle specifies the address
of the block to unprotect and confirms the
command. If the command is not confirmed,
Table 8. Commands
Command
Bus Operations
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data
Read Memory Array
≥ 2 Write
≥ 2 Write
X
X
FFh Read RA
RD
(2)
(1)
(1)
90h Read
70h
Read Electronic Signature
Read Status Register
Read Query
IDA
IDD
1
Write
X
X
X
≥ 2 Write
98h Read RA
50h
RD
Clear Status Register
Block Erase
1
2
2
Write
Write 55h 20h Write BA
D0h
Erase All Main Blocks
Write 55h 80h Write AAh D0h
40h
any block
Program
2
2
Write AAh
Write PA
PD
10h
Write AAh 40h Write PA
OTP Block
PD
N
Write to Buffer and Program
Program/Erase Suspend
Program/Erase Resume
N+4 Write AAh E8h Write BA
Write PA PD Write
X
D0h
1
1
Write
Write
X
X
B0h
D0h
Set Burst Configuration
Register
≥3 Write
X
60h Write BCRh 03h Read RA RD
(3)
4
4
Write AAh 48h Write TPAh TPCh Write AAh 48h Write TPAh TPCh
Tuning Protection Program
(3)
Write
Write
X
X
78h Write TPAh TPCh Write
X
78h Write TPAh TPCh
Tuning Protection Unlock
Set Block Protection
Configuration Register
2
2
60h Write BA
60h Write BA
01h
D0h
Clear Block Protection
Configuration Register
Write
X
Note: 1. X Don’t Care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status Register
Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Con-
figuration Register value, TPA = Tuning Protection Address, TPC = Tuning Protection Code, N+1 number of Words to program, BA
Block address.
2. The Manufacturer Code, the Device Code, the Burst Configuration Register, and the Block Protection Configuration Register of
each block are read using the Read Electronic Signature command.
3. Cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code.
26/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 9. Read Electronic Signature
Code
Device
A19-A0
00000h
00001h
DQ31-DQ0
00000020h
00008838h
Manufacturer
All
(1)
(1)
M58BW032xT
M58BW032xB
Device
00001h
00005h
00008837h
Burst Configuration
Register
(2)
BCR
00000000h (Unprotected)
00000001h (Protected)
Block Protection
Configuration Register
(3)
All
SBA+02h
Note: 1. x= B or D version of the device.
2. BCR= Burst Configuration Register.
3. SBA is the start address of each block.
Table 10. Program, Erase Times and Program Erase Endurance Cycles
M58BW032B/D
Parameters
Unit
Min
Typ
Max
20
Full Chip Program
15
s
µs
s
Double Word Program
TBD
1
TBD
2
512 Kbit Block Erase
256 Kbit Block Erase
0.8
0.6
3
1.6
s
64 Kbit Block Erase
1.2
s
Program Suspend Latency Time
Erase Suspend Latency Time
Program/Erase Cycles (per Block)
10
µs
µs
cycles
10
30
100,000
Note: T = –40 to 125°C, V = 3.0V to 3.6V, V
= 1.6V to V
DD
A
DD
DDQ
27/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Tuning Protection operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Program/Erase Resume commands. The
Status Register can be read from any address.
The contents of the Status Register can be updat-
ed during an erase or program operation by tog-
gling the Output Enable or Output Disable pins or
by dis-activating (Chip Enable, VIH) and then reac-
tivating (Chip Enable and Output Enable, VIL, and
Output Disable, VIH.) the device.
The Status Register bits are summarized in Table
11., Status Register Bits. Refer to Table 11 in con-
junction with the following text descriptions.
and the memory is waiting for a Program/Erase
Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5)
The Erase Status bit can be used to identify if the
memory has failed to verify that the block has
erased correctly. The Erase Status bit should be
read once the Program/Erase Controller Status bit
is High (Program/Erase Controller inactive).
When the Erase Status bit is set to ‘0’, the memory
has successfully verified that the block has erased
correctly. When the Erase Status bit is set to ‘1’,
the Program/Erase Controller has applied the
maximum number of pulses to the block and still
failed to verify that the block has erased correctly.
Once set to ‘1’, the Erase Status bit can only be re-
set to ‘0’ by a Clear Status Register command or a
hardware reset. If set to ‘1’ it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program/ Write to Buffer and Program/Tuning
Protection Unlock Status (Bit 4)
The Program/Write to Buffer and Program/Tuning
Protection Unlock Status bit is used to identify a
Program failure, a Write to Buffer and Program
failure or a Tuning Protection Code verify failure.
Bit4 should be read once the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
inactive).
When bit4 is set to ‘0’ the memory has successful-
ly verified that the device has programmed cor-
rectly or that the correct Tuning Protection Code
has been written. When bit4 is set to ‘1’ the device
has failed to verify that the data has been pro-
grammed correctly or that the correct Tuning Pro-
tection code has been written.
Program/Erase Controller Status (Bit 7)
The Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Sta-
tus bit is set to ‘0’, the Program/Erase Controller is
active; when bit7 is set to ‘1’, the Program/Erase
Controller is inactive.
The Program/Erase Controller Status is set to ‘0’
immediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is set to ‘1’.
During Program and Erase operations the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is set to ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status (bit5), Program/Tuning
Protection Unlock status (bit4) bits should be test-
ed for errors.
Once set to 1’, the Program Status bit can only be
reset to ‘0’ by a Clear Status Register command or
a hardware reset. If set to ‘1’ it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Erase Suspend Status (Bit 6)
The Erase Suspend Status bit indicates that an
Erase operation has been suspended and is wait-
ing to be resumed. The Erase Suspend Status
should only be considered valid when the Pro-
gram/Erase Controller Status bit is set to ‘1’ (Pro-
gram/Erase Controller inactive); after a Program/
Erase Suspend command is issued the memory
may still complete the operation rather than enter-
ing the Suspend mode.
When the Erase Suspend Status bit is set to ‘0’,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is set to ‘1’, a Pro-
gram/Erase Suspend command has been issued
VPEN Status (Bit 3). The VPEN Status bit can be
used to identify if a program or erase operation
has been attempted when VPEN is Low, VIL.
When Bit 3 is set to ‘0’ no program or erase oper-
ations have been attempted with VPEN Low, VIL,
since the last Clear Status Register command, or
hardware reset.
When Bit 3 is set to ‘1’ a program or erase opera-
tion has been attempted with VPEN Low, VIL.
Once set to ‘1’, Bit 3 can only be reset by an Clear
Status Register command or a hardware reset. If
set to ‘1’ it should be reset before a new program
28/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
or erase command is issued, otherwise the new
When the Block Protection Status bit is set to ‘0’,
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
when the Block Protection Status bit is set to ‘1’, a
Program or Erase operation has been attempted
on a protected block.
Once set to ‘1’, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set to ‘1’ it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
command will appear to fail.
Program Suspend Status (Bit 2)
The Program Suspend Status bit indicates that a
Program operation has been suspended and is
waiting to be resumed. The Program Suspend
Status should only be considered valid when the
Program/Erase Controller Status bit is set to ‘1’
(Program/Erase Controller inactive); after a Pro-
gram/Erase Suspend command is issued the
memory may still complete the operation rather
than entering the Suspend mode.
When the Program Suspend Status bit is set to ‘0’,
the Program/Erase Controller is active or has com-
pleted its operation; when the bit is set to ‘1’, a Pro-
gram/Erase Suspend command has been issued
and the memory is waiting for a Program/Erase
Resume command.
Tuning Protection Status (Bit 0)
The Tuning Protection Status bit indicates if the
device is locked (Tuning Protection is enabled) or
unlocked (Tuning Protection is disabled).
When the Tuning Protection Status bit is set to ‘0’
the device is locked, when it is set to ‘1’ the device
is unlocked. After a reset or power-up the device is
locked and so bit0 is set to ‘0’.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1)
The Tuning Protection Status bit is set to ‘1’ for the
M58BW032D version.
The Block Protection Status bit can be used to
identify if a Program or Erase operation has tried
to modify the contents of a protected block.
Table 11. Status Register Bits
Bit
Name
Logic Level
Definition
7
’1’
’0’
’1’
’0’
’1’
’0’
’1’
’0’
‘0’
‘1’
’1’
’0’
Ready
Program/Erase Controller Status
Busy
6
5
4
3
2
1
Suspended
Erase Suspend Status
Erase Status
In Progress or Completed
Erase Error
Erase Success
Program Error
Program Status,
Tuning Protection Unlock Status
Program Success
no program or erase attempted
program or erase attempted
Suspended
V
Status bit
PEN
Program Suspend Status
In Progress or Completed
program/erase on protected block,
abort
’1’
Erase/Program in a Protected
Block
’0’
’1’
’0’
No operations to protected blocks
(1)
0
Tuning Protection Disabled
Tuning Protection Status
Tuning Protection Enabled
Note: 1. For the M58BW032D version the Tuning Protection Status bit is always set to ‘1’.
29/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
MAXIMUM RATING
Stressing the device above the ratings listed in Ta-
ble 12., Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 12. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–40
–55
Max
125
155
TBD
T
Temperature Under Bias
°C
°C
°C
BIAS
T
Storage Temperature
STG
(1)
T
LEAD
Lead Temperature during Soldering
V
+0.6
+0.6
DDQ
V
Input or Output Voltage
Supply Voltage
–0.6
–0.6
V
V
IO
V
DDQIN
V
, V
V
DDQ, DDQIN
4.2
DD
Note: 1. Compliant with the ECOPACK® 7191395 specification for Lead-free soldering processes.
30/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment
Conditions
summarized
in
Table
13., Operating and AC Measurement Conditions.
Designers should check that the operating condi-
tions in their circuit match the measurement condi-
tions when relying on the quoted parameters.
Table 13. Operating and AC Measurement Conditions
Parameter
Value
Units
Min
3.0
Max
3.6
3.6
90
Supply Voltage (V
)
V
V
DD
Input/Output Supply Voltage (V
)
2.4
DDQ
Grade 6
Grade 3
–40
–40
°C
°C
pF
ns
ns
V
Ambient Temperature (T )
A
125
Load Capacitance (C )
30
L
Clock Rise and Fall Times
Input Rise and Fall Times
Input Pulses Voltages
3
3
0 to V
DDQ
V
DDQ
/2
Input and Output Timing Ref. Voltages
V
Figure 6. AC Measurement Input Output
Waveform
Figure 7. AC Measurement Load Circuit
DEVICE
UNDER
TEST
V
DDQ
OUT
V
DDQIN
V
/2
/2
DDQ
V
C
L
DDQIN
0V
AI04153
C
includes JIG capacitance
L
AI04154b
Note: V = V
.
DD
DDQ
Table 14. Device Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Typ
6
Max
8
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
V
OUT
8
12
pF
OUT
Note: 1. T = 25°C, f = 1 MHz
A
2. Sampled only, not 100% tested.
31/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 15. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
I
0V≤ V ≤ V
LI
IN
DDQ
I
LO
0V≤ V
≤V
±5
µA
OUT DDQ
(1)
E = V , G = V , f = 6MHz
IH add
Supply Current (Random Read)
Supply Current (Burst Read)
50
50
mA
mA
I
IL
DD
E = V , G = V , f
=
IL
IH clock
(1)
I
DDB
75MHz
(1)
(1)
E = RP = V ± 0.2V
Supply Current (Standby)
100
30
µA
I
DD
DD1
Supply Current (Program or Erase)
Program, Erase in progress
mA
I
I
DD2
Supply Current
(Erase/Program Suspend)
(1)
E = V
40
µA
IH
DD3
V
0.2V
DDQIN
Input Low Voltage
–0.5
V
V
IL
V
V
V
0.8V
V +0.3
DDQ
Input High Voltage (for DQ lines)
IH
DDQIN
DDQIN
Input High Voltage (for Input only
lines)
0.8V
3.6
V
IH
I
= 100µA
Output Low Voltage
0.1
V
V
OL
OL
V
OH
I
= –100µA
V
–0.1
Output High Voltage CMOS
OH
DDQ
V
Supply Voltage (Erase and
DD
V
2.2
V
LKO
Program lockout)
Note: 1. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to ‘1’.
32/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 8. Asynchronous Bus Read AC Waveforms
tAVAV
VALID
A0-A19
tAVQV
tLLEL
tEHLX
L
tELQX
tELQV
tAXQX
E
tGLQX
tGLQV
tEHQX
tEHQZ
G
GD
tGHQX
tGHQZ
DQ0-DQ31
OUTPUT
See also Page Read
AI08921
Table 16. Asynchronous Bus Read AC Characteristics.
M58BW032
Symbol
Parameter
Test Condition
Unit
45
45
45
0
55
55
55
60
60
60
t
E = V , G = V
IL
Address Valid to Address Valid
Min
Max
Min
Min
Min
Max
ns
ns
ns
ns
ns
ns
AVAV
IL
IL
IL
t
E = V , G = V
Address Valid to Output Valid
AVQV
IL
t
E = V , G = V
Address Transition to Output Transition
Chip Enable High to Latch Enable Transition
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
AXQX
IL
t
0
EHLX
t
G = V
0
EHQX
IL
t
G = V
20
EHQZ
IL
(1)
G = V
Chip Enable Low to Output Valid
Max
Min
Min
Max
Max
Min
Min
45
0
55
60
ns
ns
ns
ns
ns
ns
ns
t
IL
ELQV
t
G = V
Chip Enable Low to Output Transition
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable to Output Transition
Latch Enable Low to Chip Enable Low
ELQX
IL
t
E = V
0
GHQX
IL
t
E = V
15
15
0
GHQZ
IL
t
E = V
GLQV
IL
t
E = V
GLQX
IL
t
0
LLEL
Note: 1. Output Enable G may be delayed up to t
- t
after the falling edge of Chip Enable E without increasing t
.
ELQV GLQV
ELQV
33/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms
A0-A19
VALID
tAVLL
tLHAX
L
tLHLL
tLLLH
tELLL
tEHLX
E
tEHQX
tEHQZ
tGLQX
tGLQV
G
tLLQX
tLLQV
tGHQX
GHQZ
DQ0-DQ31
OUTPUT
See also Page Read
AI08922
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
E = V
Unit
45
0
55
0
60
0
t
Address Valid to Latch Enable Low
Chip Enable High to Latch Enable Transition
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
Min
Min
Min
Max
Min
Min
Max
Max
Min
Min
Min
Min
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
IL
t
0
0
0
EHLX
t
G = V
G = V
0
0
0
EHQX
IL
IL
t
20
0
20
0
20
0
EHQZ
t
Chip Enable Low to Latch Enable Low
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Latch Enable High to Address Transition
Latch Enable High to Latch Enable Low
Latch Enable Low to Latch Enable High
Latch Enable Low to Output Valid
ELLL
t
E = V
0
0
0
GHQX
IL
IL
IL
IL
IL
t
E = V
E = V
E = V
E = V
15
15
0
15
25
0
15
25
0
GHQZ
t
GLQV
t
GLQX
t
5
5
5
LHAX
t
10
10
45
0
10
10
55
0
10
10
60
0
LHLL
t
E = V
LLLH
IL
t
E = V , G = V
LLQV
IL
IL
IL
t
E = V , G = V
Latch Enable Low to Output Transition
LLQX
IL
34/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 10. Asynchronous Page Read AC Waveforms
A0-A1
A0 and/or A1
tAVQV1
tAXQX
OUTPUT + 1
OUTPUT
DQ0-DQ31
AI03646
Table 18. Asynchronous Page Read AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
Unit
45
25
6
55
25
6
60
t
E = V , G = V
IL
Address Valid to Output Valid
Max
Min
25
6
ns
ns
AVQV1
IL
t
E = V , G = V
IL
Address Transition to Output Transition
AXQX
IL
Note: For other timings see Table 16., Asynchronous Bus Read AC Characteristics..
35/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 11. Asynchronous Write AC Waveform
36/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 12. Asynchronous Latch Controlled Write AC Waveform
37/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
Min
Unit
45
0
55
0
60
0
t
Address Valid to Latch Enable Low
Address Valid to Write Enable High
Data Input Valid to Write Enable High
Chip Enable Low to Latch Enable Low
Chip Enable Low to Write Enable Low
Latch Enable High to Address Transition
Latch Enable Low to Latch Enable High
latch Enable Low to Write Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
t
E = V
E = V
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
25
25
0
25
25
0
25
25
0
AVWH
IL
IL
t
DVWH
t
ELLL
t
0
0
0
ELWL
t
5
5
5
LHAX
t
10
25
0
10
25
0
10
25
0
LLLH
t
E = V
LLWH
IL
t
Output Valid to V
Low
PEN
QVVPL
t
V
PEN
High to Write Enable High
0
0
0
VPHWH
t
E = V
E = V
Write Enable High to Address Transition
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Write Enable High to Output Valid
0
0
0
WHAX
IL
IL
t
0
0
0
WHDX
t
0
0
0
WHEH
t
150
175
20
25
0
150
175
20
25
0
150
175
20
25
0
WHGL
t
WHQV
t
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Output Valid to Reset/Power-down Low
WHWL
t
E = V
WLWH
IL
t
QVPL
38/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 13. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)
39/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 20. Synchronous Burst Read AC Characteristics
M58BW032
Symbol
Parameter
Test Condition
Unit
45
55
60
t
E = V
Address Valid to Latch Enable Low
Min
Min
0
0
0
ns
ns
AVLL
IL
E = V , G = V ,
Burst Address Advance High to Valid Clock
Edge
IL
IL
t
8
8
8
8
8
8
BHKH
L = V
IH
E = V , G = V ,
Burst Address Advance Low to Valid Clock
Edge
IL
IL
t
Min
ns
BLKH
L = V
IH
t
Chip Enable Low to Latch Enable low
Output Enable Low to Output Valid
Min
Min
Min
Min
Min
0
10
5
0
10
5
0
10
5
ns
ns
ns
ns
ns
ELLL
t
E = V , L = V
GLQV
IL
IH
t
E = V
Valid Clock Edge to Address Transition
Valid Clock Edge to Latch Enable Low
Valid Clock Edge to Latch Enable Transition
KHAX
IL
t
E = V
0
0
0
KHLL
IL
t
E = V
0
0
0
KHLX
IL
E = V , G = V ,
IL
IL
t
Valid Clock Edge to Output Transition
Latch Enable Low to Valid Clock Edge
Valid Data Ready Low to Valid Clock Edge
Min
Min
Min
0
6
6
0
6
6
0
6
6
ns
ns
ns
KHQX
L = V
IH
t
E = V
IL
LLKH
E = V , G = V ,
IL
IL
t
RLKH
L = V
IH
E = V , G = V ,
IL
IL
t
Valid Clock Edge to Output Valid
Max
8
8
8
ns
KHQV
L = V
IH
Note: 1. Data output should be read on the valid clock edge.
2. For other timings see Table 16., Asynchronous Bus Read AC Characteristics..
Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge)
n
n+1
n+2
n+3
n+4
n+5
K
tKHQV
DQ0-DQ31
Q0
Q1
Q2
Q3
Q4
Q5
tKHQX
SETUP
Burst Read
Q0 to Q3
Note: n depends on Burst X-Latency
AI04408c
Note: For set up signals and timings see Synchronous Burst Read.
40/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 15. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
(1)
Output
V
V
V
V
V
tRLKH
R
(2)
AI03649b
Note: Valid Data Ready = Valid Low during valid clock edge
1. V= Valid output.
2. The internal timing of R follows DQ.
Figure 16. Synchronous Burst Read - Burst Address Advance
K
VALID
A0-A19
L
DQ0-DQ31
G
Q0
Q1
Q2
tGLQV
tBLKH
tBHKH
B
AI03650
41/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 17. Reset, Power-Down and Power-up AC Waveform
W, E, G
tPHWL
tPHEL
tPHGL
tPLRH
R
tPHWL
tPHEL
tPHGL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI03849b
Table 21. Reset, Power-Down and Power-up AC Characteristics
Symbol
Parameter
Min
Max
Unit
t
Reset/Power-down High to Chip Enable Low
50
ns
PHEL
(1)
Reset/Power-down High to Output Valid
130
ns
ns
ns
ns
µs
µs
t
PHQV
t
Reset/Power-down High to Write Enable Low
Reset/Power-down High to Output Enable Low
Reset/Power-down Low to Reset/Power-down High
Reset/Power-down Low to Valid Data Ready High
Supply Voltages High to Reset/Power-down High
50
50
100
2
PHWL
t
PHGL
t
PLPH
PLRH
t
30
t
10
VDHPH
Note: 1. This time is t
+ t
or t
+ t
ELQV
.
PHEL
AVQV
PHEL
42/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PACKAGE MECHANICAL
Figure 18. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1 BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z05
Note: Drawing is not to scale.
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.700
0.450
Typ
Max
A
A1
A2
b
0.0669
0.0177
0.400
1.100
0.500
10.000
7.000
0.350
0.0157
0.0433
0.0197
0.3937
0.2756
0.0138
–
–
–
–
–
–
–
–
D
–
–
D1
ddd
E
–
–
0.150
0.0059
12.000
9.000
1.000
1.500
1.500
0.500
0.500
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.4724
0.3543
0.0394
0.0591
0.0591
0.0197
0.0197
–
–
–
–
–
–
–
–
–
–
–
–
–
–
E1
e
FD
FE
SD
SE
43/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
Ne
A2
N
1
e
b
Nd
D2 D1
D
E2
E1
E
A
c
CP
L1
A1
α
L
QFP-B
Note: Drawing is not to scale.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data
millimeters
Min
inches
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
3.400
0.1339
0.250
2.550
0.300
0.130
22.950
19.900
–
0.0098
0.1004
0.0118
0.0051
0.9035
0.7835
–
2.800
3.050
0.450
0.230
23.450
20.100
–
0.1102
0.1201
0.0177
0.0091
0.9232
0.7913
–
c
D
23.200
20.000
18.400
0.800
0.9134
0.7874
0.7244
0.0315
0.6772
0.5512
0.4724
0.0315
0.0630
D1
D2
e
–
–
–
–
E
17.200
14.000
12.000
0.800
16.950
13.900
–
17.450
14.100
–
0.6673
0.5472
–
0.6870
0.5551
–
E1
E2
L
0.650
–
0.950
–
0.0256
–
0.0374
–
L1
α
1.600
0°
7°
0°
7°
N
80
80
Nd
Ne
24
24
16
16
44/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PART NUMBERING
Table 24. Ordering Information Scheme
Example:
M58BW032B
T
45
T
3
T
Device Type
M58
Architecture
B = Burst Mode
Operating Voltage
W = V = 3.0V to 3.6V; V
= V
=1.6 to V
DDQIN DD
DD
DDQ
Device Function
032B = 32 Mbit (x32), Boot Block, Burst Tuning Protection
032D = 32 Mbit (x32), Boot Block, Burst no Tuning Protection
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45ns
55 = 55ns
60 = 60ns
Package
T = PQFP80
ZA = LBGA80: 1.0mm pitch
Temperature Range
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
45/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
APPENDIX A. FLOW CHARTS
Figure 20. Program Flowchart and Pseudo Code
Start
Program Command:
– write 40h, Address AAh
– write Address & Data
Write 40h
(memory enters read status
state after the Program command)
Write Address
& Data
Read Status
Register
do:
– read status register
(E or G must be toggled)
NO
NO
NO
NO
b7 = 1
YES
while b7 = 1
V
Invalid
Error (1)
If b3 = 1, V invalid error:
PEN
– error handler
PEN
b3 = 0
YES
Program
Error (1)
If b4 = 1, Program error:
– error handler
b4 = 0
YES
Program to Protect
Block Error
If b1 = 1, Program to Protected Block Error:
– error handler
b1 = 0
YES
End
AI03850d
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
46/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
Write 70h
– write 70h
do:
Read Status
Register
– read status register
NO
NO
b7 = 1
YES
while b7 = 1
If b2 = 0, Program completed
b2 = 1
YES
Program Complete
Read Memory Array Command:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
Program Erase Resume Command:
– write D0h
to resume programming
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
Write D0h
Write FFh
Read Data
Program Continues
AI00612b
47/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 22. Block Erase Flowchart and Pseudo Code
Start
Erase Command:
– write 20h, Address 55h
– write Block Address
Write 20h
(A11-A19) & D0h
(memory enters read status
state after the Erase command)
Write Block Address
& D0h
NO
do:
Read Status
Register
– read status register
(E or G must be toggled)
if Erase command given execute
suspend erase loop
Suspend
YES
NO
Suspend
Loop
b7 = 1
while b7 = 1
YES
NO
YES
NO
NO
V
Invalid
Error (1)
If b3 = 1, V invalid error:
PEN
PEN
b3 = 0
YES
– error handler
Command
Sequence Error
If b4, b5 = 1, Command Sequence error:
– error handler
b4 and b5
= 1
NO
Erase
Error (1)
If b5 = 1, Erase error:
– error handler
b5 = 0
YES
Erase to Protected
Block Error
If b1 = 1, Erase to Protected Block Error:
– error handler
b1 = 0
YES
End
AI08623c
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
Write 70h
– write 70h
do:
Read Status
Register
– read status register
NO
NO
b7 = 1
YES
while b7 = 1
If b6 = 0, Erase completed
b6 = 1
YES
Erase Complete
Read Memory Array command:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
or Program
Program/Erase Resume command:
– write D0h to resume the Erase
operation
– if the Erase operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
Write D0h
Write FFh
Read Data
Erase Continues
AI00615b
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 24. Unlock Device and Change Tuning Protection Code Flowchart
Reset
Add: don't care
Data: FFh
Issue Read command
5th: Write Cycle
Device locked
by tuning code
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 78h
Add: AAh
Data: 48h
1st: Write Cycle
6th: Write Cycle
2nd: Write Cycle
(old code,
factory setup = FFFFh)
Add: 00000h
Data: First 32 bit
Add: 00000h
Data: First 32 bit
7th: Write Cycle
(new code)
Add: don't care
Data: FFh
b7 = 1
YES
b7 = 1
YES
Issue
Read
command
Add: don't care
Data: 78h
Add: AAh
Data: 48h
3rd: Write Cycle
8th: Write Cycle
4th: Write Cycle
(old code,
factory setup = FFFFh)
Add: 00001h
Data: Second 32 bit
Add: 00001h
Data: Second 32 bit
9th: Write Cycle
(new code)
b7 = 1
YES
b7 = 1
YES
Read Status
Register
Reset
Device locked
by new code
NO
DEVICE LOCKED
b0 = 1
YES
DEVICE UNLOCKED
AI04501b
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 25. Unlock Device and Program a Tuning Protected Block Flowchart
Reset
Add: don't care
Data: FFh
Issue Read command
5th: Write Cycle
Device locked
by tuning code
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 78h
Add: AAh
Data: 40h
6th: Write Cycle
7th: Write Cycle
1st: Write Cycle
2nd: Write Cycle
(First part
of the tuning code)
Add: 00000h
Data: First 32 bit
Add: location to prog.
Data: data to prog.
Add: don't care
Data: FFh
b7 = 1
YES
b7 = 1
YES
Issue
Read
command
Add: don't care
Data: 78h
Status Register
check
3rd: Write Cycle
4th: Write Cycle
(Second part
of the tuning code)
Location
programmed
Add: 00001h
Data: Second 32 bit
b7 = 1
YES
Read Status
Register
NO
DEVICE LOCKED
b0 = 1
YES
DEVICE UNLOCKED
AI04502b
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 26. Unlock Device and Erase a Tuning Protected Block Flowchart
Reset
Add: don't care
Data: FFh
Issue Read command
5th: Write Cycle
Device locked
by tuning code
TUNING PROTECTION
UNLOCK SEQUENCE
Add: don't care
Data: 78h
Add: 55h
Data: 20h
6th: Write Cycle
7th: Write Cycle
1st: Write Cycle
2nd: Write Cycle
(First part
of the tuning code)
Add: 00000h
Data: First 32 bit
Add: block to erase
Data: D0h
Add: don't care
Data: FFh
b7 = 1
YES
b7 = 1
YES
Issue
Read
command
Add: don't care
Data: 78h
Status Register
check
3rd: Write Cycle
4th: Write Cycle
(Second part
of the tuning code)
Block
Erased
Add: 00001h
Data: Second 32 bit
b7 = 1
YES
Read Status
Register
NO
DEVICE LOCKED
b0 = 1
YES
DEVICE UNLOCKED
AI04503b
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 27. Power-up Sequence to Burst the Flash
Power-up
or Reset
BCR bit 15 = '1'
Asynchronous Read
Write 60h command
Set Burst Configuration Register Command:
– write 60h
– write 03h
and BCR on A15-A0
Write 03h with A15-A0
BCR inputs
BCR bit 15 = '0'
BCR bit 14-bit 0 = '1'
Synchronous Read
AI03834
53/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 28. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE
READ
ARRAY
NO
90h
YES
READ ELEC.
SIGNATURE
NO
98h
YES
D
READ CFI
NO
70h
YES
READ
STATUS
NO
20h
YES
ERASE
SET-UP
NO
40h
YES
ERASE
COMMAND
ERROR
NO
NO
PROGRAM
SET-UP
D0h
50h
E
YES
YES
A
CLEAR
C
STATUS
D
READ
STATUS
B
AI03835
54/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 29. Command Interface and Program Erase Controller Flowchart (b)
E
NO
48h
YES
TP
NO
78h
YES
TP
PROGRAM
SET_UP
F
NO
60h
YES
UNLOCK
SET_UP
NO
FFh
YES
G
SET BCR
SET_UP
NO
03h
YES
D
AI03836
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 30. Command Interface and Program Erase Controller Flowchart (c)
A
B
ERASE
YES
READY
NO
NO
READ
STATUS
B0h
YES
ERASE
SUSPEND
YES
READY
NO
NO
ERASE
SUSPENDED
READ
STATUS
YES
YES
READ
STATUS
70h
NO
YES
YES
PROGRAM
SET_UP
40h
NO
C
NO
READ
STATUS
READ
ARRAY
D0h
AI03837
56/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 31. Command Interface and Program Erase Controller Flowchart (d)
C
B
PROGRAM
YES
READY
NO
NO
READ
STATUS
B0h
YES
PROGRAM
SUSPEND
YES
READY
NO
NO
PROGRAM
SUSPENDED
READ
STATUS
YES
YES
READ
STATUS
70h
NO
NO
YES
READ
STATUS
READ
ARRAY
D0h
AI03838
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 32. Command Interface and Program Erase Controller Flowchart (e)
F
B
TP
PROGRAM
YES
NO
READ
STATUS
READY
G
B
TP
UNLOCK
YES
NO
READ
STATUS
READY
AI03839
58/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
REVISION HISTORY
Table 25. Document Revision History
Date
Version
Revision Details
20-Oct-2003
1.0
First Issue.
Figure 7, AC Measurement Load Circuit modified. I
Table 5, DC Characteristics.
test condition updated in
DDB
21-Oct-2003
20-Nov-2003
27-Apr-2004
1.1
1.2
2.0
Bit M3 no longer reserved, described in Burst Configuration Register section. Minor
text changes. Program and Erase Suspend Latency Times added to Table Table
10., Program, Erase Times and Program Erase Endurance Cycles.
A19 added in Figure 4.PQFP Connections (Top view through package).
Table 6.Burst Configuration Register, Note 1 updated.
DQ8-DQ15 and R signal names updated in Table 1., Signal Names.
Description of Valid Data Ready (R).signal updated.
Burst Length Bit (M2-M0).paragraph updated in Burst Configuration Register section.
X-Latency of 8 clock cycles added in Table 6., Burst Configuration Register
COMMAND INTERFACE section: Erase All Main Blocks command added, Read
Electronic Signature Command, Read Status Register Command, Write to Buffer
and Program Command, Set Block Protection Configuration Register Command and
Clear Block Protection Configuration Register Command. updated.
Erase All Main Blocks command added, Write to Buffer and Program, Set Burst
Configuration Register, Set and Clear Block Protection commands updated in Table
8., Commands.
30-July-2004
3.0
Standby Status removed from Table 9., Read Electronic Signature.
Definition of bit 4 updated in STATUS REGISTER section.
tQVKH removed from Figure 13., Synchronous Burst Read (Data Valid from ’n’
Clock Rising Edge).
05-Nov-2004
4.0
Datasheet status changed to Preliminary Data.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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