M58BW032DB55T6T [NUMONYX]
Flash, 1MX32, 55ns, PQFP80, PLASTIC, QFP-80;
| 型号： | M58BW032DB55T6T |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 1MX32, 55ns, PQFP80, PLASTIC, QFP-80 内存集成电路 |
| 文件： | 总9页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M58BW032BT, M58BW032BB
M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst)
3.3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■
SUPPLY VOLTAGE
Figure 1. Packages
–
–
VDD = 3.0V to 3.6V for Program, Erase
and Read
VDDQ = VDDQIN = 1.6V to 3.6V for I/O
Buffers
■
HIGH PERFORMANCE
–
–
Access Time: 45, 55 and 60ns
75MHz Effective Zero Wait-State Burst
Read
PQFP80 (T)
–
–
Synchronous Burst Reads
Asynchronous Page Reads
■
MEMORY ORGANIZATION
– Eight 64 Kbit small parameter Blocks
BGA
– Four 128Kbit large parameter Blocks (of
which one is OTP)
– Sixty-two 512Kbit main Blocks
LBGA80 (ZA)
10 x 8 ball array
■
■
HARDWARE BLOCK PROTECTION
–
–
WP pin Lock Program and Erase
VPEN signal for Program/Erase Enable
SOFTWARE BLOCK PROTECTION
■
■
ELECTRONIC SIGNATURE
–
Tuning Protection to Lock Program and
Erase with 64-bit User Programmable
Password (M58BW032B version only)
–
–
–
Manufacturer Code: 20h
Top Device Code M58BW032xT: 8838h
Bottom Device Code M58BW032xB:
8837h
■
■
■
SECURITY
–
64-bit Unique Device Identifier (UID)
OPERATING TEMPERATURE RANGE
FAST PROGRAMMING
–
–
Automotive (Grade 3): –40 to 125°C
Industrial (Grade 6): –40 to 90°C
–
Write to Buffer and Program capability
OPTIMIZED FOR FDI DRIVERS
–
–
Common Flash Interface (CFI)
Fast Program/Erase Suspend feature in
each block
■
LOW POWER CONSUMPTION
100µA Typical Standby
–
November 2004
1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SUMMARY DESCRIPTION
The M58BW032B/D is a 32Mbit non-volatile Flash
memory that can be erased electrically at the block
level and programmed in-system on a Double-
Word basis using a 3.0V to 3.6V VDD supply for the
circuit and a VDDQ supply down to 1.6V for the In-
put and Output buffers.
The devices support Asynchronous (Latch Con-
trolled and Page Read) and Synchronous Bus op-
erations. The Synchronous Burst Read Interface
allows a high data transfer rate controlled by the
Burst Clock, K, signal. It is capable of bursting
fixed or unlimited lengths of data. The burst type,
latency and length are configurable and can be
easily adapted to a large variety of system clock
frequencies and microprocessors. All Writes are
Asynchronous. On power-up the memory defaults
to Read mode with an Asynchronous Bus.
The device features an asymmetrical block archi-
tecture. The M58BW032B/D has an array of 62
main blocks of 512 Kbits each, plus 4 large param-
eter blocks of 128Kbits each and 8 small parame-
ter blocks of 64 Kbits each. The large and small
parameter blocks are located either at the top
(M58BW032BT, M58BW032DT) or at the bottom
(M58BW032BB, M58BW032DB) of the address
space. The first large parameter block is referred
to as Boot Block and can be used either to store a
boot code or parameters.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
All blocks are protected during power-up. The
M58BW032B features four different levels of hard-
ware and software block protection to avoid un-
wanted program/erase operations:
■
Write/Protect Enable input, WP, provides a
hardware protection of a combination of
blocks from program or erase operations. The
Block Protection configuration can be defined
individually by issuing a Set Block Protection
Configuration Register or Clear Block
Protection Configuration Register commands.
■
■
All Program or Erase operations are blocked
when Reset, RP, is held low.
A Program/Erase Enable input, VPEN, is used
to protect all blocks, preventing Program and
Erase operations from affecting their data.
■
The Program and Erase commands can be
password protected by the Tuning Protection
command.
The M58BW032D offers the same protection fea-
tures with the exception of the Tuning Block Pro-
tection which is disabled in the factory.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consump-
tion is reduced to the standby level, the device is
write protected and both the Status and Burst Con-
figuration Registers are cleared. A recovery time is
required when the RP input goes High.
A manufacturer and device code are available.
They can be read from the memory allowing pro-
gramming equipment or applications to automati-
cally match their interface to the characteristics of
the memory.
Finally, the M58BW032B/D features a Unique De-
vice Identifier (UID) which is programmed by ST. It
is unique for each die and can be used to imple-
ment cryptographic algorithms to improve securi-
ty.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
The memory is offered in PQFP80 (14 x 20mm)
and LBGA80 (1.0mm pitch) packages and it is
supplied with all the bits erased (set to ’1’).
2/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 1. Signal Names
Figure 2. Logic Diagram
A0-A19
Address inputs
DQ0-DQ7
Data Input/Output, Command Input
V
V
V
Data Input/Output, Burst Configuration
Register
V
DD DDQ DDQIN
PEN
DQ8-DQ15
DQ16-DQ31 Data Input/Output
B
Burst Address Advance
Chip Enable
A0-A19
DQ0-DQ31
E
K
L
G
Output Enable
K
Burst Clock
M58BW032BT
M58BW032BB
M58BW032DT
M58BW032DB
E
L
Latch Enable
RP
G
R
R
Valid Data Ready
RP
W
GD
WP
Reset /Power-Down
Write Enable
GD
W
Output Disable
Write Protect
WP
B
V
Supply Voltage
DD
V
Power Supply for Output Buffers
Power Supply for Input Buffers only
Program/Erase Enable
Ground
DDQ
V
V
V
V
DDQIN
PEN
SS
V
V
SSQ
SS
AI08918b
Input/Output Ground
Not Connected Internally
Don’t Use as Internally Connected
SSQ
NC
DU
3/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 3. LBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A15
A14
V
V
V
A6
A3
A2
DD
PEN
A9
SS
A16
A17
DQ3
A13
A18
A12
A11
A19
DQ2
DQ6
DQ10
DQ11
L
A8
NC
A5
A7
A4
DU
A1
A0
A10
DU
DQ0
DQ4
DQ7
DQ8
DQ12
DQ14
RP
NC
DQ31
DQ28
DQ25
DQ21
DQ19
G
DQ30
DQ26
DQ24
DQ23
DQ18
R
DQ29
V
DQ1
DQ5
DQ9
WP
B
DQ27
NC
V
DDQ
DDQ
V
V
SSQ
SSQ
G
H
J
V
DQ22
DQ17
E
V
DDQ
DDQ
DQ13
DQ15
DQ20
DQ16
DU
K
V
K
V
V
W
GD
DDQIN
SS
DD
AI08920b
4/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 4. PQFP Connections (Top view through package)
DQ16
DQ17
DQ18
DQ19
1
DQ15
DQ14
DQ13
DQ12
64
V
V
V
DDQ
SSQ
DDQ
V
SSQ
DQ20
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
M58BW032BT
M58BW032BB
M58BW032DT
12
53
M58BW032DB
V
V
V
DDQ
SSQ
DDQ
V
SSQ
DQ28
DQ3
DQ2
DQ1
DQ0
A19
A18
A17
A16
DQ29
DQ30
DQ31
DU
A0
A1
A2
41
24
AI08919c
5/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Block Protection
Block Protection. When the two protections are
disabled, WP and RP at VIH, the blocks locked by
the Tuning Block Protection cannot be modified.
All blocks are protected at power-up.
The M58BW032B features four different levels of
block protection. The M58BW032D has the same
block protection with the exception of the Tuning
Block Protection, which is disabled in the factory.
Tuning Block Protection
■
Write Protect Pin, WP, - When WP is Low,
VIL, the protection status that has been
configured in the Block Protection
Configuration Register is activated. The Block
Protection Configuration Register is volatile.
Any combination of blocks is possible. Any
attempt to program or erase a protected block
will be ignored and will return an error in the
Status Register.
Reset/Power-Down Pin, RP, - If the device is
held in reset mode (RP at VIL), no program or
erase operations can be performed on any
block.
Program/Erase Enable, VPEN, - VPEN
protects all blocks preventing Program and
Erase operations from affecting their data.
Program/Erase Enable must be kept High
(VIH) during all Program/Erase Controller
operations, otherwise the operations is not
guaranteed to succeed and data may become
corrupt.
The Tuning Block Protection is a software feature
to protect blocks from program or erase opera-
tions. It allows the user to lock program and erase
operations with a user definable 64 bit code. It is
only available on the M58BW032B version.
The code is written once in the Tuning Protection
Register and cannot be erased. When shipped the
flash memory will have the Tuning Protection
Code bits set to ‘1'. The user can program a ‘0’ in
any of the 64 positions. Once programmed it is not
possible to reset a bit to ‘1’ as the cells cannot be
erased. The Tuning Protection Register can be
programmed at any moment (after providing the
correct code), however once all bits are set to ‘0’
the Tuning Protection Code can no longer be al-
tered.
The Tuning Protection Code locks the program
and erase operations of all the blocks except for
blocks 12 and 13 for the bottom configuration, and
blocks 60 and 61 for the top configuration.
The tuning blocks are "locked" if the tuning protec-
tion code has not been provided, and “unlocked"
once the correct code has been provided. The tun-
ing blocks are locked after reset or power-up. The
tuning protection status can be monitored in the
Status Register. Refer to the Status Register sec-
tion.
■
■
■
Tuning Block Protection - M58BW032B
features a 64 bit password protection for
program and erase operations for a fixed
number of blocks After power-up or reset the
device is tuning protected. An Unlock
command is provided to allow program or
erase operations in all the blocks.
Refer to the Command Interface section for the
Tuning Protection Block Unlock and Tuning Pro-
tection Program commands.
After a device reset the first two kinds of block pro-
tection (WP, RP) can be combined to give a flexi-
ble block protection. They do not affect the Tuning
6/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PART NUMBERING
Table 2. Ordering Information Scheme
Example:
M58BW032B
T
45
T
3
T
Device Type
M58
Architecture
B = Burst Mode
Operating Voltage
W = V = 3.0V to 3.6V; V
= V
=1.6 to V
DDQIN DD
DD
DDQ
Device Function
032B = 32 Mbit (x32), Boot Block, Burst Tuning Protection
032D = 32 Mbit (x32), Boot Block, Burst no Tuning Protection
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
45 = 45ns
55 = 55ns
60 = 60ns
Package
T = PQFP80
ZA = LBGA80: 1.0mm pitch
Temperature Range
3 = –40 to 125 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
7/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
REVISION HISTORY
Table 3. Document Revision History
Date
Version
Revision Details
05-Nov-2004
1.0
First Issue.
8/9
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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