M48Z08-100PC1 [STMICROELECTRONICS]
64 Kbit 8Kb x 8 ZEROPOWER SRAM; 64 Kbit的是8K ×8 ZEROPOWER SRAM
| 型号： | M48Z08-100PC1 |
| 厂家： | 
ST |
| 描述： | 64 Kbit 8Kb x 8 ZEROPOWER SRAM |
| 文件： | 总18页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z08
M48Z18
®
64 Kbit (8Kb x 8) ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
SNAPHAT (SH)
Battery
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
28
– M48Z08: 4.50V ≤ VPFD ≤ 4.75V
– M48Z18: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
1
28
1
PCDIP28 (PC)
Battery CAPHAT
SOH28 (MH)
PACKAGING INCLUDES a 28 LEAD SOIC
and SNAPHAT® TOP (to be Ordered
Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY
PIN and FUNCTION COMPATIBLE with the
DS1225 and JEDEC STANDARD 8K x 8
SRAMs
Figure 1. Logic Diagram
DESCRIPTION
V
CC
The M48Z08/18 ZEROPOWER® RAM is an 8K x
8 non-volatile static RAM which is pin and func-
tional compatible with the DS1225. The monolithic
chip is available in two special packages to provide
a highly integrated battery backed-up memory so-
lution.
13
8
A0-A12
W
DQ0-DQ7
M48Z08
M48Z18
Table 1. Signal Names
E
A0-A12
Address Inputs
Data Inputs / Outputs
Chip Enable
G
DQ0-DQ7
E
G
Output Enable
Write Enable
Supply Voltage
Ground
V
SS
AI01022
W
VCC
VSS
March 1999
1/18
M48Z08, M48Z18
Figure 2A. DIP Pin Connections
Figure 2B. SOIC Pin Connections
NC
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 NC
25 A8
24 A9
23 A11
3
NC
A8
A6
A6
4
A5
A5
5
A9
A4
A4
6
A11
G
A3
22
G
A3
7
M48Z08
M48Z18
M48Z18
A2
21 A10
20
A2
8
A10
E
A1
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
V
SS
SS
AI01183
AI01023B
Warning:
Warning:
NC = Not Connected.
NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
–40 to 85
–40 to 85
260
Unit
Ambient Operating Temperature
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
°C
°C
°C
V
TSTG
(2)
TSLD
VIO
VCC
IO
–0.3 to 7
–0.3 to 7
20
V
Output Current
mA
W
PD
Power Dissipation
1
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode
Deselect
Write
VCC
E
VIH
VIL
VIL
VIL
X
G
X
W
X
DQ0-DQ7
High Z
DIN
Power
Standby
4.75V to 5.5V
or
4.5V to 5.5V
X
VIL
VIH
VIH
X
Active
Read
VIL
VIH
X
DOUT
Active
Read
High Z
High Z
High Z
Active
Deselect
Deselect
V
SO to VPFD (min)
CMOS Standby
Battery Back-up Mode
≤ VSO
X
X
X
Note:
1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2/18
M48Z08, M48Z18
Figure 3. Block Diagram
A0-A12
LITHIUM
CELL
DQ0-DQ7
E
POWER
8K x 8
SRAM ARRAY
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
PFD
W
G
V
V
CC
SS
AI01394
DESCRIPTION
Table 4. AC Measurement Conditions
(cont’d)
The M48Z08/18 is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
1.5V
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no
longer driven.
The 28 pin 600mil DIP CAPHAT houses the
M48Z08/18 silicon with a long life lithium button cell
in a single package.
Figure 4. AC Testing Load Circuit
5V
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential batterydamage due to the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF or 30pF
L
The SOIC and battery packages are shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form.
C
includes JIG capacitance
L
AI01398
3/18
M48Z08, M48Z18
Table 5. Capacitance (1, 2)
°
(TA = 25 C)
Symbol
Parameter
Input Capacitance
Test Condition
VIN = 0V
Min
Max
10
Unit
pF
CIN
(3)
CIO
Input / Output Capacitance
VOUT = 0V
10
pF
Notes:
1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected
Table 6. DC Characteristics
°
(TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
E = VIH
Min
Max
Unit
µA
µA
mA
mA
mA
V
(1)
ILI
±1
(1)
ILO
±5
ICC
ICC1
ICC2
80
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
3
3
E = VCC – 0.2V
(2)
VIL
–0.3
2.2
0.8
VIH
VOL
VOH
Input High Voltage
VCC + 0.3
0.4
V
Output Low Voltage
IOL = 2.1mA
IOH = –1mA
V
Output High Voltage
2.4
V
Notes:
1. Outputs deselects.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
°
(TA = 0 to 70 C)
Symbol
Parameter
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
VPFD
VPFD
VSO
tDR
Power-fail Deselect Voltage (M48Z08)
Power-fail Deselect Voltage (M48Z18)
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
V
V
11
YEARS
Note:
1. All voltages referenced to VSS
.
DESCRIPTION
(cont’d)
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data until valid power re-
turns.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z08/18 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
4/18
M48Z08, M48Z18
Table 8. Power Down/Up Mode AC Characteristics
°
(TA = 0 to 70 C)
Symbol
Parameter
Min
0
Max
Unit
µs
tPD
E or W at VIH before Power Down
(1)
tF
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
VPFD(min) to VPFD (max) VCC Rise Time
VSO to VPFD (min) VCC Rise Time
E or W at VIH after Power Up
300
10
0
µs
(2)
tFB
µs
tR
µs
tRB
1
µs
tREC
1
ms
Notes
µ
: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tRB
DON'T CARE
tREC
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systems
may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/18
M48Z08, M48Z18
Table 9. Read Mode AC Characteristics
°
(TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z08 / M48Z18
-100
Symbol
Parameter
Unit
Min
Max
tAVAV
Read Cycle Time
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tAVQV
Address Valid to Output Valid
100
100
50
(1)
tELQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
(1)
tGLQV
(2)
tELQX
10
5
(2)
tGLQX
(2)
tEHQZ
50
40
(2)
tGHQZ
(1)
tAXQX
5
Notes:
1. CL = 100pF (see Figure 4).
2. CL = 30pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note:
Write Enable (W) = High.
6/18
M48Z08, M48Z18
Table 10. Write Mode AC Characteristics
°
(TA = 0 to 70 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z08 / M48Z18
-100
Symbol
Parameter
Unit
Min
100
0
Max
tAVAV
tAVWL
tAVEL
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tE1HDX
80
80
10
10
50
30
5
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
5
(1, 2)
tWLQZ
50
tAVWH
tAVEH
80
80
10
(1, 2)
tWHQX
Notes:
1. CL = 30pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
READ MODE
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
The M48Z08/18 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 65,536 locations in the
static storage array. Thus, the unique address
specified by the 13 Address Inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time (tGLQV).
WRITE MODE
The M48Z08/18 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E.
Awrite is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
7/18
M48Z08, M48Z18
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
8/18
M48Z08, M48Z18
DATA RETENTION MODE
and the power supply is switched to external VCC
.
Write protection continues until VCC reaches VPFD
(min) plus tREC (min). E should be kept high as VCC
rises past VPFD(min) to prevent inadvertent write
cycles prior to system stabilization. Normal RAM
operation can resume tREC after VCC exceeds
VPFD(max).
With valid VCC applied, the M48Z08/18 operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automat-
ically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
For more information on Battery Storage Life refer
to the Application Note AN1012.
Note:
A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z08/18 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
SYSTEM BATTERY LIFE
The useful life of the battery in the M48Z08/18 is
expected to ultimately come to an end for one of
two reasons: either because it has been dis-
charged while providing current to the RAM in the
battery back-up mode, or because the effects of
aging render the cell useless before it can actually
be completely discharged. The two effects are
virtually unrelated, allowing discharge or Capacity
Consumption, and the effects of aging or Storage
Life, to be treated as two independent but simulta-
neous mechanisms. The earlier occurring failure
mechanism defines the battery system life of the
M48Z08/18.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48Z08/18 for
an accumulated period of at least 11 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the battery is disconnected,
Figure 9. Predicted Battery Storage Life versus Temperature
AI01399
50
40
30
t50% (AVERAGE)
t1%
20
10
8
6
5
4
3
2
1
20
30
40
50
60
70
80
90
TEMPERATURE (Degrees Celsius)
9/18
M48Z08, M48Z18
Cell Storage Life
Reference for System Life
Storage life is primarily a function of temperature.
Figure 9 illustrates the approximate storage life of
the M48Z08/18 battery over temperature. The re-
sults in Figure 9 are derived from temperature
accelerated life test studies performed at SGS-
THOMSON. For the purpose of the testing, a cell
failure is defined as the inability of a cell stabilized
Each M48Z08/18 is marked with a nine digit manu-
facturing date code in the form of H99XXYYZZ. For
example, H995B9431 is:
H = fabricated in Carrollton, TX
9 = assembled in Muar, Malaysia,
9 = tested in Muar, Malaysia,
°
at 25 C to produce a 2.4V closed circuit voltage
5B = lot designator,
Ω
across a 250 k load resistor. The two lines, t1%
and t50%, represent different failure rate distribu-
9431 = assembled in the year 1994, work week 31.
°
tions for the cell’s storage life. At70 C, for example,
the t1% line indicates that an M48Z08/18 has a 1%
chance of having a battery failure 28 years into its
life while the t50% shows the part has a 50% chance
of failure at the 50 year mark. The t1% line repre-
sents the practical onset of wear out and can be
considered the worst case Storage Life for the cell.
The t50% can be considered the normal or average
life.
POWER SUPPLY DECOUPLING and UNDER-
SHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A ceramic bypass capaci-
Calculating Storage Life
The following formula can be used to predict stor-
age life:
µ
tor value of 0.1 F (as shown in Figure 10) is
1
recommended in order to provide the needed filter-
ing.
{[(TA1/TT)/SL1]+[(TA2/TT)/SL2]+...+[(TAN/TT)/SLN]}
where,
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
– TA1, TA2, TAN = time at ambient temperature
1, 2, etc.
– TT = total time = TA1+TA2+...+TAN
– SL1, SL2, SLN = storage life at temperature 1,
2, etc.
For example, an M48Z08/18 is exposed to tem-
°
peratures of 55 C or less for 8322 hrs/yr, and
°
°
temperatures greater than 60 C but less than 70 C
for the remaining 438 hrs/yr. Reading predicted t1%
values from Figure 9,
– SL1 200 yrs, SL2 = 28 yrs
– TT = 8760 hrs/yr
Figure 10. Supply Voltage Protection
– TA1 = 8322 hrs/yr, TA2 = 438 hrs/yr
≥
Predicted storage life
V
CC
1
{[(8322/8760)/200]+[(431/8760)/28]}
V
CC
or 154 years.
As can been seen from these calculations and the
results, the expected lifetime of the M48Z08/18
should exceed most system requirements.
0.1µF
DEVICE
Estimated System Life
V
SS
Since either storage life or capacity consumption
can end the battery’s life, the system life is marked
by which ever occurs first.
AI02169
10/18
M48Z08, M48Z18
ORDERING INFORMATION SCHEME
Example:
M48Z18 -100 MH
1
TR
Supply Voltage and Write
Protect Voltage
Speed
Package
Temp. Range
Shipping Method
for SOIC
08 (1) VCC = 4.75V to 5.5V
-100 100ns
PC
PCDIP28
1
0 to 70 °C
blank Tubes
V
PFD = 4.5V to 4.75V
MH (2,3)SOH28
6 (4) –40 to 85 °C
TR Tape &Reel
18
VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
Notes:
1. The M48Z08 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4Z28-BR00SH1" in plastic tube or "M4Z28-BR00SH1TR" in Tape & Reel form.
3. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are
functionally equivalent (see package drawing section for details).
4. Temperature range available for M48Z18 product only.
Caution:
Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
11/18
M48Z08, M48Z18
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm
Min
inches
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale.
12/18
M48Z08, M48Z18
SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT
mm
Min
inches
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Min
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing not to scale.
13/18
M48Z08, M48Z18
SOH28 - 28 lead Plastic Small Outline, 2-socket battery SNAPHAT
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-B
Drawing not to scale.
14/18
M48Z08, M48Z18
SH - 4-pin SNAPHAT Housing for 49 mAh Battery
mm
Min
inches
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Min
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
A2
A1
A
A3
L
eA
D
B
eB
E
SH
Drawing not to scale.
15/18
M48Z08, M48Z18
SH - 2-pin SNAPHAT Housing for 49 mAh Battery
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
3.20
0.018
0.835
0.560
0.126
0.080
D
E
eB
L
2.03
A2
A1
A
A3
L
B
eB
D
E
SHZP-A
Drawing not to scale.
16/18
M48Z08, M48Z18
SH - 2-pin SNAPHAT Housing for 130 mAh Battery
mm
Min
inches
Symb
Typ
Max
10.54
8.51
Typ
Min
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
3.20
0.56
0.018
0.835
0.680
0.126
0.080
D
21.84
18.03
3.61
E
eB
L
2.03
2.29
A2
A1
A
A3
L
B
eB
D
E
SHZP-B
Drawing not to scale.
17/18
M48Z08, M48Z18
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
® TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics
CAPHAT and BYTEWIDE are trademarks of STMicroelectronics
All other names are the property of their respective owners
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www.st.com
18/18
相关型号：
©2020 ICPDF网 联系我们和版权申明