M48Z08-150PC6 [STMICROELECTRONICS]
16 Kbit 2Kb x 8 ZEROPOWER SRAM; 16 Kbit的2K位×8 ZEROPOWER SRAM
| 型号： | M48Z08-150PC6 |
| 厂家： | 
ST |
| 描述： | 16 Kbit 2Kb x 8 ZEROPOWER SRAM |
| 文件： | 总12页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z02
M48Z12
®
16 Kbit (2Kb x 8) ZEROPOWER SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
24
1
– M48Z02: 4.50V ≤ VPFD ≤ 4.75V
– M48Z12: 4.20V ≤ VPFD ≤ 4.50V
PCDIP24 (PC)
Battery CAPHAT
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2K x 8 SRAMs
Figure 1. Logic Diagram
DESCRIPTION
The M48Z02/12 ZEROPOWER® RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
A special 24 pin 600mil DIP CAPHAT package
houses the M48Z02/12 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
V
CC
11
8
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data and clockfunction-
ality for an accumulated time period of at least 10
years in the absence of power over the operating
temperature range.
A0-A10
DQ0-DQ7
W
E
M48Z02
M48Z12
Table 1. Signal Names
A0-A10
Address Inputs
Data Inputs / Outputs
Chip Enable
G
DQ0-DQ7
E
V
SS
G
Output Enable
Write Enable
Supply Voltage
Ground
AI01186
W
VCC
VSS
May 1999
1/12
M48Z02, M48Z12
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
–40 to 85
–40 to 85
260
Unit
°C
°C
°C
V
Ambient Operating Temperature
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
TSTG
(2)
TSLD
VIO
VCC
IO
–0.3 to 7
–0.3 to 7
20
V
Output Current
mA
W
PD
Power Dissipation
1
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
Deselect
Write
VCC
E
VIH
VIL
VIL
VIL
X
G
X
W
X
DQ0-DQ7
High Z
DIN
Power
Standby
4.75V to 5.5V
or
4.5V to 5.5V
X
VIL
VIH
VIH
X
Active
Read
VIL
VIH
X
DOUT
Active
Read
High Z
High Z
High Z
Active
Deselect
Deselect
V
SO to VPFD (min)
CMOS Standby
Battery Back-up Mode
≤ VSO
X
X
X
Notes
: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
DESCRIPTION
(cont’d)
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
A7
A6
1
2
3
4
5
6
7
8
9
24
V
CC
23 A8
A5
22 A9
A4
21
20
W
G
A3
A2
M48Z02 19 A10
M48Z12
A1
18
E
A0
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
DQ0
DQ1 10
DQ2 11
V
12
SS
AI01187
2/12
M48Z02, M48Z12
Figure 3. Block Diagram
A0-A10
LITHIUM
CELL
DQ0-DQ7
E
POWER
2K x 8
SRAM ARRAY
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
V
PFD
W
G
V
V
CC
SS
AI01255
Table 4. AC Measurement Conditions
READ MODE
The M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time (tGLQV).
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0V to 3V
1.5V
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF
L
C
includes JIG capacitance
L
AI01019
3/12
M48Z02, M48Z12
Table 5. Capacitance (1)
°
(TA = 25 C)
Symbol
Parameter
Input Capacitance
Test Condition
VIN = 0V
Min
Max
10
Unit
pF
CIN
(2)
CIO
Input / Output Capacitance
VOUT = 0V
10
pF
Notes:
1. Effective capacitance measured with power supply at 5V.
2. Outputs deselected
Table 6. DC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Test Condition
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
E = VIH
Min
Max
Unit
µA
µA
mA
mA
mA
V
(1)
ILI
±1
(1)
ILO
±5
ICC
ICC1
ICC2
80
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
3
3
E = VCC – 0.2V
(2)
VIL
–0.3
2.2
0.8
VIH
VOL
VOH
Input High Voltage
VCC + 0.3
0.4
V
Output Low Voltage
IOL = 2.1mA
IOH = –1mA
V
Output High Voltage
2.4
V
Notes:
1. Outputs Deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics (1)
°
°
(TA = 0 to 70 C or –40 to 85 C)
Symbol
VPFD
VPFD
VSO
Parameter
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
Power-fail Deselect Voltage (M48Z02)
Power-fail Deselect Voltage (M48Z12)
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
V
V
tDR
10
YEARS
Note:
1. All voltages referenced to VSS
.
4/12
M48Z02, M48Z12
Table 8. Power Down/Up Mode AC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C)
Symbol
Parameter
Min
0
Max
Unit
µs
tPD
E or W at VIH before Power Down
(1)
tF
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSO VCC Fall Time
VPFD(min) to VPFD (max) VCC Rise Time
VSO to VPFD (min) VCC Rise Time
E or W at VIH after Power Up
300
10
0
µs
(2)
tFB
tR
µs
µs
tRB
1
µs
tREC
2
ms
Notes
µ
: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 50 s after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tRB
DON'T CARE
tREC
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systems
may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/12
M48Z02, M48Z12
Table 9. Read Mode AC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z02 / M48Z12
-150
Symbol
Parameter
Unit
-70
-200
Min
Max
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAXQX
Read Cycle Time
70
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Output Valid
70
70
35
150
150
75
200
200
80
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
5
5
10
5
10
5
25
25
35
35
40
40
10
5
5
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A10
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01330
Note:
Write Enable (W) = High.
6/12
M48Z02, M48Z12
Table 10. Write Mode AC Characteristics
°
°
(TA = 0 to 70 C or –40 to 85 C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z02 / M48Z12
-150
Symbol
Parameter
Unit
-200
-70
Min
70
0
Max
Min
150
0
Max
Min
200
0
Max
tAVAV
tAVWL
tAVEL
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
0
0
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
tWLQZ
tAVWH
tAVEH
tWHQX
50
55
0
90
90
10
10
40
40
5
120
120
10
10
60
60
5
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
0
30
30
5
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
5
5
5
25
50
60
60
60
5
120
120
10
140
140
10
WRITE MODE
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
The M48Z02/12 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
7/12
M48Z02, M48Z12
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A10
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01331
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A10
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01332B
8/12
M48Z02, M48Z12
Figure 9. Checking the BOK Flag Status
DATA RETENTION MODE
With valid VCC applied, the M48Z02/12 operates as
a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automat-
ically power-fail deselect, write protecting itself
when VCC falls within the VPFD(max), VPFD(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."
POWER-UP
READ DATA
AT ANY ADDRESS
Note:
A power failure during a write cycle may
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z02/12 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
READ DATA
AT SAME
ADDRESS AGAIN
The power switching circuit connects external VCC
to the RAM and disconnects the battery when VCC
rises above VSO. As VCC rises, the battery voltage
is checked. If the voltage is too low, an internal
Battery Not OK (BOK) flag will be set. The BOKflag
can be checked after power up. If the BOK flag is
set, the first write attempted will be blocked. The
flag is automatically cleared after the first write, and
normal RAM operation resumes. Figure 9 illus-
trates how a BOK check routine could be struc-
tured.
IS DATA
COMPLEMENT
OF FIRST
NO (BATTERY LOW)
READ?
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
POWER SUPPLY DECOUPLING and UNDER-
SHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A ceramic bypass capaci-
AI00607
Figure 10. Supply Voltage Protection
µ
tor value of 0.1 F (as shown in Figure 10) is
V
CC
recommended in order to provide the needed filter-
ing.
V
CC
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
0.1µF
DEVICE
V
SS
AI02169
9/12
M48Z02, M48Z12
ORDERING INFORMATION SCHEME
Example:
M48Z02
-70 PC
1
Supply Voltage and Write
Protect Voltage
Speed
Package
PCDIP24
Temp. Range
02
V
V
CC = 4.75V to 5.5V
PFD = 4.5V to 4.75V
-70
70ns
PC
1
6
0 to 70 °C
–40 to 85 °C
-150
-200
150ns
200ns
12
VCC = 4.5V to 5.5V
PFD = 4.2V to 4.5V
V
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/12
M48Z02, M48Z12
PCDIP24 - 24 pin Plastic DIP, battery CAPHAT
mm
Min
inches
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
34.80
18.34
2.79
30.73
16.00
3.81
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
34.29
17.83
2.29
25.15
15.24
3.05
24
0.350
0.015
0.330
0.015
0.045
0.008
1.350
0.702
0.090
0.990
0.600
0.120
24
0.380
0.030
0.350
0.021
0.070
0.012
1.370
0.722
0.110
1.210
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale.
11/12
M48Z02, M48Z12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners
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12/12
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