M48Z02-70PC6 [STMICROELECTRONICS]
5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM; 5V ， 16千位（ 2K位×8 ） ZEROPOWER SRAM
| 型号： | M48Z02-70PC6 |
| 厂家： | 
ST |
| 描述： | 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| 文件： | 总16页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z02
M48Z12
®
5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM
Figure 1. 24-pin CAPHAT, DIP Package
and POWER-FAIL CONTROL CIRCUIT
■ UNLIMITED WRITE CYCLES
■ READ CYCLE TIME EQUALS WRITE CYCLE
TIME
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
24
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
1
PFD
– M48Z02: V = 4.75 to 5.5V;
CC
PCDIP24 (PC)
Battery/Crystal
CAPHAT
4.5V ≤ V
≤ 4.75V
PFD
– M48Z12: V = 4.5 to 5.5V;
CC
4.2V ≤ V
≤ 4.5V
PFD
■ SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE
■ PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2K x 8 SRAMs
April 2003
1/16
Rev. 3.1
M48Z02, M48Z12
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 5
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. WRITE Enable Controlled, WRITE AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Checking the BOK Flag Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
M48Z02, M48Z12
SUMMARY DESCRIPTION
®
The M48Z02/12 ZEROPOWER RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
the absence of power over commercial operating
temperature range.
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
A special 24-pin, 600mil DIP CAPHAT™ package
houses the M48Z02/12 silicon with a long life lithi-
um button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data functionality for
an accumulated time period of at least 10 years in
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A10
Address Inputs
Data Inputs / Outputs
Chip Enable
V
CC
DQ0-DQ7
11
8
E
A0-A10
DQ0-DQ7
G
W
Output Enable
WRITE Enable
Supply Voltage
Ground
W
E
M48Z02
M48Z12
V
CC
V
SS
G
V
SS
AI01186
Figure 3. DIP Connections
A7
A6
1
2
3
4
5
6
7
8
9
24
V
CC
23 A8
A5
22 A9
A4
21
20
W
G
A3
A2
M48Z02 19 A10
M48Z12
A1
18
E
A0
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
DQ0
DQ1 10
DQ2 11
V
12
SS
AI01187
3/16
M48Z02, M48Z12
Figure 4. Block Diagram
A0-A10
LITHIUM
CELL
DQ0-DQ7
E
POWER
2K x 8
SRAM ARRAY
VOLTAGE SENSE
AND
V
SWITCHING
CIRCUITRY
PFD
W
G
V
V
CC
SS
AI01255
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
Grade 1
Grade 6
°C
T
A
Ambient Operating Temperature
–40 to 85
–40 to 85
T
Storage Temperature (V Off, Oscillator Off)
°C
°C
STG
CC
(1)
Lead Solder Temperature for 10 seconds
260
T
SLD
V
Input or Output Voltages
Supply Voltage
–0.3 to 7
V
V
IO
V
CC
–0.3 to 7
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
4/16
M48Z02, M48Z12
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M48Z02
4.75 to 5.5
0 to 70
–
M48Z12
4.5 to 5.5
0 to 70
–40 to 85
100
Unit
V
Supply Voltage (V
)
CC
Grade 1
Grade 6
°C
°C
pF
ns
V
Ambient Operating Temperature (T )
A
Load Capacitance (C )
100
L
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
1.5
0 to 3
Input and Output Timing Ref. Voltages
1.5
V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF
L
C
includes JIG capacitance
L
AI01019
Table 4. Capacitance
Symbol
(1,2)
Min
Max
10
Unit
Parameter
C
Input Capacitance
Input / Output Capacitance
pF
pF
IN
(3)
10
C
IO
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
5/16
M48Z02, M48Z12
Table 5. DC Characteristics
(1)
Symbol
Parameter
Min
Max
±1
±1
80
3
Unit
µA
Test Condition
0V ≤ V ≤ V
Input Leakage Current
I
IN
CC
LI
(2)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
µA
I
OUT
LO
I
Outputs open
mA
mA
mA
CC
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
I
I
IH
CC1
E = V – 0.2V
3
CC
CC2
(3)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
V
V
V
V
V
IL
V
V
+ 0.3
IH
CC
V
V
I
= 2.1mA
= –1mA
OH
0.4
OL
OL
I
2.4
OH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
2. Outputs deselected.
3. Negative spikes of –1V allowed for up to 10ns once per Cycle.
OPERATION MODES
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
data security in the midst of unpredictable system
operation brought on by low V . As V falls be-
CC
CC
low approximately 3V, the control circuitry con-
nects the battery which maintains data operation
until valid power returns.
tion. When V is out of tolerance, the circuit write
CC
protects the SRAM, providing a high degree of
Table 6. Operating Modes
V
Mode
Deselect
WRITE
READ
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.75 to 5.5V
or
4.5 to 5.5V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
Active
IL
OUT
V
IH
READ
High Z
High Z
High Z
Active
(1)
Deselect
X
X
X
CMOS Standby
V
SO
to V
(min)
PFD
(1)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
1. See Table 10, page 11 for details.
6/16
M48Z02, M48Z12
READ Mode
The M48Z02/12 is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
available after the latter of the Chip Enable Access
time (t
) or Output Enable Access time
ELQV
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
indeterminate state until t
, the data lines will be driven to an
AVQV
. If the Address In-
AVQV
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
within Address Access time (t
) after the last
AVQV
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
time (t
) but will go indeterminate until the next
AXQX
Address Access.
Figure 6. READ Mode AC Waveforms
tAVAV
VALID
A0-A10
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01330
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
M48Z02/M48Z12
–150
(1)
Symbol
–70
Max
–200
Unit
Parameter
Min
Min
Max
Min
Max
t
READ Cycle Time
70
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
35
150
150
75
200
200
80
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
ELQV
t
GLQV
t
5
5
10
5
10
5
ELQX
t
GLQX
t
25
25
35
35
40
40
EHQZ
t
GHQZ
t
10
5
5
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
7/16
M48Z02, M48Z12
WRITE Mode
The M48Z02/12 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
er READ or WRITE cycle. Data-in must be valid t
D-
prior to the end of WRITE and remain valid for
VWH
t
afterward. G should be kept high during
WHDX
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WLQZ
a minimum of t
from Chip Enable or t
EHAX
WHAX
from WRITE Enable prior to the initiation of anoth-
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
A0-A10
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01331
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A10
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01332B
8/16
M48Z02, M48Z12
Table 8. WRITE Mode AC Characteristics
M48Z02/M48Z12
–150
(1)
Symbol
–70
–200
Unit
Parameter
Min Max Min Max Min Max
t
WRITE Cycle Time
70
0
150
0
200
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable 1 Low
WRITE Enable Pulse Width
AVWL
t
0
0
0
AVEL
t
50
55
0
90
90
10
10
40
40
5
120
120
10
10
60
60
5
WLWH
t
Chip Enable Low to Chip Enable 1 High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
WHDX
t
5
5
5
EHDX
t
25
50
60
WLQZ
t
60
60
5
120
120
10
140
140
10
AVWH
t
AVEH
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
9/16
M48Z02, M48Z12
Data Retention Mode
Figure 9. Checking the BOK Flag Status
With valid V
applied, the M48Z02/12 operates
CC
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
POWER-UP
READ DATA
AT ANY ADDRESS
self when V
falls within the V
(max), V
PFD PFD
CC
(min) window. All outputs become high imped-
ance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
tent. At voltages below V
(min), the user can be
PFD
assured the memory will be in a write protected
READ DATA
AT SAME
ADDRESS AGAIN
state, provided the V fall time is not less than t .
CC
F
The M48Z02/12 may respond to transient noise
spikes on V that reach into the deselect window
CC
during the time the device is sampling V . There-
CC
fore, decoupling of the power supply lines is rec-
ommended.
IS DATA
NO (BATTERY LOW)
The power switching circuit connects external V
to the RAM and disconnects the battery when V
COMPLEMENT
OF FIRST
READ?
CC
CC
rises above V . As V rises, the battery voltage
SO
CC
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
is checked. If the voltage is too low, an internal
Battery Not OK (BOK) flag will be set. The BOK
flag can be checked after power up. If the BOK flag
is set, the first WRITE attempted will be blocked.
The flag is automatically cleared after the first
WRITE, and normal RAM operation resumes. Fig-
ure 9 illustrates how a BOK check routine could be
structured.
(BATTERY OK) YES
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
For more information on a Battery Storage Life re-
fer to the Application Note AN1012.
AI00607
Figure 10. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tDR
tR
tPD
tFB
tRB
tREC
RECOGNIZED
NOTE
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as V rises past V
(min). Some systems
PFD
CC
may perform inadvertent WRITE cycles after V rises above V
(min) but before normal system operations begin. Even though a
CC
PFD
power on reset is being applied to the processor, a reset condition may not occur until after the system is running.
10/16
M48Z02, M48Z12
Table 9. Power Down/Up AC Characteristics
(1)
Symbol
Min
0
Max
Unit
µs
Parameter
t
PD
E or W at V before Power Down
IH
(2)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
(3)
V
V
V
V
Fall Time
10
0
µs
µs
µs
ms
t
PFD
PFD
SS CC
FB
t
(min) to V
(max) V Rise Time
R
PFD CC
t
to V
(min) V Rise Time
PFD CC
1
RB
SS
t
E or W at V after Power Up
IH
2
REC
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after V pass-
PFD CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
SS FB
PFD
Table 10. Power Down/Up Trip Points DC Characteristics
(1,2)
Symbol
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
V
Parameter
M48Z02
M48Z12
V
PFD
Power-fail Deselect Voltage
V
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
V
SO
(3)
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
A
CC
3. At 25°C, V = 0V.
CC
Figure 11. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
-60
-80
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
11/16
M48Z02, M48Z12
V
Noise And Negative Going Transients
Figure 12. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
12) is recommended in order to provide the need-
ed filtering.
V
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
V
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
AI02169
mends connecting a schottky diode from V
to
CC
V
(cathode connected to V , anode to V ).
SS
CC SS
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
12/16
M48Z02, M48Z12
PACKAGE MECHANICAL INFORMATION
Figure 13. PCDIP24 – 24-pin Plastic DIP, Battery CAPHAT™, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note: Drawing is not to scale.
Table 11. PCDIP24 – 24-pin Plastic DIP, Battery CAPHAT™, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
34.80
18.34
2.79
30.73
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
34.29
17.83
2.29
25.15
15.24
3.05
24
0.350
0.015
0.330
0.015
0.045
0.008
1.350
0.702
0.090
0.990
0.600
0.120
24
0.380
0.030
0.350
0.021
0.070
0.012
1.370
0.722
0.110
1.210
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
13/16
M48Z02, M48Z12
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M48Z
02
–70
PC
1
TR
Device Type
M48Z
Supply Voltage and Write Protect Voltage
02 = V = 4.75 to 5.5V; V
= 4.5 to 4.75V
CC
PFD
12 = V = 4.5 to 5.5V; V
= 4.2 to 4.5V
PFD
CC
Speed
–70 = 70ns (M48Z02/12)
–150 = 150ns (M48Z02/12)
–200 = 200ns (M48Z02/12)
Package
PC = PCDIP24
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method
blank = Tubes
TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest you.
14/16
M48Z02, M48Z12
REVISION HISTORY
Table 13. Document Revision History
Date
Rev. #
Revision Details
May 1999
1.0
First issue
Reformatted; Temperature information added to tables (Table 2, 3, 4, 5, 7, 8, 9, 10); Figure
updated (Figure 10)
09-Jul-01
2.0
17-Dec-01
20-May-02
01-Apr-03
22-Apr-03
2.1
2.2
3.0
3.1
Remove references to “clock” in document
Updated V Noise and Negative Going Transients text
CC
v2.2 template applied; test condition updated (Table 10)
Fix error in Ordering Information (Table 12)
15/16
M48Z02, M48Z12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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