M48T35-70PC6 [STMICROELECTRONICS]
256 Kbit 32Kb x8 TIMEKEEPER SRAM; 256千位32Kb的X8 TIMEKEEPER SRAM
| 型号： | M48T35-70PC6 |
| 厂家： | 
ST |
| 描述： | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| 文件： | 总18页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T35
M48T35Y
®
256 Kbit (32Kb x8) TIMEKEEPER SRAM
■ INTEGRATED ULTRA LOW POWER SRAM,
SNAPHAT (SH)
Battery
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
■ BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■ BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
■ FREQUENCY TEST OUTPUT for REAL TIME
28
CLOCK
1
■ AUTOMATIC POWER-FAIL CHIP DESELECT
28
PCDIP28 (PC)
and WRITE PROTECTION
1
Battery CAPHAT
■ WRITE PROTECT VOLTAGES
SOH28 (MH)
(V
PFD
= Power-fail Deselect Voltage):
– M48T35: 4.5V ≤ V
≤ 4.75V
PFD
– M48T35Y: 4.2V ≤ V
≤ 4.5V
PFD
■ SELF-CONTAINED BATTERY and CRYSTAL
Figure 1. Logic Diagram
in the CAPHAT DIP PACKAGE
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT HOUSING
CONTAINING the BATTERY and CRYSTAL
V
CC
®
■ SNAPHAT HOUSING (BATTERY and
CRYSTAL) is REPLACEABLE
15
8
■ PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32Kb x8 SRAMs
A0-A14
DQ0-DQ7
W
E
M48T35
M48T35Y
Table 1. Signal Names
A0-A14
Address Inputs
Data Inputs / Outputs
Chip Enable
G
DQ0-DQ7
E
G
W
Output Enable
Write Enable
Supply Voltage
Ground
V
SS
AI01620B
V
CC
V
SS
February 2000
1/18
M48T35, M48T35Y
Figure 2A. DIP Connections
Figure 2B. SOIC Connections
A14
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 A13
25 A8
24 A9
23 A11
3
A13
A8
A6
A6
4
A5
A5
5
A9
A4
A4
6
A11
G
A3
22
G
A3
7
M48T35
M48T35Y
M48T35Y
A2
21 A10
A2
8
A10
E
A1
20
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
V
SS
SS
AI01621B
AI01622B
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
Grade 1
0 to 70
T
A
Ambient Operating Temperature
Grade 6
–40 to 85
–40 to 85
°C
T
Storage Temperature (V Off, Oscillator Off)
°C
STG
CC
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
260
–0.3 to 7
–0.3 to 7
20
°C
V
T
SLD
V
IO
V
V
CC
I
O
Output Current
mA
W
P
D
Power Dissipation
1
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
DESCRIPTION
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
®
The M48T35/35Y TIMEKEEPER RAM is a 32Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packag-
es to provide a highly integrated battery backed-up
memory and real time clock solution.
The M48T35/35Y is a non-volatile pin and function
equivalent to any JEDEC standard 32Kb x8
SRAM. It also easily fits into many ROM, EPROM,
The 28 pin 600mil DIP CAPHAT houses the
M48T35/35Y silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
2/18
M48T35, M48T35Y
(1)
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
CC
V
X
High Z
IH
4.75V to 5.5V
or
4.5V to 5.5V
V
IL
V
IL
V
IL
V
D
Active
IL
IH
IH
IN
V
IL
V
V
D
Read
Active
OUT
V
IH
Read
High Z
High Z
High Z
Active
(2)
Deselect
Deselect
X
X
X
CMOS Standby
Battery Back-up Mode
V
to V
(min)
PFD
SO
≤ V
X
X
X
SO
Note: 1. X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
2. See Table 7 for details.
Figure 3. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
DQ0-DQ7
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
V
CC
SS
AI01623
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery/crys-
tal packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28-
BR12SH1".
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T35/35Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE clock information in the bytes with ad-
dresses 7FF8h-7FFFh.
3/18
M48T35, M48T35Y
Table 4. AC Measurement Conditions
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no longer
driven.
1.9kΩ
DEVICE
UNDER
TEST
OUT
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year), 30, and 31
day months are made automatically. Byte 7FF8h
is the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting.
1kΩ
C
= 100pF or 5pF
L
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T35/35Y includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
C
includes JIG capacitance
L
AI01030
Access time (t
GLQV
) or Output Enable Access time
ELQV
(t
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
The M48T35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
, the data lines will be driven to an
AVQV
indeterminate state until t
.
AVQV
condition. When V is out of tolerance, the circuit
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
tem operation brought on by low V . As V falls
put Data Hold time (t
) but will go indetermi-
AXQX
CC
CC
below approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
nate until the next Address Access.
WRITE MODE
The M48T35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
READ MODE
The M48T35/35Y is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
of t
from Chip Enable or t
from Write En-
EHAX
WHAX
able prior to the initiation of another read or write
cycle. Data-in must be valid t prior to the end
time (t
) after the last address input signal is
AVQV
DVWH
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
of write and remain valid for t
afterward. G
WHDX
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs t
after W falls.
WLQZ
4/18
M48T35, M48T35Y
(1, 2)
Table 5. Capacitance
(T = 25 °C)
A
Symbol
Parameter
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
Input Capacitance
10
pF
IN
IN
(3)
V
OUT
Input / Output Capacitance
10
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
±1
µA
I
LI
IN
CC
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±5
50
3
µA
mA
mA
mA
V
I
OUT
LO
I
Outputs open
CC
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
CC1
IH
I
E = V – 0.2V
3
CC2
CC
(2)
–0.3
2.2
0.8
V
IL
V
V
V
+ 0.3
Input High Voltage
V
IH
CC
I
= 2.1mA
= –1mA
Output Low Voltage
0.4
V
OL
OH
OL
V
I
OH
Output High Voltage
2.4
V
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
4.5
4.2
Typ
Max
Unit
V
M48T35
4.6
4.35
3.0
4.75
4.5
V
PFD
Power-fail Deselect Voltage
M48T35Y
V
V
SO
Battery Back-up Switchover Voltage
V
(2)
Grade 1
Grade 6
YEARS
YEARS
10
10
Expected Data Retention Time
(at 25°C)
t
DR
(3)
Note: 1. All voltages referenced to V
.
SS
2. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top t = 7 years (typ).
DR
3. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
5/18
M48T35, M48T35Y
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
Max
Unit
t
E or W at V before Power Down
0
µs
PD
IH
(1)
V
(max) to V
(min) V Fall Time
300
10
µs
µs
t
PFD
PFD
PFD
PFD
CC
F
(2)
V
V
V
(min) to V
V
Fall Time
t
SS CC
FB
t
(min) to V
(max) V Rise Time
PFD CC
10
1
µs
µs
R
t
to V
(min) V Rise Time
PFD CC
RB
(3)
SS
V
(max) to Inputs Recognized
40
200
ms
t
PFD
REC
Note: 1. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
F CC
PFD
PFD
es V
(min).
PFD
2. V
3. t
(min) to V fall time of less than t may cause corruption of RAM data.
(min) = 20ms for industrial temperature grade (6) device.
PFD
REC
SS FB
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
tDR
tREC
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
6/18
M48T35, M48T35Y
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
M48T35 / M48T35Y
-70
Symbol
Parameter
Unit
Min
Max
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
(1)
Address Valid to Output Valid
70
70
35
t
t
AVQV
ELQV
GLQV
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
5
5
t
ELQX
GLQX
EHQZ
GHQZ
t
t
25
25
t
10
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
Figure 6. Read Mode AC Waveforms.
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: Write Enable (W) = High.
7/18
M48T35, M48T35Y
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
M48T35 / M48T35Y
-70
Symbol
Parameter
Unit
Min
70
0
Max
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
AVEL
t
50
55
0
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
WHDX
t
5
EHDX
(1, 2)
25
t
WLQZ
t
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
60
60
5
ns
ns
ns
AVWH
t
AVEH
(1, 2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
DATA RETENTION MODE
When V
drops below V , the control circuit
CC SO
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T35/35Y
for an accumulated period of at least 7 years when
With valid V applied, the M48T35/35Y operates
CC
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally power-fail deselect, write protecting itself
V
is less than V . As system power returns
CC
SO
when V
falls within the V
(max), V
(min)
CC
PFD
PFD
and V
rises above V , the battery is discon-
SO
CC
window. All outputs become high impedance, and
all inputs are treated as "don't care."
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
nected, and the power supply is switched to exter-
nal V . Write protection continues until V
CC
CC
reaches V
kept high as V
inadvertent write cycles prior to processor stabili-
zation. Normal RAM operation can resume t
(min) plus t
(min). E should be
PFD
REC
rises past V
(min) to prevent
CC
PFD
At voltages below V
(min), the user can be as-
PFD
REC
sured the memory will be in a write protected state,
after V exceeds V
(max).
CC
PFD
provided the V fall time is not less than tF. The
CC
For more information on Battery Storage Life refer
to the Application Note AN1012.
M48T35/35Y may respond to transient noise
spikes on V that reach into the deselect window
CC
during the time the device is sampling V . There-
CC
fore, decoupling of the power supply lines is rec-
ommended.
8/18
M48T35, M48T35Y
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
9/18
M48T35, M48T35Y
Table 11. Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
10 M
CB
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
7FFBh
7FFAh
7FF9h
7FF8h
10 Years
Year
Year
Month
Date
00-99
0
0
0
0
0
Month
01-12
01-31
10 Date
Date: Day of Month
Day of Week
0
FT
0
CEB
0
Century/Day 00-01/01-07
0
10 Hours
Hours (24 Hour Format)
Minutes
Hour
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
Minutes
Seconds
Control
ST
W
Seconds
R
Calibration
Keys: S = Sign Bit
FT = Frequency Test Bit (Must be set to ‘0’ upon power for normal operation)
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
CEB = Century Enable Bit
CB = Century Bit
Note: When CEB is set to ‘1’, CB will toggle from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of the century (dependent upon the initial value set).
When CEB is set to ‘0’, CB will not toggle.
The WRITE Bit does not need to be set to write to CEB and CB.
CLOCK OPERATIONS
allows normal operation to resume.The FT bit and
the bits marked as ’0’ in Table 11 must be written
to ’0’ to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next
clock update will occur within one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" on the for information
on Century Rollover.
Reading the Clock Updates to the TIMEKEEPER
registers should be halted before clock data is
read to prevent reading data in transition. Because
the BiPORT TIMEKEEPER cells in the RAM array
are only data registers, and not the actual clock
counters, updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T35/35Y is
shipped from STMicroelectronics with the STOP
bit set to a ’1’. When reset to a ’0’, the M48T35/35Y
oscillator starts within 1 second.
Calibrating the Clock
Setting the Clock
The M48T35/35Y is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed 35 ppm
(parts per million) oscillator frequency error at
25 °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T35/35Y improves to better
than ±4 ppm at 25 °C. The oscillation rate of any
crystal changes with temperature (see Figure 10).
Bit D7 of the Control Register 7FF8h is the WRITE
bit. Setting the WRITE bit to a ’1’, like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 11). Resetting the WRITE bit to a ’0’ then
transfers the values of all time registers 7FF9h-
7FFFh to the actual TIMEKEEPER counters and
10/18
M48T35, M48T35Y
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Most clock chips compensate for crystal frequency
and temperature shift error with cumbersome trim
capacitors. The M48T35/35Y design, however,
employs periodic counter correction. The calibra-
tion circuit adds or subtracts counts from the oscil-
lator divider circuit at the divide by 256 stage, as
shown in Figure 9. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
Two methods are available for ascertaining how
much calibration a given M48T35/35Y may re-
quire. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration byte.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768
Hz, each of the 31 increments in the Calibration
byte would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
The second approach is better suited to a manu-
facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register is set to a ’1’, and D7 of the Seconds Reg-
ister is a ’0’ (Oscillator Running), DQ0 will toggle at
512Hz during a read of the Seconds Register. Any
deviation from 512 Hz indicates the degree and di-
rection of oscillator frequency shift at the test tem-
perature. For example, a reading of 512.01024 Hz
would indicate a +20 ppm oscillator frequency er-
ror, requiring a –10 (WR001010) to be loaded into
the Calibration Byte for correction. Note that set-
ting or changing the Calibration Byte does not af-
fect the Frequency test output frequency.
The FT bit MUST be reset to '0' for normal clock
operations to resume. The FT bit is automatically
Reset on power-up.
For more information on calibration, see the Appli-
cation Note AN934 "TIMEKEEPER Calibration".
11/18
M48T35, M48T35Y
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
Figure 11. Supply Voltage Protection
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
V
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass ca-
pacitor value of 0.1µF (as shown in Figure 11) is
recommended in order to provide the needed fil-
tering.
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
V
SS
ative voltage spikes on V
that drive it to values
CC
below VSS by as much as one Volt. These nega-
tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V (cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
12/18
M48T35, M48T35Y
Table 12. Ordering Information Scheme
Example:
M48T35Y
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
(1)
35
= V = 4.75V to 5.5V; V
= 4.5V to 5.5V
PFD
CC
35Y = V = 4.5V to 5.5V; V
= 4.2V to 4.5V
CC
PFD
Speed
-70 = 70ns
Package
PC = PCDIP28
(2)
MH
= SOH28
Temperature Range
1 = 0 to 70 °C
(3)
6
= –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The M48T35 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR12SH1" in plastic tube or "M4TXX-BR12SH1TR" in Tape & Reel form.
3. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-cell bat-
tery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
November 1999 First Issue
t
Description changed (Table 7)
02/07/00
DR
13/18
M48T35, M48T35Y
Table 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
Figure 12. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale.
14/18
M48T35, M48T35Y
Table 15. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT,
Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 13. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
15/18
M48T35, M48T35Y
Table 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
3.20
0.018
0.835
0.560
0.126
0.080
D
E
eB
L
2.03
Figure 14. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK
Drawing is not to scale.
16/18
M48T35, M48T35Y
Table 17. M4T28-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
8.00
0.38
0.56
21.84
18.03
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
8.00
7.24
0.315
0.285
0.46
21.21
17.27
3.20
0.018
0.835
0.680
0.126
0.080
D
E
eB
L
2.03
Figure 15. M4T28-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK
Drawing is not to scale.
17/18
M48T35, M48T35Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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18/18
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